1 /* 2 * Generic board initialisation, based on uboot-xburst and xburst-tools. 3 * 4 * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de> 5 * Copyright (C) 2005-2006 Ingenic Semiconductor, <jlwei@ingenic.cn> 6 * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com> 7 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> 8 * 9 * This program is free software; you can redistribute it and/or modify it under 10 * the terms of the GNU General Public License as published by the Free Software 11 * Foundation; either version 3 of the License, or (at your option) any later 12 * version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 16 * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License along with 20 * this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #ifdef CONFIG_CPU_JZ4730 24 #include "jz4730.h" 25 #include "jz4730_compat.h" 26 #else 27 #include "jz4740.h" 28 #endif 29 30 #include "sdram.h" 31 #include "usb_boot_defines.h" 32 33 /* These arguments are initialised by usbboot and are defined in... 34 /etc/xburst-tools/usbboot.cfg. */ 35 36 struct fw_args *fw_args; 37 volatile u32 FW_CPU_ID; 38 volatile u8 FW_SDRAM_BW16; 39 volatile u8 FW_SDRAM_BANK4; 40 volatile u8 FW_SDRAM_ROW; 41 volatile u8 FW_SDRAM_COL; 42 volatile u8 FW_CONFIG_MOBILE_SDRAM; 43 volatile u8 FW_IS_SHARE; 44 45 void load_args(void) 46 { 47 /* Get the fw args from memory. See head1.S for the memory layout. */ 48 49 fw_args = (struct fw_args *)0x80002008; 50 FW_CPU_ID = fw_args->cpu_id ; 51 FW_SDRAM_BW16 = fw_args->bus_width; 52 FW_SDRAM_BANK4 = fw_args->bank_num; 53 FW_SDRAM_ROW = fw_args->row_addr; 54 FW_SDRAM_COL = fw_args->col_addr; 55 FW_CONFIG_MOBILE_SDRAM = fw_args->is_mobile; 56 FW_IS_SHARE = fw_args->is_busshare; 57 } 58 59 /* Initialisation functions. */ 60 61 void gpio_init(void) 62 { 63 /* 64 * Initialize NAND Flash Pins 65 */ 66 __gpio_as_nand(); 67 68 /* 69 * Initialize SDRAM pins 70 */ 71 __gpio_as_sdram_16bit_4720(); 72 } 73 74 void pll_init(void) 75 { 76 register unsigned int cfcr, plcr1; 77 int nf, pllout2; 78 79 /* See CPCCR (Clock Control Register). 80 * 0 == same frequency; 2 == f/3 81 */ 82 83 cfcr = CPM_CPCCR_CLKOEN | 84 CPM_CPCCR_PCS | 85 (0 << CPM_CPCCR_CDIV_BIT) | 86 (2 << CPM_CPCCR_HDIV_BIT) | 87 (2 << CPM_CPCCR_PDIV_BIT) | 88 (2 << CPM_CPCCR_MDIV_BIT) | 89 (2 << CPM_CPCCR_LDIV_BIT); 90 91 /* Init USB Host clock. 92 * Desired frequency == 48MHz 93 */ 94 95 #ifdef CONFIG_CPU_JZ4730 96 cfcr |= ((CFG_CPU_SPEED / 48000000 - 1) << 25); 97 #else 98 /* Determine the divider clock output based on the PCS bit. */ 99 pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2); 100 101 /* Divisor == UHCCDR + 1 */ 102 REG_CPM_UHCCDR = pllout2 / 48000000 - 1; 103 #endif 104 105 nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL; 106 plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ 107 (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ 108 (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ 109 CPM_CPPCR_PLLEN; /* enable PLL */ 110 111 /* Update PLL and wait. */ 112 113 REG_CPM_CPCCR = cfcr; 114 REG_CPM_CPPCR = plcr1; 115 while (!__cpm_pll_is_on()); 116 } 117 118 void sdram_init(void) 119 { 120 register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; 121 unsigned int pllout = __cpm_get_pllout(); 122 123 unsigned int cas_latency_sdmr[2] = { 124 EMC_SDMR_CAS_2, 125 EMC_SDMR_CAS_3, 126 }; 127 128 unsigned int cas_latency_dmcr[2] = { 129 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ 130 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ 131 }; 132 133 /* Divisors for CPCCR values. */ 134 135 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; 136 137 cpu_clk = pllout / div[__cpm_get_cdiv()]; 138 mem_clk = pllout / div[__cpm_get_mdiv()]; 139 140 REG_EMC_BCR = 0; /* Disable bus release */ 141 REG_EMC_RTCSR = 0; /* Disable clock for counting */ 142 143 /* Fault DMCR value for mode register setting*/ 144 dmcr0 = (0<<EMC_DMCR_RA_BIT) | 145 (0<<EMC_DMCR_CA_BIT) | 146 (0<<EMC_DMCR_BA_BIT) | 147 (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) | 148 EMC_DMCR_EPIN | 149 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 150 151 /* Basic DMCR value */ 152 dmcr = ((FW_SDRAM_ROW-SDRAM_ROW0)<<EMC_DMCR_RA_BIT) | 153 ((FW_SDRAM_COL-SDRAM_COL0)<<EMC_DMCR_CA_BIT) | 154 ((FW_SDRAM_BANK4-SDRAM_BANK40)<<EMC_DMCR_BA_BIT) | 155 (FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) | 156 EMC_DMCR_EPIN | 157 cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; 158 159 /* SDRAM timimg */ 160 ns = 1000000000 / mem_clk; 161 tmp = SDRAM_TRAS/ns; 162 if (tmp < 4) tmp = 4; 163 if (tmp > 11) tmp = 11; 164 dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); 165 tmp = SDRAM_RCD/ns; 166 if (tmp > 3) tmp = 3; 167 dmcr |= (tmp << EMC_DMCR_RCD_BIT); 168 tmp = SDRAM_TPC/ns; 169 if (tmp > 7) tmp = 7; 170 dmcr |= (tmp << EMC_DMCR_TPC_BIT); 171 tmp = SDRAM_TRWL/ns; 172 if (tmp > 3) tmp = 3; 173 dmcr |= (tmp << EMC_DMCR_TRWL_BIT); 174 tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; 175 if (tmp > 14) tmp = 14; 176 dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); 177 178 /* SDRAM mode value */ 179 sdmode = EMC_SDMR_BT_SEQ | 180 EMC_SDMR_OM_NORMAL | 181 EMC_SDMR_BL_4 | 182 cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; 183 184 /* jz4730 additional measures */ 185 #ifdef CONFIG_CPU_JZ4730 186 if (FW_SDRAM_BW16) 187 sdmode <<= 1; 188 else 189 sdmode <<= 2; 190 #endif 191 192 /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ 193 REG_EMC_DMCR = dmcr; 194 REG8(EMC_SDMR0|sdmode) = 0; 195 196 /* jz4730 additional measures */ 197 #ifdef CONFIG_CPU_JZ4730 198 REG8(EMC_SDMR1|sdmode) = 0; 199 #endif 200 201 /* Wait for precharge, > 200us */ 202 tmp = (cpu_clk / 1000000) * 1000; 203 while (tmp--); 204 205 /* Stage 2. Enable auto-refresh */ 206 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; 207 208 tmp = SDRAM_TREF/ns; 209 tmp = tmp/64 + 1; 210 if (tmp > 0xff) tmp = 0xff; 211 REG_EMC_RTCOR = tmp; 212 REG_EMC_RTCNT = 0; 213 REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ 214 215 /* Wait for number of auto-refresh cycles */ 216 tmp = (cpu_clk / 1000000) * 1000; 217 while (tmp--); 218 219 /* Stage 3. Mode Register Set */ 220 REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 221 REG8(EMC_SDMR0|sdmode) = 0; 222 223 /* jz4730 additional measures */ 224 #ifdef CONFIG_CPU_JZ4730 225 REG8(EMC_SDMR1|sdmode) = 0; 226 #endif 227 228 /* Set back to basic DMCR value */ 229 REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; 230 231 /* everything is ok now */ 232 }