NanoPayload

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Properly reset the TLB mappings.
Moved the task management and the example task into separate files.
Introduced convenience headers for configuration-related file selection.
Renamed board-specific.h to init.h.
Moved board-specific timer operations to the appropriate files.
Allow task zero to plot a pattern and to run with the other tasks.
Moved paging definitions into a new header file, adjusting the table address.
Switched to using stacks accessible via the same virtual address region.
Switched to mapped stack regions, keeping stack pointers within their regions.
Added missing multiplication registers to loading and storing.
Added explicit clearing of TLB mappings.
Fixed page table indexing in the TLB miss handler.
Introduced kernel regions for task register storage.
Removed superfluous TLB mapping entry.
Put the page tables and the stacks in unmapped space, with the stacks occupying
Tidied up stack location calculations.
Added a generic exception handler to handle TLB misses during exceptions.
Minor formatting changes.
Fixed absent EPC initialisation.
Permit different test patterns.
Masking interrupts should not be necessary.
Introduced more immediate TLB miss handling in order to avoid stack usage and
Added a potentially useful TLB page miss mapping function.
Introduced a method of invoking task routines for testing.
Added elements of a task switching mechanism.
Introduced the start of a more complicated page mapping scheme.
Separated error level and interrupt initialisation.
Added missing ASID sections to EntryHi register values.
Moved status register saving and adjustment, saving the unmodified value.
Make a copy of the global offset table for user mode use.
Attempt to prevent a system hang by saving certain registers early.
Ensure that the GP is set up appropriately for interrupt and TLB miss handling.
Disable user mode transitions for now.
Fixed the operation of the enter_user_mode function.
Merged changes from the branch upon reverting to position-independent code.
Switched to position-independent code to enable user mode execution. stage2-non-pic
Pass parameters to the plot_pattern function. stage2-non-pic
Merged fixes. stage2-non-pic
Fixed initial TLB mapping. stage2-non-pic
Moved tlb_handle into the interrupt handling file. Added an idle wait loop. stage2-non-pic
Added index-based page mapping and page unmapping functions, allowing flags and stage2-non-pic
Removed spurious initial TLB mapping, exposing the actual replacement mechanism. stage2-non-pic
Enter user mode before starting the task. stage2-non-pic
Introduced elementary TLB handling; separated out register saving and loading. stage2-non-pic
Introduced a page mapping function. stage2-non-pic
Converted various multi-line macros into inline functions. stage2-non-pic
Removed probably superfluous no-operations and tidied slightly. stage2-non-pic
Mask interrupts while handling them, saving the status and EPC registers. stage2-non-pic
Allow the power button to trigger an interrupt, although handling does not work. stage2-non-pic
Employ normal GPIO level-testing to affect the test pattern, with the power stage2-non-pic
Attempted unsuccessfully to use GPIO interrupts. stage2-non-pic
Added a function to set the pixel depth for future use. stage2-non-pic
Correct bpp discrepancy. stage2-non-pic
Experiment with a different test pattern. stage2-non-pic
Supported 4bpp modes with a simple 121 4-bit RGB mapping. stage2-non-pic
Made the palette size correspond to the pixel depth. stage2-non-pic
Added support for 8bpp output with a simple 332 8-bit RGB palette mapping. stage2-non-pic
Added 16bpp support, fixed/improved dual panel support, handled apparent stage2-non-pic
Fixed region mapping comment. stage2-non-pic
Merged the allocated memory regions into one. stage2-non-pic
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