# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1462395476 -7200
# Node ID 010e441bc874e01d9c4e32b55b6cbd0e313e4e45
# Parent  dcf9647a9edceb7652c36373d4fe2ea4ac7afdfe
Added definitions for register fields.

diff -r dcf9647a9edc -r 010e441bc874 include/mips.h
--- a/include/mips.h	Wed May 04 22:07:41 2016 +0200
+++ b/include/mips.h	Wed May 04 22:57:56 2016 +0200
@@ -16,4 +16,12 @@
 #define CP0_TAGLO	$28
 #define CP0_TAGHI	$29
 
+#define STATUS_BEV	0x00400000
+#define STATUS_IRQ	0xfc00
+#define STATUS_ERL	4
+#define STATUS_EXL	2
+#define STATUS_IE	1
+
+#define CAUSE_IV	0x00800000
+
 #endif /* __MIPS_H__ */
diff -r dcf9647a9edc -r 010e441bc874 stage2/cpu_op.S
--- a/stage2/cpu_op.S	Wed May 04 22:07:41 2016 +0200
+++ b/stage2/cpu_op.S	Wed May 04 22:57:56 2016 +0200
@@ -78,7 +78,7 @@
 
 handle_error_level:
 	mfc0 $t3, CP0_STATUS
-	li $t4, 0xfffffffb	/* ERL = 0 */
+	li $t4, ~STATUS_ERL
 	and $t3, $t3, $t4
 	mtc0 $t3, CP0_STATUS
 	jr $ra
@@ -88,8 +88,7 @@
 
 enable_interrupts:
 	mfc0 $t3, CP0_STATUS
-	li $t4, 0x0000fc01	/* IE = enable interrupts */
-	or $t3, $t3, $t4
+	ori $t3, $t3, STATUS_IRQ | STATUS_IE
 	mtc0 $t3, CP0_STATUS
 	jr $ra
 	nop
@@ -101,10 +100,10 @@
 	/* Set exception registers. */
 
 	mtc0 $zero, CP0_WATCHLO
-	li $t3, 0x00800000	/* IV = 1 (use 0x80000200 for interrupts) */
+	li $t3, CAUSE_IV	/* IV = 1 (use 0x80000200 for interrupts) */
 	mtc0 $t3, CP0_CAUSE
 	mfc0 $t4, CP0_STATUS
-	li $t3, 0xffbfffff	/* BEV=0 */
+	li $t3, ~STATUS_BEV
 	and $t3, $t3, $t4
 	mtc0 $t3, CP0_STATUS
 	jr $ra
@@ -128,7 +127,7 @@
 	lw $gp, 104($t3)
 	mtc0 $t9, CP0_EPC
 	mfc0 $t3, CP0_STATUS
-	ori $t3, $t3, 0x2	/* EXL = 1 */
+	ori $t3, $t3, STATUS_EXL
 	mtc0 $t3, CP0_STATUS
 	eret
 	nop