# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1462399144 -7200
# Node ID 174153b3fcbc9ec2775d5f29a52e74ec868caffa
# Parent  bc3ddcefdc42c0315b97afc3c6600a9bd5d848d1
Allow the TLB random mapping threshold to be specified.

diff -r bc3ddcefdc42 -r 174153b3fcbc stage2/cpu.c
--- a/stage2/cpu.c	Wed May 04 23:35:03 2016 +0200
+++ b/stage2/cpu.c	Wed May 04 23:59:04 2016 +0200
@@ -73,9 +73,9 @@
 	base[29] = (u32) function - 0x80000000;	/* store the function address as EPC (for the handler) */
 }
 
-void init_tlb(void)
+void init_tlb(u8 first_random)
 {
-	u32 limit = configure_tlb(), i;
+	u32 limit = configure_tlb(first_random), i;
 
 	/* Reset the mappings. The total number is bits 30..25 of Config1. */
 
diff -r bc3ddcefdc42 -r 174153b3fcbc stage2/cpu.h
--- a/stage2/cpu.h	Wed May 04 23:35:03 2016 +0200
+++ b/stage2/cpu.h	Wed May 04 23:59:04 2016 +0200
@@ -5,7 +5,7 @@
 
 void flush_cache_all();
 void init_registers(u32 *, u32, void (*)(), u32[], u8);
-void init_tlb();
+void init_tlb(u8);
 void init_page_table(u32, u32, u32, u32, u8, u8);
 void map_page(u32, u32, u32, u8, u8);
 void map_page_index(u32, u32, u32, u8, u8, u32);
diff -r bc3ddcefdc42 -r 174153b3fcbc stage2/cpu_op.S
--- a/stage2/cpu_op.S	Wed May 04 23:35:03 2016 +0200
+++ b/stage2/cpu_op.S	Wed May 04 23:59:04 2016 +0200
@@ -136,7 +136,7 @@
 
 configure_tlb:
 	mtc0 $zero, CP0_CONTEXT
-	mtc0 $zero, CP0_WIRED	/* first random entry is zero */
+	mtc0 $a0, CP0_WIRED	/* first random entry is defined by the parameter */
 	mfc0 $v0, CP0_CONFIG	/* return the limit */
 	jr $ra
 	nop
diff -r bc3ddcefdc42 -r 174153b3fcbc stage2/cpu_op.h
--- a/stage2/cpu_op.h	Wed May 04 23:35:03 2016 +0200
+++ b/stage2/cpu_op.h	Wed May 04 23:59:04 2016 +0200
@@ -11,7 +11,7 @@
 void enable_interrupts();
 void init_interrupts();
 void invoke_task(u8, u32 *, u32 *);
-u32 configure_tlb();
+u32 configure_tlb(u32);
 void map_page_set_index(u32);
 void map_page_op(u32, u32, u32, u32);
 void map_page_index_op(u32, u32, u32, u32);
diff -r bc3ddcefdc42 -r 174153b3fcbc stage2/stage2.c
--- a/stage2/stage2.c	Wed May 04 23:35:03 2016 +0200
+++ b/stage2/stage2.c	Wed May 04 23:59:04 2016 +0200
@@ -30,7 +30,7 @@
 {
 	volatile int started;
 
-	init_tlb();
+	init_tlb(0);
 	flush_cache_all();
 
 	/* The actual work. */