# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1499611709 -7200
# Node ID 1871eb0ee98c257d6a965ec807bc22000306377e
# Parent  36caaaf8aecf2e288ced66498a4ddf7fadf1397c
Fixed erroneous clock and power management operations.

diff -r 36caaaf8aecf -r 1871eb0ee98c stage2/jzlcd.c
--- a/stage2/jzlcd.c	Sun Jul 09 16:00:26 2017 +0200
+++ b/stage2/jzlcd.c	Sun Jul 09 16:48:29 2017 +0200
@@ -366,7 +366,7 @@
 
 #ifdef CONFIG_CPU_JZ4730
         val = __cpm_get_pllout() / pclk;
-        lcd_ctrl_set(vid, CPM_CFCR2, val - 1);
+        REG_CPM_CFCR2 = val - 1;
         val = pclk * 4 ;
         if ( val > 150000000 ) {
                 val = 150000000;
@@ -378,7 +378,7 @@
 #else
 	int pll_div;
 
-	pll_div = lcd_ctrl_get(vid, CPM_CPCCR) & lcd_ctrl_get(vid, CPM_CPCCR_PCS); /* clock source,0:pllout/2 1: pllout */
+	pll_div = REG_CPM_CPCCR & CPM_CPCCR_PCS; /* clock source,0:pllout/2 1: pllout */
 	pll_div = pll_div ? 1 : 2 ;
 	val = ( __cpm_get_pllout()/pll_div ) / pclk;
 	val--;
@@ -398,7 +398,7 @@
 	}
 #endif
 	__cpm_set_ldiv( val );
-	lcd_ctrl_set(vid, CPM_CPCCR, lcd_ctrl_get(vid, CPM_CPCCR) | CPM_CPCCR_CE); /* update divide */
+	REG_CPM_CPCCR = REG_CPM_CPCCR | CPM_CPCCR_CE; /* update divide */
 }
 
 /* Initialise the LCD controller with the memory, panel and framebuffer details.