# HG changeset patch # User Paul Boddie # Date 1433626191 -7200 # Node ID 2b0ffb019036cac219fa979944257587c5838c72 # Parent ea2af6a8d4bd8e3867d9705e6d530337f7941418 Added RTC, timer and initial LCD support. diff -r ea2af6a8d4bd -r 2b0ffb019036 Makefile --- a/Makefile Sat Jun 06 18:03:55 2015 +0200 +++ b/Makefile Sat Jun 06 23:29:51 2015 +0200 @@ -42,9 +42,9 @@ # Ordering of objects is important and cannot be left to replacement rules. SRC1 = head1.S stage1.c board-nanonote.c -SRC2 = head2.S stage2.c board-nanonote.c +SRC2 = head2.S stage2.c board-nanonote.c nanonote_gpm940b0.c OBJ1 = head1.o stage1.o board-nanonote.o -OBJ2 = head2.o stage2.o board-nanonote.o +OBJ2 = head2.o stage2.o board-nanonote.o nanonote_gpm940b0.o OBJ = $(OBJ1) $(OBJ2) .PHONY: all clean distclean diff -r ea2af6a8d4bd -r 2b0ffb019036 board-nanonote.c --- a/board-nanonote.c Sat Jun 06 18:03:55 2015 +0200 +++ b/board-nanonote.c Sat Jun 06 23:29:51 2015 +0200 @@ -3,7 +3,8 @@ * * Copyright (C) 2015 Paul Boddie * Copyright (C) Xiangfu Liu - * Copyright (c) 2006 Ingenic Semiconductor, + * Copyright (C) 2006 Ingenic Semiconductor, + * Copyright (C) 2003 Wolfgang Denk, DENX Software Engineering, * * This program is free software; you can redistribute it and/or modify it under * the terms of the GNU General Public License as published by the Free Software @@ -234,3 +235,232 @@ /* everything is ok now */ } + +void rtc_init(void) +{ + while ( !__rtc_write_ready()) ; + __rtc_enable_alarm(); /* enable alarm */ + + while ( !__rtc_write_ready()) + ; + REG_RTC_RGR = 0x00007fff; /* type value */ + + while ( !__rtc_write_ready()) + ; + REG_RTC_HWFCR = 0x0000ffe0; /* Power on delay 2s */ + + while ( !__rtc_write_ready()) + ; + REG_RTC_HRCR = 0x00000fe0; /* reset delay 125ms */ +} + +/* + * Timer routines + */ + +#define TIMER_CHAN 0 +#define TIMER_FDATA 0xffff /* Timer full data value */ +#define TIMER_HZ CONFIG_SYS_HZ + +#define READ_TIMER REG_TCU_TCNT(TIMER_CHAN) /* macro to read the 16 bit timer */ + +static unsigned long timestamp; +static unsigned long lastdec; + +void reset_timer_masked(void); +unsigned long get_timer_masked(void); +void udelay_masked(unsigned long usec); + +/* + * timer without interrupts + */ + +int timer_init(void) +{ + REG_TCU_TCSR(TIMER_CHAN) = TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN; + REG_TCU_TCNT(TIMER_CHAN) = 0; + REG_TCU_TDHR(TIMER_CHAN) = 0; + REG_TCU_TDFR(TIMER_CHAN) = TIMER_FDATA; + + REG_TCU_TMSR = (1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)); /* mask irqs */ + REG_TCU_TSCR = (1 << TIMER_CHAN); /* enable timer clock */ + REG_TCU_TESR = (1 << TIMER_CHAN); /* start counting up */ + + lastdec = 0; + timestamp = 0; + + return 0; +} + +void reset_timer(void) +{ + reset_timer_masked (); +} + +unsigned long get_timer(unsigned long base) +{ + return get_timer_masked () - base; +} + +void set_timer(unsigned long t) +{ + timestamp = t; +} + +void udelay (unsigned long usec) +{ + unsigned long tmo,tmp; + + /* normalize */ + if (usec >= 1000) { + tmo = usec / 1000; + tmo *= TIMER_HZ; + tmo /= 1000; + } + else { + if (usec >= 1) { + tmo = usec * TIMER_HZ; + tmo /= (1000*1000); + } + else + tmo = 1; + } + + /* check for rollover during this delay */ + tmp = get_timer (0); + if ((tmp + tmo) < tmp ) + reset_timer_masked(); /* timer would roll over */ + else + tmo += tmp; + + while (get_timer_masked () < tmo); +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = READ_TIMER; + timestamp = 0; +} + +unsigned long get_timer_masked (void) +{ + unsigned long now = READ_TIMER; + + if (lastdec <= now) { + /* normal mode */ + timestamp += (now - lastdec); + } else { + /* we have an overflow ... */ + timestamp += TIMER_FDATA + now - lastdec; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked (unsigned long usec) +{ + unsigned long tmo; + unsigned long endtime; + signed long diff; + + /* normalize */ + if (usec >= 1000) { + tmo = usec / 1000; + tmo *= TIMER_HZ; + tmo /= 1000; + } else { + if (usec > 1) { + tmo = usec * TIMER_HZ; + tmo /= (1000*1000); + } else { + tmo = 1; + } + } + + endtime = get_timer_masked () + tmo; + + do { + unsigned long now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On MIPS it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On MIPS it returns the number of timer ticks per second. + */ +unsigned long get_tbclk (void) +{ + return TIMER_HZ; +} + +/* CPU-specific routines from U-Boot. + See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c + See: u-boot/arch/mips/include/asm/cacheops.h +*/ + +#define Index_Store_Tag_I 0x08 +#define Index_Writeback_Inv_D 0x15 + +void flush_icache_all(void) +{ + u32 addr, t = 0; + + asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ + asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ + + for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; + addr += CONFIG_SYS_CACHELINE_SIZE) { + asm volatile ( + ".set mips3\n\t" + " cache %0, 0(%1)\n\t" + ".set mips2\n\t" + : + : "I" (Index_Store_Tag_I), "r"(addr)); + } + + /* invalicate btb */ + asm volatile ( + ".set mips32\n\t" + "mfc0 %0, $16, 7\n\t" + "nop\n\t" + "ori %0,2\n\t" + "mtc0 %0, $16, 7\n\t" + ".set mips2\n\t" + : + : "r" (t)); +} + +void flush_dcache_all(void) +{ + u32 addr; + + for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; + addr += CONFIG_SYS_CACHELINE_SIZE) { + asm volatile ( + ".set mips3\n\t" + " cache %0, 0(%1)\n\t" + ".set mips2\n\t" + : + : "I" (Index_Writeback_Inv_D), "r"(addr)); + } + + asm volatile ("sync"); +} + +void flush_cache_all(void) +{ + flush_dcache_all(); + flush_icache_all(); +} diff -r ea2af6a8d4bd -r 2b0ffb019036 board-nanonote.h --- a/board-nanonote.h Sat Jun 06 18:03:55 2015 +0200 +++ b/board-nanonote.h Sat Jun 06 23:29:51 2015 +0200 @@ -2,8 +2,13 @@ #define __BOARD_NANONOTE_H__ void gpio_init(void); +void gpio_init2(void); void cpm_init(void); void pll_init(void); void sdram_init(void); +void rtc_init(void); +int timer_init(void); +void udelay(unsigned long usec); +void flush_cache_all(void); #endif /* __BOARD_NANONOTE_H__ */ diff -r ea2af6a8d4bd -r 2b0ffb019036 include/jz4740.h --- a/include/jz4740.h Sat Jun 06 18:03:55 2015 +0200 +++ b/include/jz4740.h Sat Jun 06 23:29:51 2015 +0200 @@ -3214,12 +3214,18 @@ #define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_DISABLE) #define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE) +/* NOTE: Independent of usbboot parameters. */ + +#define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */ +#define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */ +#define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */ #ifdef CONFIG_SYS_EXTAL #define JZ_EXTAL CONFIG_SYS_EXTAL #else #define JZ_EXTAL 3686400 #endif + #define JZ_EXTAL2 32768 /* RTC clock */ /* PLL output frequency */ diff -r ea2af6a8d4bd -r 2b0ffb019036 include/lcd.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/include/lcd.h Sat Jun 06 23:29:51 2015 +0200 @@ -0,0 +1,84 @@ +/* + * U-Boot JzRISC lcd controller definitions + * + * (C) Copyright 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * (C) Copyright Xiangfu Liu + * (C) Copyright 2015 Paul Boddie + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _LCD_H_ +#define _LCD_H_ + +/* + * LCD controller stucture for JZSOC: JZ4740 + */ +struct jz_fb_dma_descriptor { + unsigned long fdadr; /* Frame descriptor address register */ + unsigned long fsadr; /* Frame source address register */ + unsigned long fidr; /* Frame ID register */ + unsigned long ldcmd; /* Command register */ +}; + +/* + * Jz LCD info + */ +struct jz_fb_info { + + unsigned long fdadr0; /* physical address of frame/palette descriptor */ + unsigned long fdadr1; /* physical address of frame descriptor */ + + /* DMA descriptors */ + struct jz_fb_dma_descriptor * dmadesc_fblow; + struct jz_fb_dma_descriptor * dmadesc_fbhigh; + struct jz_fb_dma_descriptor * dmadesc_palette; + unsigned long screen; /* address of frame buffer */ + unsigned long palette; /* address of palette memory */ + unsigned int palette_size; +}; + +typedef struct vidinfo { + unsigned short vl_col; /* Number of columns (i.e. 640) */ + unsigned short vl_row; /* Number of rows (i.e. 480) */ + unsigned char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */ + + struct jz_fb_info jz_fb; +} vidinfo_t; + +extern vidinfo_t panel_info; + +#define LCD_MONOCHROME 0 +#define LCD_COLOR2 1 +#define LCD_COLOR4 2 +#define LCD_COLOR8 3 +#define LCD_COLOR16 4 +#define LCD_COLOR32 5 + +/* Default to 8bpp if bit depth not specified */ +#ifndef LCD_BPP +#define LCD_BPP LCD_COLOR8 +#endif + +#ifndef PAGE_SIZE +#define PAGE_SIZE 4096 +#endif + +/* Calculate nr. of bits per pixel and nr. of colors */ +#define NBITS(bit_code) (1 << (bit_code)) +#define NCOLORS(bit_code) (1 << NBITS(bit_code)) + +#endif /* _LCD_H_ */ diff -r ea2af6a8d4bd -r 2b0ffb019036 include/nanonote.h --- a/include/nanonote.h Sat Jun 06 18:03:55 2015 +0200 +++ b/include/nanonote.h Sat Jun 06 23:29:51 2015 +0200 @@ -1,5 +1,6 @@ /* - * Authors: Xiangfu Liu + * Copyright (C) Xiangfu Liu + * Copyright (C) 2015 Paul Boddie * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -14,31 +15,40 @@ #define __CONFIG_NANONOTE_H /* + * Cache Configuration + */ +#define CONFIG_SYS_DCACHE_SIZE 16384 +#define CONFIG_SYS_ICACHE_SIZE 16384 +#define CONFIG_SYS_CACHELINE_SIZE 32 +#define KSEG0 0x80000000 + +/* * GPIO definition * See: http://en.qi-hardware.com/wiki/Hardware_basics */ -#define GPIO_LCD_CS (2 * 32 + 21) -#define GPIO_AMP_EN (3 * 32 + 4) +#define GPIO_LCD_CS (2 * 32 + 21) +#define GPIO_AMP_EN (3 * 32 + 4) -#define GPIO_SDPW_EN (3 * 32 + 2) -#define GPIO_SD_DETECT (3 * 32 + 0) +#define GPIO_SDPW_EN (3 * 32 + 2) +#define GPIO_SD_DETECT (3 * 32 + 0) -#define GPIO_BUZZ_PWM (3 * 32 + 27) -#define GPIO_USB_DETECT (3 * 32 + 28) +#define GPIO_BUZZ_PWM (3 * 32 + 27) +#define GPIO_USB_DETECT (3 * 32 + 28) -#define GPIO_AUDIO_POP (1 * 32 + 29) -#define GPIO_COB_TEST (1 * 32 + 30) +#define GPIO_AUDIO_POP (1 * 32 + 29) +#define GPIO_COB_TEST (1 * 32 + 30) -#define GPIO_KEYOUT_BASE (2 * 32 + 10) -#define GPIO_KEYIN_BASE (3 * 32 + 18) -#define GPIO_KEYIN_8 (3 * 32 + 26) +#define GPIO_KEYOUT_BASE (2 * 32 + 10) +#define GPIO_KEYIN_BASE (3 * 32 + 18) +#define GPIO_KEYIN_8 (3 * 32 + 26) -#define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */ -#define GPIO_SD_VCC_EN_N GPIO_SDPW_EN /* SD Card Power Enable */ +#define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */ +#define GPIO_SD_VCC_EN_N GPIO_SDPW_EN /* SD Card Power Enable */ -#define GPIO_SD_CMD (3 * 32 + 8) +#define GPIO_SD_CMD (3 * 32 + 8) -#define SPEN GPIO_LCD_CS /* LCDCS :Serial command enable */ -#define SPDA (2 * 32 + 22) /* LCDSCL:Serial command clock input */ -#define SPCK (2 * 32 + 23) /* LCDSDA:Serial command data input */ +#define SPEN GPIO_LCD_CS /* LCDCS :Serial command enable */ +#define SPDA (2 * 32 + 22) /* LCDSCL:Serial command clock input */ +#define SPCK (2 * 32 + 23) /* LCDSDA:Serial command data input */ + #endif /* __CONFIG_NANONOTE_H */ diff -r ea2af6a8d4bd -r 2b0ffb019036 nanonote_gpm940b0.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/nanonote_gpm940b0.c Sat Jun 06 23:29:51 2015 +0200 @@ -0,0 +1,415 @@ +/* + * JzRISC lcd controller + * + * Xiangfu Liu + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "lcd.h" + +/* virt_to_phys() from u-boot/arch/mips/include/asm/addrspace.h + via u-boot/arch/mips/include/asm/io.h */ +#define virt_to_phys(n) (((int) n) & 0x1fffffff) + +#include "jz4740.h" +#include "nanonote_gpm940b0.h" +#include "board-nanonote.h" + +#define align2(n) (n)=((((n)+1)>>1)<<1) +#define align4(n) (n)=((((n)+3)>>2)<<2) +#define align8(n) (n)=((((n)+7)>>3)<<3) + +struct jzfb_info { + unsigned int cfg; /* panel mode and pin usage etc. */ + unsigned int w; + unsigned int h; + unsigned int bpp; /* bit per pixel */ + unsigned int fclk; /* frame clk */ + unsigned int hsw; /* hsync width, in pclk */ + unsigned int vsw; /* vsync width, in line count */ + unsigned int elw; /* end of line, in pclk */ + unsigned int blw; /* begin of line, in pclk */ + unsigned int efw; /* end of frame, in line count */ + unsigned int bfw; /* begin of frame, in line count */ +}; + +static struct jzfb_info jzfb = { + MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N, + 320, 240, 32, 70, 1, 1, 273, 140, 1, 20 +}; + +vidinfo_t panel_info = { + 320, 240, LCD_BPP, +}; + +int lcd_line_length; +int lcd_color_fg; +int lcd_color_bg; +/* + * Frame buffer memory information + */ +void *lcd_base; /* Start of framebuffer memory */ +void *lcd_console_address; /* Start of console buffer */ + +short console_col; +short console_row; + +void lcd_ctrl_init (void *lcdbase); +void lcd_enable (void); +void lcd_disable (void); + +static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid); +static void jz_lcd_desc_init(vidinfo_t *vid); +static int jz_lcd_hw_init(vidinfo_t *vid); +/* extern int flush_cache_all(void); */ + +void lcd_ctrl_init (void *lcdbase) +{ + jz_lcd_init_mem(lcdbase, &panel_info); + jz_lcd_desc_init(&panel_info); + jz_lcd_hw_init(&panel_info); +} + +/* + * Before enabled lcd controller, lcd registers should be configured correctly. + */ +void lcd_enable (void) +{ + REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */ + REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/ +} + +void lcd_disable (void) +{ + REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */ + /* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */ +} + +static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid) +{ + unsigned long palette_mem_size; + struct jz_fb_info *fbi = &vid->jz_fb; + int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8; + + fbi->screen = (unsigned long)lcdbase; + fbi->palette_size = 256; + palette_mem_size = fbi->palette_size * sizeof(u16); + + /* debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (unsigned long) palette_mem_size); */ + /* locate palette and descs at end of page following fb */ + fbi->palette = (unsigned long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size; + + return 0; +} + +static void jz_lcd_desc_init(vidinfo_t *vid) +{ + struct jz_fb_info * fbi; + fbi = &vid->jz_fb; + fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16); + fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16); + fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16); + + #define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8) + + /* populate descriptors */ + fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow); + fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL)); + fbi->dmadesc_fblow->fidr = 0; + fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ; + + fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */ + + fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen); + fbi->dmadesc_fbhigh->fidr = 0; + fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */ + + fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette); + fbi->dmadesc_palette->fidr = 0; + fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28); + + if(NBITS(vid->vl_bpix) < 12) + { + /* assume any mode with <12 bpp is palette driven */ + fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh); + fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette); + /* flips back and forth between pal and fbhigh */ + fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette); + } else { + /* palette shouldn't be loaded in true-color mode */ + fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh); + fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */ + } + + flush_cache_all(); +} + +static int jz_lcd_hw_init(vidinfo_t *vid) +{ + struct jz_fb_info *fbi = &vid->jz_fb; + unsigned int val = 0; + unsigned int pclk; + unsigned int stnH; + int pll_div; + + /* Setting Control register */ + switch (jzfb.bpp) { + case 1: + val |= LCD_CTRL_BPP_1; + break; + case 2: + val |= LCD_CTRL_BPP_2; + break; + case 4: + val |= LCD_CTRL_BPP_4; + break; + case 8: + val |= LCD_CTRL_BPP_8; + break; + case 15: + val |= LCD_CTRL_RGB555; + case 16: + val |= LCD_CTRL_BPP_16; + break; + case 17 ... 32: + val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */ + break; + + default: + /* printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp); */ + val |= LCD_CTRL_BPP_16; + break; + } + + switch (jzfb.cfg & MODE_MASK) { + case MODE_STN_MONO_DUAL: + case MODE_STN_COLOR_DUAL: + case MODE_STN_MONO_SINGLE: + case MODE_STN_COLOR_SINGLE: + switch (jzfb.bpp) { + case 1: + /* val |= LCD_CTRL_PEDN; */ + case 2: + val |= LCD_CTRL_FRC_2; + break; + case 4: + val |= LCD_CTRL_FRC_4; + break; + case 8: + default: + val |= LCD_CTRL_FRC_16; + break; + } + break; + } + + val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */ + val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */ + + switch (jzfb.cfg & MODE_MASK) { + case MODE_STN_MONO_DUAL: + case MODE_STN_COLOR_DUAL: + case MODE_STN_MONO_SINGLE: + case MODE_STN_COLOR_SINGLE: + switch (jzfb.cfg & STN_DAT_PINMASK) { + case STN_DAT_PIN1: + /* Do not adjust the hori-param value. */ + break; + case STN_DAT_PIN2: + align2(jzfb.hsw); + align2(jzfb.elw); + align2(jzfb.blw); + break; + case STN_DAT_PIN4: + align4(jzfb.hsw); + align4(jzfb.elw); + align4(jzfb.blw); + break; + case STN_DAT_PIN8: + align8(jzfb.hsw); + align8(jzfb.elw); + align8(jzfb.blw); + break; + } + break; + } + + REG_LCD_CTRL = val; + + switch (jzfb.cfg & MODE_MASK) { + case MODE_STN_MONO_DUAL: + case MODE_STN_COLOR_DUAL: + case MODE_STN_MONO_SINGLE: + case MODE_STN_COLOR_SINGLE: + if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) || + ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) + stnH = jzfb.h >> 1; + else + stnH = jzfb.h; + + REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; + REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw); + + /* Screen setting */ + REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw); + REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w); + REG_LCD_DAV = (0 << 16) | (stnH); + + /* AC BIAs signal */ + REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw); + + break; + + case MODE_TFT_GEN: + case MODE_TFT_SHARP: + case MODE_TFT_CASIO: + case MODE_TFT_SAMSUNG: + case MODE_8BIT_SERIAL_TFT: + case MODE_TFT_18BIT: + REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; + REG_LCD_HSYNC = (0 << 16) | jzfb.hsw; + REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h); + REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w ); + REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \ + | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw); + break; + } + + switch (jzfb.cfg & MODE_MASK) { + case MODE_TFT_SAMSUNG: + { + unsigned int total, tp_s, tp_e, ckv_s, ckv_e; + unsigned int rev_s, rev_e, inv_s, inv_e; + + pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * + (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ + + total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; + tp_s = jzfb.blw + jzfb.w + 1; + tp_e = tp_s + 1; + /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */ + ckv_s = tp_s - pclk/(1000000000/4100); + ckv_e = tp_s + total; + rev_s = tp_s - 11; /* -11.5 clk */ + rev_e = rev_s + total; + inv_s = tp_s; + inv_e = inv_s + total; + REG_LCD_CLS = (tp_s << 16) | tp_e; + REG_LCD_PS = (ckv_s << 16) | ckv_e; + REG_LCD_SPL = (rev_s << 16) | rev_e; + REG_LCD_REV = (inv_s << 16) | inv_e; + jzfb.cfg |= STFT_REVHI | STFT_SPLHI; + break; + } + case MODE_TFT_SHARP: + { + unsigned int total, cls_s, cls_e, ps_s, ps_e; + unsigned int spl_s, spl_e, rev_s, rev_e; + total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; + spl_s = 1; + spl_e = spl_s + 1; + cls_s = 0; + cls_e = total - 60; /* > 4us (pclk = 80ns) */ + ps_s = cls_s; + ps_e = cls_e; + rev_s = total - 40; /* > 3us (pclk = 80ns) */ + rev_e = rev_s + total; + jzfb.cfg |= STFT_PSHI; + REG_LCD_SPL = (spl_s << 16) | spl_e; + REG_LCD_CLS = (cls_s << 16) | cls_e; + REG_LCD_PS = (ps_s << 16) | ps_e; + REG_LCD_REV = (rev_s << 16) | rev_e; + break; + } + case MODE_TFT_CASIO: + break; + } + + /* Configure the LCD panel */ + REG_LCD_CFG = jzfb.cfg; + + /* Timing setting */ + __cpm_stop_lcd(); + + val = jzfb.fclk; /* frame clk */ + if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) { + pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * + (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ + } else { + /* serial mode: Hsync period = 3*Width_Pixel */ + pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) * + (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ + } + + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || + ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) + pclk = (pclk * 3); + + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || + ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) || + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) + pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4); + + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) + pclk >>= 1; + + pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */ + pll_div = pll_div ? 1 : 2 ; + val = ( __cpm_get_pllout()/pll_div ) / pclk; + val--; + if ( val > 0x1ff ) { + /* printf("CPM_LPCDR too large, set it to 0x1ff\n"); */ + val = 0x1ff; + } + __cpm_set_pixdiv(val); + + val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */ + if ( val > 150000000 ) { + /* printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val); */ + /* printf("Change LCDClock to 150MHz\n"); */ + val = 150000000; + } + val = ( __cpm_get_pllout()/pll_div ) / val; + val--; + if ( val > 0x1f ) { + /* printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n"); */ + val = 0x1f; + } + __cpm_set_ldiv( val ); + REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */ + + __cpm_start_lcd(); + udelay(1000); + + REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/ + + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) + REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/ + + return 0; +} + +void lcd_setcolreg (unsigned short regno, unsigned short red, unsigned short green, unsigned short blue) +{ +} + +void lcd_initcolregs (void) +{ +} diff -r ea2af6a8d4bd -r 2b0ffb019036 nanonote_gpm940b0.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/nanonote_gpm940b0.h Sat Jun 06 23:29:51 2015 +0200 @@ -0,0 +1,135 @@ +/* + * JzRISC lcd controller + * + * Xiangfu Liu + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __QI_LB60_GPM940B0_H__ +#define __QI_LB60_GPM940B0_H__ + +struct lcd_desc{ + unsigned int next_desc; /* LCDDAx */ + unsigned int databuf; /* LCDSAx */ + unsigned int frame_id; /* LCDFIDx */ + unsigned int cmd; /* LCDCMDx */ +}; + +#define MODE_MASK 0x0f +#define MODE_TFT_GEN 0x00 +#define MODE_TFT_SHARP 0x01 +#define MODE_TFT_CASIO 0x02 +#define MODE_TFT_SAMSUNG 0x03 +#define MODE_CCIR656_NONINT 0x04 +#define MODE_CCIR656_INT 0x05 +#define MODE_STN_COLOR_SINGLE 0x08 +#define MODE_STN_MONO_SINGLE 0x09 +#define MODE_STN_COLOR_DUAL 0x0a +#define MODE_STN_MONO_DUAL 0x0b +#define MODE_8BIT_SERIAL_TFT 0x0c + +#define MODE_TFT_18BIT (1<<7) + +#define STN_DAT_PIN1 (0x00 << 4) +#define STN_DAT_PIN2 (0x01 << 4) +#define STN_DAT_PIN4 (0x02 << 4) +#define STN_DAT_PIN8 (0x03 << 4) +#define STN_DAT_PINMASK STN_DAT_PIN8 + +#define STFT_PSHI (1 << 15) +#define STFT_CLSHI (1 << 14) +#define STFT_SPLHI (1 << 13) +#define STFT_REVHI (1 << 12) + +#define SYNC_MASTER (0 << 16) +#define SYNC_SLAVE (1 << 16) + +#define DE_P (0 << 9) +#define DE_N (1 << 9) + +#define PCLK_P (0 << 10) +#define PCLK_N (1 << 10) + +#define HSYNC_P (0 << 11) +#define HSYNC_N (1 << 11) + +#define VSYNC_P (0 << 8) +#define VSYNC_N (1 << 8) + +#define DATA_NORMAL (0 << 17) +#define DATA_INVERSE (1 << 17) + + +/* Jz LCDFB supported I/O controls. */ +#define FBIOSETBACKLIGHT 0x4688 +#define FBIODISPON 0x4689 +#define FBIODISPOFF 0x468a +#define FBIORESET 0x468b +#define FBIOPRINT_REG 0x468c + +/* + * LCD panel specific definition + */ +#define MODE (0xc9) /* 8bit serial RGB */ + +#define __spi_write_reg1(reg, val) \ +do { \ + unsigned char no; \ + unsigned short value; \ + unsigned char a=reg; \ + unsigned char b=val; \ + __gpio_set_pin(SPEN); \ + __gpio_set_pin(SPCK); \ + __gpio_clear_pin(SPDA); \ + __gpio_clear_pin(SPEN); \ + value=((a<<8)|(b&0xFF)); \ + for(no=0;no<16;no++) \ + { \ + __gpio_clear_pin(SPCK); \ + if((value&0x8000)==0x8000) \ + __gpio_set_pin(SPDA); \ + else \ + __gpio_clear_pin(SPDA); \ + __gpio_set_pin(SPCK); \ + value=(value<<1); \ + } \ + __gpio_set_pin(SPEN); \ +} while (0) + +#define __lcd_display_pin_init() \ +do { \ + __cpm_start_tcu(); \ + __gpio_as_output(SPEN); /* use SPDA */ \ + __gpio_as_output(SPCK); /* use SPCK */ \ + __gpio_as_output(SPDA); /* use SPDA */ \ +} while (0) + +#define __lcd_display_on() \ +do { \ + __spi_write_reg1(0x05, 0x1e); \ + __spi_write_reg1(0x05, 0x5e); \ + __spi_write_reg1(0x07, 0x8d); \ + __spi_write_reg1(0x13, 0x01); \ + __spi_write_reg1(0x05, 0x5f); \ +} while (0) + +#define __lcd_display_off() \ +do { \ + __spi_write_reg1(0x05, 0x5e); \ +} while (0) + +#endif /* __QI_LB60_GPM940B0_H__ */ diff -r ea2af6a8d4bd -r 2b0ffb019036 stage2.c --- a/stage2.c Sat Jun 06 18:03:55 2015 +0200 +++ b/stage2.c Sat Jun 06 23:29:51 2015 +0200 @@ -41,6 +41,8 @@ void c_main(void) { - __gpio_as_output(GPIO_SD_CMD); - __gpio_set_pin(GPIO_SD_CMD); + gpio_init2(); + cpm_init(); + rtc_init(); + timer_init(); }