# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1499608826 -7200
# Node ID 36caaaf8aecf2e288ced66498a4ddf7fadf1397c
# Parent  d41c05accd390d4923fb5b8fdcf9cd5a7d7210e5
Make LCD register access relative to a supplied base parameter.

diff -r d41c05accd39 -r 36caaaf8aecf include/jz4740.h
--- a/include/jz4740.h	Sun Jul 09 01:47:02 2017 +0200
+++ b/include/jz4740.h	Sun Jul 09 16:00:26 2017 +0200
@@ -2080,49 +2080,8 @@
 /*************************************************************************
  * LCD (LCD Controller)
  *************************************************************************/
-#define LCD_CFG		(LCD_BASE + 0x00) /* LCD Configure Register */
-#define LCD_VSYNC	(LCD_BASE + 0x04) /* Vertical Synchronize Register */
-#define LCD_HSYNC	(LCD_BASE + 0x08) /* Horizontal Synchronize Register */
-#define LCD_VAT		(LCD_BASE + 0x0c) /* Virtual Area Setting Register */
-#define LCD_DAH		(LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */
-#define LCD_DAV		(LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */
-#define LCD_PS		(LCD_BASE + 0x18) /* PS Signal Setting */
-#define LCD_CLS		(LCD_BASE + 0x1c) /* CLS Signal Setting */
-#define LCD_SPL		(LCD_BASE + 0x20) /* SPL Signal Setting */
-#define LCD_REV		(LCD_BASE + 0x24) /* REV Signal Setting */
-#define LCD_CTRL	(LCD_BASE + 0x30) /* LCD Control Register */
-#define LCD_STATE	(LCD_BASE + 0x34) /* LCD Status Register */
-#define LCD_IID		(LCD_BASE + 0x38) /* Interrupt ID Register */
-#define LCD_DA0		(LCD_BASE + 0x40) /* Descriptor Address Register 0 */
-#define LCD_SA0		(LCD_BASE + 0x44) /* Source Address Register 0 */
-#define LCD_FID0	(LCD_BASE + 0x48) /* Frame ID Register 0 */
-#define LCD_CMD0	(LCD_BASE + 0x4c) /* DMA Command Register 0 */
-#define LCD_DA1		(LCD_BASE + 0x50) /* Descriptor Address Register 1 */
-#define LCD_SA1		(LCD_BASE + 0x54) /* Source Address Register 1 */
-#define LCD_FID1	(LCD_BASE + 0x58) /* Frame ID Register 1 */
-#define LCD_CMD1	(LCD_BASE + 0x5c) /* DMA Command Register 1 */
-
-#define REG_LCD_CFG	REG32(LCD_CFG)
-#define REG_LCD_VSYNC	REG32(LCD_VSYNC)
-#define REG_LCD_HSYNC	REG32(LCD_HSYNC)
-#define REG_LCD_VAT	REG32(LCD_VAT)
-#define REG_LCD_DAH	REG32(LCD_DAH)
-#define REG_LCD_DAV	REG32(LCD_DAV)
-#define REG_LCD_PS	REG32(LCD_PS)
-#define REG_LCD_CLS	REG32(LCD_CLS)
-#define REG_LCD_SPL	REG32(LCD_SPL)
-#define REG_LCD_REV	REG32(LCD_REV)
-#define REG_LCD_CTRL	REG32(LCD_CTRL)
-#define REG_LCD_STATE	REG32(LCD_STATE)
-#define REG_LCD_IID	REG32(LCD_IID)
-#define REG_LCD_DA0	REG32(LCD_DA0)
-#define REG_LCD_SA0	REG32(LCD_SA0)
-#define REG_LCD_FID0	REG32(LCD_FID0)
-#define REG_LCD_CMD0	REG32(LCD_CMD0)
-#define REG_LCD_DA1	REG32(LCD_DA1)
-#define REG_LCD_SA1	REG32(LCD_SA1)
-#define REG_LCD_FID1	REG32(LCD_FID1)
-#define REG_LCD_CMD1	REG32(LCD_CMD1)
+
+/* Register definitions with absolute positioning have been removed. */
 
 /* LCD Configure Register */
 #define LCD_CFG_LCDPIN_BIT	31  /* LCD pins selection */
diff -r d41c05accd39 -r 36caaaf8aecf stage2/jzlcd.c
--- a/stage2/jzlcd.c	Sun Jul 09 01:47:02 2017 +0200
+++ b/stage2/jzlcd.c	Sun Jul 09 16:00:26 2017 +0200
@@ -632,7 +632,7 @@
 
 	fb_vaddr = (void *) lcd_get_framebuffer(0, vid);
 
-	jz_lcd_ctrl_init(0, fb_vaddr, vid);
+	jz_lcd_ctrl_init((void *) LCD_BASE_KSEG1, fb_vaddr, vid);
 	flush_cache_all();
 	jz_lcd_hw_init(vid);
 	jz_lcd_timing_init(vid);
diff -r d41c05accd39 -r 36caaaf8aecf stage2/jzlcd.h
--- a/stage2/jzlcd.h	Sun Jul 09 01:47:02 2017 +0200
+++ b/stage2/jzlcd.h	Sun Jul 09 16:00:26 2017 +0200
@@ -136,6 +136,34 @@
 #define DATA_NORMAL	(0 << 17)
 #define DATA_INVERSE	(1 << 17)
 
+/* LCD register base. */
+
+#define LCD_BASE_KSEG1		0xB3050000
+
+/* Register offsets. */
+
+#define LCD_CFG			0x00 /* LCD Configure Register */
+#define LCD_VSYNC		0x04 /* Vertical Synchronize Register */
+#define LCD_HSYNC		0x08 /* Horizontal Synchronize Register */
+#define LCD_VAT			0x0c /* Virtual Area Setting Register */
+#define LCD_DAH			0x10 /* Display Area Horizontal Start/End Point */
+#define LCD_DAV			0x14 /* Display Area Vertical Start/End Point */
+#define LCD_PS			0x18 /* PS Signal Setting */
+#define LCD_CLS			0x1c /* CLS Signal Setting */
+#define LCD_SPL			0x20 /* SPL Signal Setting */
+#define LCD_REV			0x24 /* REV Signal Setting */
+#define LCD_CTRL		0x30 /* LCD Control Register */
+#define LCD_STATE		0x34 /* LCD Status Register */
+#define LCD_IID			0x38 /* Interrupt ID Register */
+#define LCD_DA0			0x40 /* Descriptor Address Register 0 */
+#define LCD_SA0			0x44 /* Source Address Register 0 */
+#define LCD_FID0		0x48 /* Frame ID Register 0 */
+#define LCD_CMD0		0x4c /* DMA Command Register 0 */
+#define LCD_DA1			0x50 /* Descriptor Address Register 1 */
+#define LCD_SA1			0x54 /* Source Address Register 1 */
+#define LCD_FID1		0x58 /* Frame ID Register 1 */
+#define LCD_CMD1		0x5c /* DMA Command Register 1 */
+
 /* Palette buffer (LCD_CMDx.PAL). */
 
 #define LCD_CMD_PAL		(1 << 28)