# HG changeset patch # User Paul Boddie # Date 1499617875 -7200 # Node ID 58cf8c659804597a2a4c29b82930a40ee1a8b669 # Parent 2b8d17cf5a881ae745831d5902b5dc5549c81170 Removed superfluous definitions. diff -r 2b8d17cf5a88 -r 58cf8c659804 include/jz4730.h --- a/include/jz4730.h Sun Jul 09 17:14:00 2017 +0200 +++ b/include/jz4730.h Sun Jul 09 18:31:15 2017 +0200 @@ -4,7 +4,7 @@ * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc. * Copyright (C) 2009 Qi Hardware Inc. * Author: Xiangfu Liu - * Copyright (C) 2015 Paul Boddie + * Copyright (C) 2015, 2017 Paul Boddie * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -2044,49 +2044,8 @@ /************************************************************************* * LCD *************************************************************************/ -#define LCD_CFG (LCD_BASE + 0x00) -#define LCD_VSYNC (LCD_BASE + 0x04) -#define LCD_HSYNC (LCD_BASE + 0x08) -#define LCD_VAT (LCD_BASE + 0x0c) -#define LCD_DAH (LCD_BASE + 0x10) -#define LCD_DAV (LCD_BASE + 0x14) -#define LCD_PS (LCD_BASE + 0x18) -#define LCD_CLS (LCD_BASE + 0x1c) -#define LCD_SPL (LCD_BASE + 0x20) -#define LCD_REV (LCD_BASE + 0x24) -#define LCD_CTRL (LCD_BASE + 0x30) -#define LCD_STATE (LCD_BASE + 0x34) -#define LCD_IID (LCD_BASE + 0x38) -#define LCD_DA0 (LCD_BASE + 0x40) -#define LCD_SA0 (LCD_BASE + 0x44) -#define LCD_FID0 (LCD_BASE + 0x48) -#define LCD_CMD0 (LCD_BASE + 0x4c) -#define LCD_DA1 (LCD_BASE + 0x50) -#define LCD_SA1 (LCD_BASE + 0x54) -#define LCD_FID1 (LCD_BASE + 0x58) -#define LCD_CMD1 (LCD_BASE + 0x5c) - -#define REG_LCD_CFG REG32(LCD_CFG) -#define REG_LCD_VSYNC REG32(LCD_VSYNC) -#define REG_LCD_HSYNC REG32(LCD_HSYNC) -#define REG_LCD_VAT REG32(LCD_VAT) -#define REG_LCD_DAH REG32(LCD_DAH) -#define REG_LCD_DAV REG32(LCD_DAV) -#define REG_LCD_PS REG32(LCD_PS) -#define REG_LCD_CLS REG32(LCD_CLS) -#define REG_LCD_SPL REG32(LCD_SPL) -#define REG_LCD_REV REG32(LCD_REV) -#define REG_LCD_CTRL REG32(LCD_CTRL) -#define REG_LCD_STATE REG32(LCD_STATE) -#define REG_LCD_IID REG32(LCD_IID) -#define REG_LCD_DA0 REG32(LCD_DA0) -#define REG_LCD_SA0 REG32(LCD_SA0) -#define REG_LCD_FID0 REG32(LCD_FID0) -#define REG_LCD_CMD0 REG32(LCD_CMD0) -#define REG_LCD_DA1 REG32(LCD_DA1) -#define REG_LCD_SA1 REG32(LCD_SA1) -#define REG_LCD_FID1 REG32(LCD_FID1) -#define REG_LCD_CMD1 REG32(LCD_CMD1) + +/* Register definitions with absolute positioning have been removed. */ #define LCD_CFG_PDW_BIT 4 #define LCD_CFG_PDW_MASK (0x03 << LCD_DEV_PDW_BIT) @@ -4508,215 +4467,7 @@ * LCD ***************************************************************************/ -#define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS ) -#define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS ) - -#define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA ) -#define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA ) - -/* n=1,2,4,8,16 */ -#define __lcd_set_bpp(n) \ - ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n ) - -/* n=4,8,16 */ -#define __lcd_set_burst_length(n) \ -do { \ - REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \ - REG_LCD_CTRL |= LCD_CTRL_BST_n##; \ -} while (0) - -#define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 ) -#define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 ) - -#define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP ) -#define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP ) - -/* n=2,4,16 */ -#define __lcd_set_stn_frc(n) \ -do { \ - REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \ - REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \ -} while (0) - - -#define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN ) -#define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN ) - -#define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN ) -#define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN ) - -#define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM ) -#define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM ) - -#define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM ) -#define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM ) - -#define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM ) -#define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM ) - -#define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 ) -#define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 ) - -#define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 ) -#define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 ) - -#define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM ) -#define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM ) - -#define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM ) -#define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM ) - - -/* LCD status register indication */ - -#define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD ) -#define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD ) -#define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 ) -#define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 ) -#define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU ) -#define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF ) -#define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF ) - -#define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU ) -#define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF ) -#define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF ) - -#define __lcd_panel_white() ( REG_LCD_DEV |= LCD_DEV_WHITE ) -#define __lcd_panel_black() ( REG_LCD_DEV &= ~LCD_DEV_WHITE ) - -/* n=1,2,4,8 for single mono-STN - * n=4,8 for dual mono-STN - */ -#define __lcd_set_panel_datawidth(n) \ -do { \ - REG_LCD_DEV &= ~LCD_DEV_PDW_MASK; \ - REG_LCD_DEV |= LCD_DEV_PDW_n##; \ -} while (0) - -/* m=LCD_DEV_MODE_GENERUIC_TFT_xxx */ -#define __lcd_set_panel_mode(m) \ -do { \ - REG_LCD_DEV &= ~LCD_DEV_MODE_MASK; \ - REG_LCD_DEV |= (m); \ -} while(0) - -/* n = 0-255 */ -#define __lcd_disable_ac_bias() ( REG_LCD_IO = 0xff ) -#define __lcd_set_ac_bias(n) \ -do { \ - REG_LCD_IO &= ~LCD_IO_ACB_MASK; \ - REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT); \ -} while(0) - -#define __lcd_io_set_dir() ( REG_LCD_IO |= LCD_IO_DIR ) -#define __lcd_io_clr_dir() ( REG_LCD_IO &= ~LCD_IO_DIR ) - -#define __lcd_io_set_dep() ( REG_LCD_IO |= LCD_IO_DEP ) -#define __lcd_io_clr_dep() ( REG_LCD_IO &= ~LCD_IO_DEP ) - -#define __lcd_io_set_vsp() ( REG_LCD_IO |= LCD_IO_VSP ) -#define __lcd_io_clr_vsp() ( REG_LCD_IO &= ~LCD_IO_VSP ) - -#define __lcd_io_set_hsp() ( REG_LCD_IO |= LCD_IO_HSP ) -#define __lcd_io_clr_hsp() ( REG_LCD_IO &= ~LCD_IO_HSP ) - -#define __lcd_io_set_pcp() ( REG_LCD_IO |= LCD_IO_PCP ) -#define __lcd_io_clr_pcp() ( REG_LCD_IO &= ~LCD_IO_PCP ) - -#define __lcd_vsync_get_vps() \ - ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT ) - -#define __lcd_vsync_get_vpe() \ - ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT ) -#define __lcd_vsync_set_vpe(n) \ -do { \ - REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \ - REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \ -} while (0) - -#define __lcd_hsync_get_hps() \ - ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT ) -#define __lcd_hsync_set_hps(n) \ -do { \ - REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \ - REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \ -} while (0) - -#define __lcd_hsync_get_hpe() \ - ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT ) -#define __lcd_hsync_set_hpe(n) \ -do { \ - REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \ - REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \ -} while (0) - -#define __lcd_vat_get_ht() \ - ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT ) -#define __lcd_vat_set_ht(n) \ -do { \ - REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \ - REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \ -} while (0) - -#define __lcd_vat_get_vt() \ - ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT ) -#define __lcd_vat_set_vt(n) \ -do { \ - REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \ - REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \ -} while (0) - -#define __lcd_dah_get_hds() \ - ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT ) -#define __lcd_dah_set_hds(n) \ -do { \ - REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \ - REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \ -} while (0) - -#define __lcd_dah_get_hde() \ - ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT ) -#define __lcd_dah_set_hde(n) \ -do { \ - REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \ - REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \ -} while (0) - -#define __lcd_dav_get_vds() \ - ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT ) -#define __lcd_dav_set_vds(n) \ -do { \ - REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \ - REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \ -} while (0) - -#define __lcd_dav_get_vde() \ - ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT ) -#define __lcd_dav_set_vde(n) \ -do { \ - REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \ - REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \ -} while (0) - -#define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT ) -#define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT ) -#define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT ) -#define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT ) - -#define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT ) -#define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT ) -#define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT ) -#define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT ) - -#define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL ) -#define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL ) - -#define __lcd_cmd0_get_len() \ - ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) -#define __lcd_cmd1_get_len() \ - ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) - - +/* Register operations using absolute positioning have been removed. */ /*************************************************************************** * DES diff -r 2b8d17cf5a88 -r 58cf8c659804 include/jz4740.h --- a/include/jz4740.h Sun Jul 09 17:14:00 2017 +0200 +++ b/include/jz4740.h Sun Jul 09 18:31:15 2017 +0200 @@ -177,6 +177,9 @@ /************************************************************************* * CPM (Clock reset and Power control Management) *************************************************************************/ + +/* Register definitions with absolute positioning have been removed. */ + #define CPM_CPCCR (CPM_BASE+0x00) #define CPM_CPPCR (CPM_BASE+0x10) #define CPM_I2SCDR (CPM_BASE+0x60) @@ -4327,216 +4330,8 @@ /*************************************************************************** * LCD ***************************************************************************/ -#define __lcd_as_smart_lcd() ( REG_LCD_CFG |= (1<> LCD_VSYNC_VPS_BIT ) - -#define __lcd_vsync_get_vpe() \ - ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT ) -#define __lcd_vsync_set_vpe(n) \ -do { \ - REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \ - REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \ -} while (0) - -#define __lcd_hsync_get_hps() \ - ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT ) -#define __lcd_hsync_set_hps(n) \ -do { \ - REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \ - REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \ -} while (0) - -#define __lcd_hsync_get_hpe() \ - ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT ) -#define __lcd_hsync_set_hpe(n) \ -do { \ - REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \ - REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \ -} while (0) - -#define __lcd_vat_get_ht() \ - ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT ) -#define __lcd_vat_set_ht(n) \ -do { \ - REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \ - REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \ -} while (0) - -#define __lcd_vat_get_vt() \ - ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT ) -#define __lcd_vat_set_vt(n) \ -do { \ - REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \ - REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \ -} while (0) - -#define __lcd_dah_get_hds() \ - ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT ) -#define __lcd_dah_set_hds(n) \ -do { \ - REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \ - REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \ -} while (0) - -#define __lcd_dah_get_hde() \ - ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT ) -#define __lcd_dah_set_hde(n) \ -do { \ - REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \ - REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \ -} while (0) - -#define __lcd_dav_get_vds() \ - ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT ) -#define __lcd_dav_set_vds(n) \ -do { \ - REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \ - REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \ -} while (0) - -#define __lcd_dav_get_vde() \ - ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT ) -#define __lcd_dav_set_vde(n) \ -do { \ - REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \ - REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \ -} while (0) - -#define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT ) -#define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT ) -#define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT ) -#define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT ) - -#define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT ) -#define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT ) -#define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT ) -#define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT ) - -#define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL ) -#define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL ) - -#define __lcd_cmd0_get_len() \ - ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) -#define __lcd_cmd1_get_len() \ - ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT ) + +/* Register operations using absolute positioning have been removed. */ /*************************************************************************** * RTC ops