# HG changeset patch # User Paul Boddie # Date 1433711168 -7200 # Node ID 5d33753dfd71a239c231a99f43f6d1d5d39974a4 # Parent 9469cf34aec2b38c541f1f99d5845a547242dfb2 Separated the stages into separate directories in order to employ different compilation options, principally to introduce the object relocation technique apparently required by stage 2. diff -r 9469cf34aec2 -r 5d33753dfd71 Makefile --- a/Makefile Sun Jun 07 20:17:24 2015 +0200 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,78 +0,0 @@ -# Makefile - Build the NanoNote payload -# -# Copyright (C) 2015 Paul Boddie -# Copyright (C) Xiangfu Liu -# -# This program is free software; you can redistribute it and/or modify it under -# the terms of the GNU General Public License as published by the Free Software -# Foundation; either version 3 of the License, or (at your option) any later -# version. -# -# This program is distributed in the hope that it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS -# FOR A PARTICULAR PURPOSE. See the GNU General Public License for more -# details. -# -# You should have received a copy of the GNU General Public License along with -# this program. If not, see . - -ARCH = mipsel-linux-gnu -CC = $(ARCH)-gcc -LD = $(ARCH)-ld -NM = $(ARCH)-nm -OBJCOPY=$(ARCH)-objcopy -OBJDUMP=$(ARCH)-objdump - -# NOTE: -O2 is actually needed to prevent memcpy references, whereas probably -# NOTE: one of the -f{freestanding, no-hosted, no-builtin} options should work. -# NOTE: See: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=56888 - -ASM_INC = /usr/src/linux-headers-4.0.0-1-common/arch/mips/include -CFLAGS = -O2 -Wall -fno-unit-at-a-time -fno-zero-initialized-in-bss \ - -ffreestanding -fno-hosted -fno-builtin \ - -march=mips32 -mno-abicalls \ - -Iinclude -I$(ASM_INC) -I$(ASM_INC)/asm/mach-generic -LDFLAGS = -nostdlib -EL - -PAYLOAD = stage1.bin stage2.bin -TARGET = $(PAYLOAD:.bin=.elf) -DUMP = $(PAYLOAD:.bin=.dump) -MAP = $(PAYLOAD:.bin=.map) - -# Ordering of objects is important and cannot be left to replacement rules. - -SRC1 = head1.S stage1.c board-nanonote.c -SRC2 = head2.S stage2.c board-nanonote2.c nanonote_gpm940b0.c lcd.c -OBJ1 = head1.o stage1.o board-nanonote.o -OBJ2 = head2.o stage2.o board-nanonote2.o nanonote_gpm940b0.o lcd.o -OBJ = $(OBJ1) $(OBJ2) - -.PHONY: all clean distclean - -all: $(PAYLOAD) - -clean: - rm -f $(OBJ) $(TARGET) $(PAYLOAD) $(DUMP) *.map - -distclean: clean - echo "Nothing else to clean." - -$(PAYLOAD): $(TARGET) - $(OBJCOPY) -O binary $(@:.bin=.elf) $@+ - $(OBJDUMP) -D $(@:.bin=.elf) > $(@:.bin=.dump) - $(OBJDUMP) -h $(@:.bin=.elf) > $(@:.bin=.map) - $(NM) -n $(@:.bin=.elf) > System-$(@:.bin=.map) - chmod -x $@+ - mv -f $@+ $@ - -stage1.elf: $(OBJ1) - $(LD) $(LDFLAGS) -T $(@:.elf=.ld) $(OBJ1) -o $@ - -stage2.elf: $(OBJ2) - $(LD) $(LDFLAGS) -T $(@:.elf=.ld) $(OBJ2) -o $@ - -.c.o: - $(CC) -c $(CFLAGS) $< -o $@ - -.S.o: - $(CC) -c $(CFLAGS) $< -o $@ diff -r 9469cf34aec2 -r 5d33753dfd71 board-nanonote.c --- a/board-nanonote.c Sun Jun 07 20:17:24 2015 +0200 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,210 +0,0 @@ -/* - * Ben NanoNote board initialisation, based on uboot-xburst and xburst-tools. - * - * Copyright (C) 2015 Paul Boddie - * Copyright (C) Xiangfu Liu - * Copyright (C) 2006 Ingenic Semiconductor, - * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License as published by the Free Software - * Foundation; either version 3 of the License, or (at your option) any later - * version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#include "jz4740.h" -#include "configs.h" -#include "nanonote.h" -#include "usb_boot_defines.h" - -/* These arguments are initialised by usbboot and are defined in... - /etc/xburst-tools/usbboot.cfg. */ - -struct fw_args *fw_args; -volatile u32 CPU_ID; -volatile u8 SDRAM_BW16; -volatile u8 SDRAM_BANK4; -volatile u8 SDRAM_ROW; -volatile u8 SDRAM_COL; -volatile u8 CONFIG_MOBILE_SDRAM; -volatile u8 IS_SHARE; - -void load_args(void) -{ - /* Get the fw args from memory. See head1.S for the memory layout. */ - - fw_args = (struct fw_args *)0x80002008; - CPU_ID = fw_args->cpu_id ; - SDRAM_BW16 = fw_args->bus_width; - SDRAM_BANK4 = fw_args->bank_num; - SDRAM_ROW = fw_args->row_addr; - SDRAM_COL = fw_args->col_addr; - CONFIG_MOBILE_SDRAM = fw_args->is_mobile; - IS_SHARE = fw_args->is_busshare; -} - -/* Initialisation functions. */ - -void gpio_init(void) -{ - /* - * Initialize NAND Flash Pins - */ - __gpio_as_nand(); - - /* - * Initialize SDRAM pins - */ - __gpio_as_sdram_16bit_4720(); -} - -void pll_init(void) -{ - register unsigned int cfcr, plcr1; - int nf, pllout2; - - /* See CPCCR (Clock Control Register). - * 0 == same frequency; 2 == f/3 - */ - - cfcr = CPM_CPCCR_CLKOEN | - CPM_CPCCR_PCS | - (0 << CPM_CPCCR_CDIV_BIT) | - (2 << CPM_CPCCR_HDIV_BIT) | - (2 << CPM_CPCCR_PDIV_BIT) | - (2 << CPM_CPCCR_MDIV_BIT) | - (2 << CPM_CPCCR_LDIV_BIT); - - /* Determine the divider clock output based on the PCS bit. */ - - pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2); - - /* Init USB Host clock. - * Divisor == UHCCDR + 1 - * Desired frequency == 48MHz - */ - - REG_CPM_UHCCDR = pllout2 / 48000000 - 1; - - nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL; - plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ - (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ - (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ - CPM_CPPCR_PLLEN; /* enable PLL */ - - /* Update PLL and wait. */ - - REG_CPM_CPCCR = cfcr; - REG_CPM_CPPCR = plcr1; - while (!__cpm_pll_is_on()); -} - -void sdram_init(void) -{ - register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; - unsigned int pllout = __cpm_get_pllout(); - - unsigned int cas_latency_sdmr[2] = { - EMC_SDMR_CAS_2, - EMC_SDMR_CAS_3, - }; - - unsigned int cas_latency_dmcr[2] = { - 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ - 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ - }; - - /* Divisors for CPCCR values. */ - - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - - cpu_clk = pllout / div[__cpm_get_cdiv()]; - mem_clk = pllout / div[__cpm_get_mdiv()]; - - REG_EMC_BCR = 0; /* Disable bus release */ - REG_EMC_RTCSR = 0; /* Disable clock for counting */ - - /* Fault DMCR value for mode register setting*/ -#define SDRAM_ROW0 11 -#define SDRAM_COL0 8 -#define SDRAM_BANK40 0 - - dmcr0 = ((SDRAM_ROW0-11)< 11) tmp = 11; - dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); - tmp = SDRAM_RCD/ns; - if (tmp > 3) tmp = 3; - dmcr |= (tmp << EMC_DMCR_RCD_BIT); - tmp = SDRAM_TPC/ns; - if (tmp > 7) tmp = 7; - dmcr |= (tmp << EMC_DMCR_TPC_BIT); - tmp = SDRAM_TRWL/ns; - if (tmp > 3) tmp = 3; - dmcr |= (tmp << EMC_DMCR_TRWL_BIT); - tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; - if (tmp > 14) tmp = 14; - dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); - - /* SDRAM mode value */ - sdmode = EMC_SDMR_BT_SEQ | - EMC_SDMR_OM_NORMAL | - EMC_SDMR_BL_4 | - cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; - - /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ - REG_EMC_DMCR = dmcr; - REG8(EMC_SDMR0|sdmode) = 0; - - /* Wait for precharge, > 200us */ - tmp = (cpu_clk / 1000000) * 1000; - while (tmp--); - - /* Stage 2. Enable auto-refresh */ - REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; - - tmp = SDRAM_TREF/ns; - tmp = tmp/64 + 1; - if (tmp > 0xff) tmp = 0xff; - REG_EMC_RTCOR = tmp; - REG_EMC_RTCNT = 0; - REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ - - /* Wait for number of auto-refresh cycles */ - tmp = (cpu_clk / 1000000) * 1000; - while (tmp--); - - /* Stage 3. Mode Register Set */ - REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; - REG8(EMC_SDMR0|sdmode) = 0; - - /* Set back to basic DMCR value */ - REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; - - /* everything is ok now */ -} diff -r 9469cf34aec2 -r 5d33753dfd71 board-nanonote.h --- a/board-nanonote.h Sun Jun 07 20:17:24 2015 +0200 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,11 +0,0 @@ -#ifndef __BOARD_NANONOTE_H__ -#define __BOARD_NANONOTE_H__ - -/* Initialisation functions. */ - -void load_args(void); -void gpio_init(void); -void pll_init(void); -void sdram_init(void); - -#endif /* __BOARD_NANONOTE_H__ */ diff -r 9469cf34aec2 -r 5d33753dfd71 board-nanonote2.c --- a/board-nanonote2.c Sun Jun 07 20:17:24 2015 +0200 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,334 +0,0 @@ -/* - * Ben NanoNote board late initialisation, based on uboot-xburst and xburst-tools. - * - * Copyright (C) 2015 Paul Boddie - * Copyright (C) Xiangfu Liu - * Copyright (C) 2006 Ingenic Semiconductor, - * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License as published by the Free Software - * Foundation; either version 3 of the License, or (at your option) any later - * version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#include "jz4740.h" -#include "configs.h" -#include "nanonote.h" - -/* Later initialisation functions. */ - -void gpio_init2(void) -{ - /* - * Initialize LCD pins - */ - __gpio_as_slcd_8bit(); - - /* - * Initialize MSC pins - */ - __gpio_as_msc(); - - /* - * Initialize Other pins - */ - unsigned int i; - for (i = 0; i < 7; i++){ - __gpio_as_input(GPIO_KEYIN_BASE + i); - __gpio_enable_pull(GPIO_KEYIN_BASE + i); - } - - for (i = 0; i < 8; i++) { - __gpio_as_output(GPIO_KEYOUT_BASE + i); - __gpio_clear_pin(GPIO_KEYOUT_BASE + i); - } - - /* enable the TP4, TP5 as UART0 */ - __gpio_jtag_to_uart0(); - - __gpio_as_input(GPIO_KEYIN_8); - __gpio_enable_pull(GPIO_KEYIN_8); - - __gpio_as_output(GPIO_AUDIO_POP); - __gpio_set_pin(GPIO_AUDIO_POP); - - __gpio_as_output(GPIO_LCD_CS); - __gpio_clear_pin(GPIO_LCD_CS); - - __gpio_as_output(GPIO_AMP_EN); - __gpio_clear_pin(GPIO_AMP_EN); - - __gpio_as_output(GPIO_SDPW_EN); - __gpio_disable_pull(GPIO_SDPW_EN); - __gpio_clear_pin(GPIO_SDPW_EN); - - __gpio_as_input(GPIO_SD_DETECT); - __gpio_disable_pull(GPIO_SD_DETECT); - - __gpio_as_input(GPIO_USB_DETECT); - __gpio_enable_pull(GPIO_USB_DETECT); -} - -void cpm_init(void) -{ - __cpm_stop_ipu(); - __cpm_stop_cim(); - __cpm_stop_i2c(); - __cpm_stop_ssi(); - __cpm_stop_uart1(); - __cpm_stop_sadc(); - __cpm_stop_uhc(); - __cpm_stop_udc(); - __cpm_stop_aic1(); -/* __cpm_stop_aic2();*/ -} - -void rtc_init(void) -{ - while ( !__rtc_write_ready()); - __rtc_enable_alarm(); /* enable alarm */ - - while ( !__rtc_write_ready()); - REG_RTC_RGR = 0x00007fff; /* type value */ - - while ( !__rtc_write_ready()); - REG_RTC_HWFCR = 0x0000ffe0; /* Power on delay 2s */ - - while ( !__rtc_write_ready()); - REG_RTC_HRCR = 0x00000fe0; /* reset delay 125ms */ -} - -unsigned long get_memory_size(void) -{ - unsigned int dmcr; - unsigned int rows, cols, dw, banks; - unsigned long size; - - dmcr = REG_EMC_DMCR; - rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT); - cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT); - dw = (dmcr & EMC_DMCR_BW) ? 2 : 4; - banks = (dmcr & EMC_DMCR_BA) ? 4 : 2; - - size = (1 << (rows + cols)) * dw * banks; - - return size; -} - -/* Timer routines. */ - -#define TIMER_CHAN 0 -#define TIMER_FDATA 0xffff /* Timer full data value */ -#define TIMER_HZ CONFIG_SYS_HZ - -#define READ_TIMER REG_TCU_TCNT(TIMER_CHAN) /* macro to read the 16 bit timer */ - -static unsigned long timestamp; -static unsigned long lastdec; - -void reset_timer_masked(void); -unsigned long get_timer_masked(void); -void udelay_masked(unsigned long usec); - -/* - * timer without interrupts - */ - -int timer_init(void) -{ - REG_TCU_TCSR(TIMER_CHAN) = TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN; - REG_TCU_TCNT(TIMER_CHAN) = 0; - REG_TCU_TDHR(TIMER_CHAN) = 0; - REG_TCU_TDFR(TIMER_CHAN) = TIMER_FDATA; - - REG_TCU_TMSR = (1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)); /* mask irqs */ - REG_TCU_TSCR = (1 << TIMER_CHAN); /* enable timer clock */ - REG_TCU_TESR = (1 << TIMER_CHAN); /* start counting up */ - - lastdec = 0; - timestamp = 0; - - return 0; -} - -void reset_timer(void) -{ - reset_timer_masked (); -} - -unsigned long get_timer(unsigned long base) -{ - return get_timer_masked () - base; -} - -void set_timer(unsigned long t) -{ - timestamp = t; -} - -void udelay (unsigned long usec) -{ - unsigned long tmo,tmp; - - /* normalize */ - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= TIMER_HZ; - tmo /= 1000; - } - else { - if (usec >= 1) { - tmo = usec * TIMER_HZ; - tmo /= (1000*1000); - } - else - tmo = 1; - } - - /* check for rollover during this delay */ - tmp = get_timer (0); - if ((tmp + tmo) < tmp ) - reset_timer_masked(); /* timer would roll over */ - else - tmo += tmp; - - while (get_timer_masked () < tmo); -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastdec = READ_TIMER; - timestamp = 0; -} - -unsigned long get_timer_masked (void) -{ - unsigned long now = READ_TIMER; - - if (lastdec <= now) { - /* normal mode */ - timestamp += (now - lastdec); - } else { - /* we have an overflow ... */ - timestamp += TIMER_FDATA + now - lastdec; - } - lastdec = now; - - return timestamp; -} - -void udelay_masked (unsigned long usec) -{ - unsigned long tmo; - unsigned long endtime; - signed long diff; - - /* normalize */ - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= TIMER_HZ; - tmo /= 1000; - } else { - if (usec > 1) { - tmo = usec * TIMER_HZ; - tmo /= (1000*1000); - } else { - tmo = 1; - } - } - - endtime = get_timer_masked () + tmo; - - do { - unsigned long now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On MIPS it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On MIPS it returns the number of timer ticks per second. - */ -unsigned long get_tbclk (void) -{ - return TIMER_HZ; -} - -/* CPU-specific routines from U-Boot. - See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c - See: u-boot/arch/mips/include/asm/cacheops.h -*/ - -#define Index_Store_Tag_I 0x08 -#define Index_Writeback_Inv_D 0x15 - -void flush_icache_all(void) -{ - u32 addr, t = 0; - - asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ - asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ - - for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; - addr += CONFIG_SYS_CACHELINE_SIZE) { - asm volatile ( - ".set mips3\n\t" - " cache %0, 0(%1)\n\t" - ".set mips2\n\t" - : - : "I" (Index_Store_Tag_I), "r"(addr)); - } - - /* invalicate btb */ - asm volatile ( - ".set mips32\n\t" - "mfc0 %0, $16, 7\n\t" - "nop\n\t" - "ori %0,2\n\t" - "mtc0 %0, $16, 7\n\t" - ".set mips2\n\t" - : - : "r" (t)); -} - -void flush_dcache_all(void) -{ - u32 addr; - - for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; - addr += CONFIG_SYS_CACHELINE_SIZE) { - asm volatile ( - ".set mips3\n\t" - " cache %0, 0(%1)\n\t" - ".set mips2\n\t" - : - : "I" (Index_Writeback_Inv_D), "r"(addr)); - } - - asm volatile ("sync"); -} - -void flush_cache_all(void) -{ - flush_dcache_all(); - flush_icache_all(); -} diff -r 9469cf34aec2 -r 5d33753dfd71 board-nanonote2.h --- a/board-nanonote2.h Sun Jun 07 20:17:24 2015 +0200 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,17 +0,0 @@ -#ifndef __BOARD_NANONOTE2_H__ -#define __BOARD_NANONOTE2_H__ - -/* Initialisation functions. */ - -void gpio_init2(void); -void cpm_init(void); -void rtc_init(void); -int timer_init(void); - -/* Utility functions. */ - -void udelay(unsigned long usec); -void flush_cache_all(void); -unsigned long get_memory_size(void); - -#endif /* __BOARD_NANONOTE2_H__ */ diff -r 9469cf34aec2 -r 5d33753dfd71 head1.S --- a/head1.S Sun Jun 07 20:17:24 2015 +0200 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,52 +0,0 @@ -/* - * Entry point of the firmware. - * The firmware code is executed in the ICache. - * - * Copyright 2009 (C) Qi Hardware Inc., - * Author: Xiangfu Liu - * - * Copyright (C) 2015 Paul Boddie - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 3 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, - * Boston, MA 02110-1301, USA - */ - - .text - - .extern c_main - - .globl _start - .set noreorder -_start: - b real_start - nop - .word 0x0 /* address: 0x80002008 */ - .word 0x0 - .word 0x0 - .word 0x0 - .word 0x0 - .word 0x0 - .word 0x0 - .word 0x0 - /* reserve 8 words for args sizeof(struct fw_args) - */ -real_start: - /* - * setup stack, jump to C code - */ - la $29, 0x80004000 /* sp */ - j c_main - nop - - .set reorder diff -r 9469cf34aec2 -r 5d33753dfd71 head2.S --- a/head2.S Sun Jun 07 20:17:24 2015 +0200 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,33 +0,0 @@ -/* - * Entry point of the firmware. - * The firmware code are executed in the ICache. - * Do not edit! - * Copyright (C) 2006 Ingenic Semiconductor Inc. - * - */ - - .text - .extern c_main - - .globl _start - .set noreorder -_start: - b real_start - nop - .word 0x0 // its address == start address + 8 - .word 0x0 - .word 0x0 - .word 0x0 - .word 0x0 - .word 0x0 - .word 0x0 - .word 0x0 - -real_start: - /* setup stack, jump to C code */ - add $29, $20, 0x3ffff0 // sp locate at start address offset 0x2ffff0 - add $25, $20, 0x40 // t9 = c_main() - j $25 - nop - - .set reorder diff -r 9469cf34aec2 -r 5d33753dfd71 lcd.c --- a/lcd.c Sun Jun 07 20:17:24 2015 +0200 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,88 +0,0 @@ -/* - * Ben NanoNote LCD initialisation, based on uboot-xburst and xburst-tools. - * - * Copyright (C) 2015 Paul Boddie - * Copyright (C) 2001-2002 Wolfgang Denk, DENX Software Engineering, - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License as published by the Free Software - * Foundation; either version 3 of the License, or (at your option) any later - * version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#include "xburst_types.h" -#include "nanonote_gpm940b0.h" -#include "board-nanonote2.h" - -#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) -#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) - -unsigned long lcd_setmem(unsigned long addr) -{ - unsigned long size; - - size = lcd_get_size(); - - /* Round up to nearest full page, or MMU section if defined */ - size = ALIGN(size, PAGE_SIZE); - addr = ALIGN(addr - PAGE_SIZE + 1, PAGE_SIZE); - - /* Allocate pages for the frame buffer. */ - addr -= size; - - return addr; -} - -#define N_BLK_VERT 2 -#define N_BLK_HOR 3 - -static int test_colors[N_BLK_HOR * N_BLK_VERT] = { - 0x00ff0000, 0x0000ff00, 0x00ffff00, - 0x000000ff, 0x00ff00ff, 0x0000ffff, -}; - -static void test_pattern(void *lcd_base) -{ - unsigned short v_max = panel_info.vl_row; - unsigned short h_max = panel_info.vl_col; - unsigned short v_step = (v_max + N_BLK_VERT - 1) / N_BLK_VERT; - unsigned short h_step = (h_max + N_BLK_HOR - 1) / N_BLK_HOR; - unsigned short v, h; - unsigned char *pix = (unsigned char *)lcd_base; - - /* WARNING: Code silently assumes 8bit/pixel */ - for (v = 0; v < v_max; ++v) { - unsigned char iy = v / v_step; - for (h = 0; h < h_max; ++h) { - unsigned char ix = N_BLK_HOR * iy + h / h_step; - *pix++ = test_colors[ix]; - } - } -} - -void lcd_clear(void *lcd_base) -{ - test_pattern(lcd_base); -} - -/* LCD initialisation. */ - -static void *lcd_base; - -void lcd_init(void) -{ - /* Start from the top of memory and obtain a framebuffer region. */ - - lcd_base = (void *) lcd_setmem(get_memory_size()); - lcd_ctrl_init(lcd_base); - lcd_clear(lcd_base); - lcd_enable(); -} diff -r 9469cf34aec2 -r 5d33753dfd71 lcd.h --- a/lcd.h Sun Jun 07 20:17:24 2015 +0200 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,8 +0,0 @@ -#ifndef __LCD_H__ -#define __LCD_H__ - -/* Initialisation functions. */ - -void lcd_init(void); - -#endif /* __LCD_H__ */ diff -r 9469cf34aec2 -r 5d33753dfd71 nanonote_gpm940b0.c --- a/nanonote_gpm940b0.c Sun Jun 07 20:17:24 2015 +0200 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,403 +0,0 @@ -/* - * JzRISC lcd controller - * - * Copyright (C) Xiangfu Liu - * Copyright (C) 2015 Paul Boddie - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* virt_to_phys() from u-boot/arch/mips/include/asm/addrspace.h - via u-boot/arch/mips/include/asm/io.h */ -#define virt_to_phys(n) (((int) n) & 0x1fffffff) - -#include "jz4740.h" -#include "nanonote_gpm940b0.h" -#include "board-nanonote2.h" - -#define align2(n) (n)=((((n)+1)>>1)<<1) -#define align4(n) (n)=((((n)+3)>>2)<<2) -#define align8(n) (n)=((((n)+7)>>3)<<3) - -struct jzfb_info { - unsigned int cfg; /* panel mode and pin usage etc. */ - unsigned int w; - unsigned int h; - unsigned int bpp; /* bit per pixel */ - unsigned int fclk; /* frame clk */ - unsigned int hsw; /* hsync width, in pclk */ - unsigned int vsw; /* vsync width, in line count */ - unsigned int elw; /* end of line, in pclk */ - unsigned int blw; /* begin of line, in pclk */ - unsigned int efw; /* end of frame, in line count */ - unsigned int bfw; /* begin of frame, in line count */ -}; - -static struct jzfb_info jzfb = { - MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N, - 320, 240, 32, 70, 1, 1, 273, 140, 1, 20 -}; - -vidinfo_t panel_info = { - 320, 240, LCD_BPP, -}; - -unsigned long lcd_get_size(void) -{ - int line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; - return line_length * panel_info.vl_row; -} - -static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid); -static void jz_lcd_desc_init(vidinfo_t *vid); -static int jz_lcd_hw_init(vidinfo_t *vid); - -void lcd_ctrl_init (void *lcdbase) -{ - jz_lcd_init_mem(lcdbase, &panel_info); - jz_lcd_desc_init(&panel_info); - jz_lcd_hw_init(&panel_info); -} - -/* - * Before enabled lcd controller, lcd registers should be configured correctly. - */ -void lcd_enable (void) -{ - REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */ - REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/ -} - -void lcd_disable (void) -{ - REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */ - /* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */ -} - -static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid) -{ - unsigned long palette_mem_size; - struct jz_fb_info *fbi = &vid->jz_fb; - int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8; - - fbi->screen = (unsigned long)lcdbase; - fbi->palette_size = 256; - palette_mem_size = fbi->palette_size * sizeof(u16); - - /* debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (unsigned long) palette_mem_size); */ - /* locate palette and descs at end of page following fb */ - fbi->palette = (unsigned long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size; - - return 0; -} - -static void jz_lcd_desc_init(vidinfo_t *vid) -{ - struct jz_fb_info * fbi; - fbi = &vid->jz_fb; - fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16); - fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16); - fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16); - - #define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8) - - /* populate descriptors */ - fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow); - fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL)); - fbi->dmadesc_fblow->fidr = 0; - fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ; - - fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */ - - fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen); - fbi->dmadesc_fbhigh->fidr = 0; - fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */ - - fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette); - fbi->dmadesc_palette->fidr = 0; - fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28); - - if(NBITS(vid->vl_bpix) < 12) - { - /* assume any mode with <12 bpp is palette driven */ - fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh); - fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette); - /* flips back and forth between pal and fbhigh */ - fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette); - } else { - /* palette shouldn't be loaded in true-color mode */ - fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh); - fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */ - } - - flush_cache_all(); -} - -static int jz_lcd_hw_init(vidinfo_t *vid) -{ - struct jz_fb_info *fbi = &vid->jz_fb; - unsigned int val = 0; - unsigned int pclk; - unsigned int stnH; - int pll_div; - - /* Setting Control register */ - switch (jzfb.bpp) { - case 1: - val |= LCD_CTRL_BPP_1; - break; - case 2: - val |= LCD_CTRL_BPP_2; - break; - case 4: - val |= LCD_CTRL_BPP_4; - break; - case 8: - val |= LCD_CTRL_BPP_8; - break; - case 15: - val |= LCD_CTRL_RGB555; - case 16: - val |= LCD_CTRL_BPP_16; - break; - case 17 ... 32: - val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */ - break; - - default: - /* printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp); */ - val |= LCD_CTRL_BPP_16; - break; - } - - switch (jzfb.cfg & MODE_MASK) { - case MODE_STN_MONO_DUAL: - case MODE_STN_COLOR_DUAL: - case MODE_STN_MONO_SINGLE: - case MODE_STN_COLOR_SINGLE: - switch (jzfb.bpp) { - case 1: - /* val |= LCD_CTRL_PEDN; */ - case 2: - val |= LCD_CTRL_FRC_2; - break; - case 4: - val |= LCD_CTRL_FRC_4; - break; - case 8: - default: - val |= LCD_CTRL_FRC_16; - break; - } - break; - } - - val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */ - val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */ - - switch (jzfb.cfg & MODE_MASK) { - case MODE_STN_MONO_DUAL: - case MODE_STN_COLOR_DUAL: - case MODE_STN_MONO_SINGLE: - case MODE_STN_COLOR_SINGLE: - switch (jzfb.cfg & STN_DAT_PINMASK) { - case STN_DAT_PIN1: - /* Do not adjust the hori-param value. */ - break; - case STN_DAT_PIN2: - align2(jzfb.hsw); - align2(jzfb.elw); - align2(jzfb.blw); - break; - case STN_DAT_PIN4: - align4(jzfb.hsw); - align4(jzfb.elw); - align4(jzfb.blw); - break; - case STN_DAT_PIN8: - align8(jzfb.hsw); - align8(jzfb.elw); - align8(jzfb.blw); - break; - } - break; - } - - REG_LCD_CTRL = val; - - switch (jzfb.cfg & MODE_MASK) { - case MODE_STN_MONO_DUAL: - case MODE_STN_COLOR_DUAL: - case MODE_STN_MONO_SINGLE: - case MODE_STN_COLOR_SINGLE: - if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) - stnH = jzfb.h >> 1; - else - stnH = jzfb.h; - - REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; - REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw); - - /* Screen setting */ - REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw); - REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w); - REG_LCD_DAV = (0 << 16) | (stnH); - - /* AC BIAs signal */ - REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw); - - break; - - case MODE_TFT_GEN: - case MODE_TFT_SHARP: - case MODE_TFT_CASIO: - case MODE_TFT_SAMSUNG: - case MODE_8BIT_SERIAL_TFT: - case MODE_TFT_18BIT: - REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; - REG_LCD_HSYNC = (0 << 16) | jzfb.hsw; - REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h); - REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w ); - REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \ - | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw); - break; - } - - switch (jzfb.cfg & MODE_MASK) { - case MODE_TFT_SAMSUNG: - { - unsigned int total, tp_s, tp_e, ckv_s, ckv_e; - unsigned int rev_s, rev_e, inv_s, inv_e; - - pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * - (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ - - total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; - tp_s = jzfb.blw + jzfb.w + 1; - tp_e = tp_s + 1; - /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */ - ckv_s = tp_s - pclk/(1000000000/4100); - ckv_e = tp_s + total; - rev_s = tp_s - 11; /* -11.5 clk */ - rev_e = rev_s + total; - inv_s = tp_s; - inv_e = inv_s + total; - REG_LCD_CLS = (tp_s << 16) | tp_e; - REG_LCD_PS = (ckv_s << 16) | ckv_e; - REG_LCD_SPL = (rev_s << 16) | rev_e; - REG_LCD_REV = (inv_s << 16) | inv_e; - jzfb.cfg |= STFT_REVHI | STFT_SPLHI; - break; - } - case MODE_TFT_SHARP: - { - unsigned int total, cls_s, cls_e, ps_s, ps_e; - unsigned int spl_s, spl_e, rev_s, rev_e; - total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; - spl_s = 1; - spl_e = spl_s + 1; - cls_s = 0; - cls_e = total - 60; /* > 4us (pclk = 80ns) */ - ps_s = cls_s; - ps_e = cls_e; - rev_s = total - 40; /* > 3us (pclk = 80ns) */ - rev_e = rev_s + total; - jzfb.cfg |= STFT_PSHI; - REG_LCD_SPL = (spl_s << 16) | spl_e; - REG_LCD_CLS = (cls_s << 16) | cls_e; - REG_LCD_PS = (ps_s << 16) | ps_e; - REG_LCD_REV = (rev_s << 16) | rev_e; - break; - } - case MODE_TFT_CASIO: - break; - } - - /* Configure the LCD panel */ - REG_LCD_CFG = jzfb.cfg; - - /* Timing setting */ - __cpm_stop_lcd(); - - val = jzfb.fclk; /* frame clk */ - if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) { - pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * - (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ - } else { - /* serial mode: Hsync period = 3*Width_Pixel */ - pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) * - (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ - } - - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) - pclk = (pclk * 3); - - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) - pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4); - - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) - pclk >>= 1; - - pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */ - pll_div = pll_div ? 1 : 2 ; - val = ( __cpm_get_pllout()/pll_div ) / pclk; - val--; - if ( val > 0x1ff ) { - /* printf("CPM_LPCDR too large, set it to 0x1ff\n"); */ - val = 0x1ff; - } - __cpm_set_pixdiv(val); - - val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */ - if ( val > 150000000 ) { - /* printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val); */ - /* printf("Change LCDClock to 150MHz\n"); */ - val = 150000000; - } - val = ( __cpm_get_pllout()/pll_div ) / val; - val--; - if ( val > 0x1f ) { - /* printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n"); */ - val = 0x1f; - } - __cpm_set_ldiv( val ); - REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */ - - __cpm_start_lcd(); - udelay(1000); - - REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/ - - if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || - ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) - REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/ - - return 0; -} - -void lcd_setcolreg (unsigned short regno, unsigned short red, unsigned short green, unsigned short blue) -{ -} - -void lcd_initcolregs (void) -{ -} diff -r 9469cf34aec2 -r 5d33753dfd71 nanonote_gpm940b0.h --- a/nanonote_gpm940b0.h Sun Jun 07 20:17:24 2015 +0200 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,143 +0,0 @@ -/* - * JzRISC lcd controller - * - * Xiangfu Liu - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __QI_LB60_GPM940B0_H__ -#define __QI_LB60_GPM940B0_H__ - -#include "nanonote.h" -#include "jz4740_lcd.h" - -unsigned long lcd_get_size(void); -void lcd_ctrl_init(void *lcdbase); -void lcd_enable(void); -void lcd_disable(void); - -struct lcd_desc{ - unsigned int next_desc; /* LCDDAx */ - unsigned int databuf; /* LCDSAx */ - unsigned int frame_id; /* LCDFIDx */ - unsigned int cmd; /* LCDCMDx */ -}; - -#define MODE_MASK 0x0f -#define MODE_TFT_GEN 0x00 -#define MODE_TFT_SHARP 0x01 -#define MODE_TFT_CASIO 0x02 -#define MODE_TFT_SAMSUNG 0x03 -#define MODE_CCIR656_NONINT 0x04 -#define MODE_CCIR656_INT 0x05 -#define MODE_STN_COLOR_SINGLE 0x08 -#define MODE_STN_MONO_SINGLE 0x09 -#define MODE_STN_COLOR_DUAL 0x0a -#define MODE_STN_MONO_DUAL 0x0b -#define MODE_8BIT_SERIAL_TFT 0x0c - -#define MODE_TFT_18BIT (1<<7) - -#define STN_DAT_PIN1 (0x00 << 4) -#define STN_DAT_PIN2 (0x01 << 4) -#define STN_DAT_PIN4 (0x02 << 4) -#define STN_DAT_PIN8 (0x03 << 4) -#define STN_DAT_PINMASK STN_DAT_PIN8 - -#define STFT_PSHI (1 << 15) -#define STFT_CLSHI (1 << 14) -#define STFT_SPLHI (1 << 13) -#define STFT_REVHI (1 << 12) - -#define SYNC_MASTER (0 << 16) -#define SYNC_SLAVE (1 << 16) - -#define DE_P (0 << 9) -#define DE_N (1 << 9) - -#define PCLK_P (0 << 10) -#define PCLK_N (1 << 10) - -#define HSYNC_P (0 << 11) -#define HSYNC_N (1 << 11) - -#define VSYNC_P (0 << 8) -#define VSYNC_N (1 << 8) - -#define DATA_NORMAL (0 << 17) -#define DATA_INVERSE (1 << 17) - - -/* Jz LCDFB supported I/O controls. */ -#define FBIOSETBACKLIGHT 0x4688 -#define FBIODISPON 0x4689 -#define FBIODISPOFF 0x468a -#define FBIORESET 0x468b -#define FBIOPRINT_REG 0x468c - -/* - * LCD panel specific definition - */ -#define MODE (0xc9) /* 8bit serial RGB */ - -#define __spi_write_reg1(reg, val) \ -do { \ - unsigned char no; \ - unsigned short value; \ - unsigned char a=reg; \ - unsigned char b=val; \ - __gpio_set_pin(SPEN); \ - __gpio_set_pin(SPCK); \ - __gpio_clear_pin(SPDA); \ - __gpio_clear_pin(SPEN); \ - value=((a<<8)|(b&0xFF)); \ - for(no=0;no<16;no++) \ - { \ - __gpio_clear_pin(SPCK); \ - if((value&0x8000)==0x8000) \ - __gpio_set_pin(SPDA); \ - else \ - __gpio_clear_pin(SPDA); \ - __gpio_set_pin(SPCK); \ - value=(value<<1); \ - } \ - __gpio_set_pin(SPEN); \ -} while (0) - -#define __lcd_display_pin_init() \ -do { \ - __cpm_start_tcu(); \ - __gpio_as_output(SPEN); /* use SPDA */ \ - __gpio_as_output(SPCK); /* use SPCK */ \ - __gpio_as_output(SPDA); /* use SPDA */ \ -} while (0) - -#define __lcd_display_on() \ -do { \ - __spi_write_reg1(0x05, 0x1e); \ - __spi_write_reg1(0x05, 0x5e); \ - __spi_write_reg1(0x07, 0x8d); \ - __spi_write_reg1(0x13, 0x01); \ - __spi_write_reg1(0x05, 0x5f); \ -} while (0) - -#define __lcd_display_off() \ -do { \ - __spi_write_reg1(0x05, 0x5e); \ -} while (0) - -#endif /* __QI_LB60_GPM940B0_H__ */ diff -r 9469cf34aec2 -r 5d33753dfd71 stage1.c --- a/stage1.c Sun Jun 07 20:17:24 2015 +0200 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,29 +0,0 @@ -/* - * Ben NanoNote stage 1 payload test. - * - * Copyright (C) 2015 Paul Boddie - * Copyright (C) Wolfgang Spraul - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License as published by the Free Software - * Foundation; either version 3 of the License, or (at your option) any later - * version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#include "board-nanonote.h" - -void c_main(void) -{ - load_args(); - gpio_init(); - pll_init(); - sdram_init(); -} diff -r 9469cf34aec2 -r 5d33753dfd71 stage1.ld --- a/stage1.ld Sun Jun 07 20:17:24 2015 +0200 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,31 +0,0 @@ -OUTPUT_ARCH(mips) -ENTRY(_start) -MEMORY -{ - ram : ORIGIN = 0x80002000 , LENGTH = 0x100000 -} - -SECTIONS -{ - . = ALIGN(4); - .text : { *(.text*) } > ram - - . = ALIGN(4); - .rodata : { *(.rodata*) } > ram - - . = ALIGN(4); - .sdata : { *(.sdata*) } > ram - - . = ALIGN(4); - .data : { *(.data*) *(.scommon*) *(.reginfo*) } > ram - - _gp = ABSOLUTE(.); /* Base of small data */ - - .got : { *(.got*) } > ram - - . = ALIGN(4); - .sbss : { *(.sbss*) } > ram - .bss : { *(.bss*) } > ram - . = ALIGN (4); -} - diff -r 9469cf34aec2 -r 5d33753dfd71 stage1/Makefile --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage1/Makefile Sun Jun 07 23:06:08 2015 +0200 @@ -0,0 +1,73 @@ +# Makefile - Build the NanoNote payload +# +# Copyright (C) 2015 Paul Boddie +# Copyright (C) Xiangfu Liu +# +# This program is free software; you can redistribute it and/or modify it under +# the terms of the GNU General Public License as published by the Free Software +# Foundation; either version 3 of the License, or (at your option) any later +# version. +# +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +# FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +# details. +# +# You should have received a copy of the GNU General Public License along with +# this program. If not, see . + +ARCH = mipsel-linux-gnu +CC = $(ARCH)-gcc +LD = $(ARCH)-ld +NM = $(ARCH)-nm +OBJCOPY=$(ARCH)-objcopy +OBJDUMP=$(ARCH)-objdump + +# NOTE: -O2 is actually needed to prevent memcpy references, whereas probably +# NOTE: one of the -f{freestanding, no-hosted, no-builtin} options should work. +# NOTE: See: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=56888 + +ASM_INC = /usr/src/linux-headers-4.0.0-1-common/arch/mips/include +CFLAGS = -O2 -Wall \ + -fno-unit-at-a-time -fno-zero-initialized-in-bss \ + -ffreestanding -fno-hosted -fno-builtin \ + -march=mips32 \ + -I../include -I$(ASM_INC) -I$(ASM_INC)/asm/mach-generic +LDFLAGS = -nostdlib -EL + +PAYLOAD = stage1.bin +TARGET = $(PAYLOAD:.bin=.elf) +DUMP = $(PAYLOAD:.bin=.dump) +MAP = $(PAYLOAD:.bin=.map) + +# Ordering of objects is important and cannot be left to replacement rules. + +SRC = head1.S stage1.c board-nanonote.c +OBJ = head1.o stage1.o board-nanonote.o + +.PHONY: all clean distclean + +all: $(PAYLOAD) + +clean: + rm -f $(OBJ) $(TARGET) $(PAYLOAD) $(DUMP) *.map + +distclean: clean + echo "Nothing else to clean." + +$(PAYLOAD): $(TARGET) + $(OBJCOPY) -O binary $(@:.bin=.elf) $@+ + $(OBJDUMP) -D $(@:.bin=.elf) > $(@:.bin=.dump) + $(OBJDUMP) -h $(@:.bin=.elf) > $(@:.bin=.map) + $(NM) -n $(@:.bin=.elf) > System.map + chmod -x $@+ + mv -f $@+ $@ + +stage1.elf: $(OBJ) + $(LD) $(LDFLAGS) -T $(@:.elf=.ld) $(OBJ) -o $@ + +.c.o: + $(CC) -c $(CFLAGS) $< -o $@ + +.S.o: + $(CC) -c $(CFLAGS) $< -o $@ diff -r 9469cf34aec2 -r 5d33753dfd71 stage1/board-nanonote.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage1/board-nanonote.c Sun Jun 07 23:06:08 2015 +0200 @@ -0,0 +1,210 @@ +/* + * Ben NanoNote board initialisation, based on uboot-xburst and xburst-tools. + * + * Copyright (C) 2015 Paul Boddie + * Copyright (C) Xiangfu Liu + * Copyright (C) 2006 Ingenic Semiconductor, + * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License as published by the Free Software + * Foundation; either version 3 of the License, or (at your option) any later + * version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "jz4740.h" +#include "configs.h" +#include "nanonote.h" +#include "usb_boot_defines.h" + +/* These arguments are initialised by usbboot and are defined in... + /etc/xburst-tools/usbboot.cfg. */ + +struct fw_args *fw_args; +volatile u32 CPU_ID; +volatile u8 SDRAM_BW16; +volatile u8 SDRAM_BANK4; +volatile u8 SDRAM_ROW; +volatile u8 SDRAM_COL; +volatile u8 CONFIG_MOBILE_SDRAM; +volatile u8 IS_SHARE; + +void load_args(void) +{ + /* Get the fw args from memory. See head1.S for the memory layout. */ + + fw_args = (struct fw_args *)0x80002008; + CPU_ID = fw_args->cpu_id ; + SDRAM_BW16 = fw_args->bus_width; + SDRAM_BANK4 = fw_args->bank_num; + SDRAM_ROW = fw_args->row_addr; + SDRAM_COL = fw_args->col_addr; + CONFIG_MOBILE_SDRAM = fw_args->is_mobile; + IS_SHARE = fw_args->is_busshare; +} + +/* Initialisation functions. */ + +void gpio_init(void) +{ + /* + * Initialize NAND Flash Pins + */ + __gpio_as_nand(); + + /* + * Initialize SDRAM pins + */ + __gpio_as_sdram_16bit_4720(); +} + +void pll_init(void) +{ + register unsigned int cfcr, plcr1; + int nf, pllout2; + + /* See CPCCR (Clock Control Register). + * 0 == same frequency; 2 == f/3 + */ + + cfcr = CPM_CPCCR_CLKOEN | + CPM_CPCCR_PCS | + (0 << CPM_CPCCR_CDIV_BIT) | + (2 << CPM_CPCCR_HDIV_BIT) | + (2 << CPM_CPCCR_PDIV_BIT) | + (2 << CPM_CPCCR_MDIV_BIT) | + (2 << CPM_CPCCR_LDIV_BIT); + + /* Determine the divider clock output based on the PCS bit. */ + + pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2); + + /* Init USB Host clock. + * Divisor == UHCCDR + 1 + * Desired frequency == 48MHz + */ + + REG_CPM_UHCCDR = pllout2 / 48000000 - 1; + + nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL; + plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ + (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ + (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ + CPM_CPPCR_PLLEN; /* enable PLL */ + + /* Update PLL and wait. */ + + REG_CPM_CPCCR = cfcr; + REG_CPM_CPPCR = plcr1; + while (!__cpm_pll_is_on()); +} + +void sdram_init(void) +{ + register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; + unsigned int pllout = __cpm_get_pllout(); + + unsigned int cas_latency_sdmr[2] = { + EMC_SDMR_CAS_2, + EMC_SDMR_CAS_3, + }; + + unsigned int cas_latency_dmcr[2] = { + 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ + 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ + }; + + /* Divisors for CPCCR values. */ + + int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; + + cpu_clk = pllout / div[__cpm_get_cdiv()]; + mem_clk = pllout / div[__cpm_get_mdiv()]; + + REG_EMC_BCR = 0; /* Disable bus release */ + REG_EMC_RTCSR = 0; /* Disable clock for counting */ + + /* Fault DMCR value for mode register setting*/ +#define SDRAM_ROW0 11 +#define SDRAM_COL0 8 +#define SDRAM_BANK40 0 + + dmcr0 = ((SDRAM_ROW0-11)< 11) tmp = 11; + dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); + tmp = SDRAM_RCD/ns; + if (tmp > 3) tmp = 3; + dmcr |= (tmp << EMC_DMCR_RCD_BIT); + tmp = SDRAM_TPC/ns; + if (tmp > 7) tmp = 7; + dmcr |= (tmp << EMC_DMCR_TPC_BIT); + tmp = SDRAM_TRWL/ns; + if (tmp > 3) tmp = 3; + dmcr |= (tmp << EMC_DMCR_TRWL_BIT); + tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; + if (tmp > 14) tmp = 14; + dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); + + /* SDRAM mode value */ + sdmode = EMC_SDMR_BT_SEQ | + EMC_SDMR_OM_NORMAL | + EMC_SDMR_BL_4 | + cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; + + /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ + REG_EMC_DMCR = dmcr; + REG8(EMC_SDMR0|sdmode) = 0; + + /* Wait for precharge, > 200us */ + tmp = (cpu_clk / 1000000) * 1000; + while (tmp--); + + /* Stage 2. Enable auto-refresh */ + REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; + + tmp = SDRAM_TREF/ns; + tmp = tmp/64 + 1; + if (tmp > 0xff) tmp = 0xff; + REG_EMC_RTCOR = tmp; + REG_EMC_RTCNT = 0; + REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ + + /* Wait for number of auto-refresh cycles */ + tmp = (cpu_clk / 1000000) * 1000; + while (tmp--); + + /* Stage 3. Mode Register Set */ + REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; + REG8(EMC_SDMR0|sdmode) = 0; + + /* Set back to basic DMCR value */ + REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; + + /* everything is ok now */ +} diff -r 9469cf34aec2 -r 5d33753dfd71 stage1/board-nanonote.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage1/board-nanonote.h Sun Jun 07 23:06:08 2015 +0200 @@ -0,0 +1,11 @@ +#ifndef __BOARD_NANONOTE_H__ +#define __BOARD_NANONOTE_H__ + +/* Initialisation functions. */ + +void load_args(void); +void gpio_init(void); +void pll_init(void); +void sdram_init(void); + +#endif /* __BOARD_NANONOTE_H__ */ diff -r 9469cf34aec2 -r 5d33753dfd71 stage1/head1.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage1/head1.S Sun Jun 07 23:06:08 2015 +0200 @@ -0,0 +1,52 @@ +/* + * Entry point of the firmware. + * The firmware code is executed in the ICache. + * + * Copyright 2009 (C) Qi Hardware Inc., + * Author: Xiangfu Liu + * + * Copyright (C) 2015 Paul Boddie + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 3 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, + * Boston, MA 02110-1301, USA + */ + + .text + + .extern c_main + + .globl _start + .set noreorder +_start: + b real_start + nop + .word 0x0 /* address: 0x80002008 */ + .word 0x0 + .word 0x0 + .word 0x0 + .word 0x0 + .word 0x0 + .word 0x0 + .word 0x0 + /* reserve 8 words for args sizeof(struct fw_args) + */ +real_start: + /* + * setup stack, jump to C code + */ + la $29, 0x80004000 /* sp */ + j c_main + nop + + .set reorder diff -r 9469cf34aec2 -r 5d33753dfd71 stage1/stage1.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage1/stage1.c Sun Jun 07 23:06:08 2015 +0200 @@ -0,0 +1,29 @@ +/* + * Ben NanoNote stage 1 payload test. + * + * Copyright (C) 2015 Paul Boddie + * Copyright (C) Wolfgang Spraul + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License as published by the Free Software + * Foundation; either version 3 of the License, or (at your option) any later + * version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "board-nanonote.h" + +void c_main(void) +{ + load_args(); + gpio_init(); + pll_init(); + sdram_init(); +} diff -r 9469cf34aec2 -r 5d33753dfd71 stage1/stage1.ld --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage1/stage1.ld Sun Jun 07 23:06:08 2015 +0200 @@ -0,0 +1,31 @@ +OUTPUT_ARCH(mips) +ENTRY(_start) +MEMORY +{ + ram : ORIGIN = 0x80002000 , LENGTH = 0x100000 +} + +SECTIONS +{ + . = ALIGN(4); + .text : { *(.text*) } > ram + + . = ALIGN(4); + .rodata : { *(.rodata*) } > ram + + . = ALIGN(4); + .sdata : { *(.sdata*) } > ram + + . = ALIGN(4); + .data : { *(.data*) *(.scommon*) *(.reginfo*) } > ram + + _gp = ABSOLUTE(.); /* Base of small data */ + + .got : { *(.got*) } > ram + + . = ALIGN(4); + .sbss : { *(.sbss*) } > ram + .bss : { *(.bss*) } > ram + . = ALIGN (4); +} + diff -r 9469cf34aec2 -r 5d33753dfd71 stage2.c --- a/stage2.c Sun Jun 07 20:17:24 2015 +0200 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,31 +0,0 @@ -/* - * Ben NanoNote stage 2 payload test. - * - * Copyright (C) 2015 Paul Boddie - * Copyright (C) Wolfgang Spraul - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License as published by the Free Software - * Foundation; either version 3 of the License, or (at your option) any later - * version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#include "board-nanonote2.h" -#include "lcd.h" - -void c_main(void) -{ - gpio_init2(); - cpm_init(); - rtc_init(); - timer_init(); - lcd_init(); -} diff -r 9469cf34aec2 -r 5d33753dfd71 stage2.ld --- a/stage2.ld Sun Jun 07 20:17:24 2015 +0200 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,32 +0,0 @@ -OUTPUT_ARCH(mips) -ENTRY(_start) -MEMORY -{ - ram : ORIGIN = 0x80000000 , LENGTH = 3M -} - -SECTIONS -{ - . = ALIGN(4); - .text : { *(.text*) } > ram - - . = ALIGN(4); - .rodata : { *(.rodata*) } > ram - - . = ALIGN(4); - .sdata : { *(.sdata*) } > ram - - . = ALIGN(4); - .data : { *(.data*) *(.scommon*) *(.reginfo*) } > ram - - _gp = ALIGN(16); - - .got : { *(.got*) } > ram - _got_end = ABSOLUTE(.); - - . = ALIGN(4); - .sbss : { *(.sbss*) } > ram - .bss : { *(.bss*) } > ram - . = ALIGN (4); -} - diff -r 9469cf34aec2 -r 5d33753dfd71 stage2/Makefile --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage2/Makefile Sun Jun 07 23:06:08 2015 +0200 @@ -0,0 +1,73 @@ +# Makefile - Build the NanoNote payload +# +# Copyright (C) 2015 Paul Boddie +# Copyright (C) Xiangfu Liu +# +# This program is free software; you can redistribute it and/or modify it under +# the terms of the GNU General Public License as published by the Free Software +# Foundation; either version 3 of the License, or (at your option) any later +# version. +# +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +# FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +# details. +# +# You should have received a copy of the GNU General Public License along with +# this program. If not, see . + +ARCH = mipsel-linux-gnu +CC = $(ARCH)-gcc +LD = $(ARCH)-ld +NM = $(ARCH)-nm +OBJCOPY=$(ARCH)-objcopy +OBJDUMP=$(ARCH)-objdump + +# NOTE: -O2 is actually needed to prevent memcpy references, whereas probably +# NOTE: one of the -f{freestanding, no-hosted, no-builtin} options should work. +# NOTE: See: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=56888 + +ASM_INC = /usr/src/linux-headers-4.0.0-1-common/arch/mips/include +CFLAGS = -O2 -Wall \ + -fno-unit-at-a-time -fno-zero-initialized-in-bss \ + -ffreestanding -fno-hosted -fno-builtin \ + -march=mips32 -fPIC \ + -I../include -I$(ASM_INC) -I$(ASM_INC)/asm/mach-generic +LDFLAGS = -nostdlib -EL -pie + +PAYLOAD = stage2.bin +TARGET = $(PAYLOAD:.bin=.elf) +DUMP = $(PAYLOAD:.bin=.dump) +MAP = $(PAYLOAD:.bin=.map) + +# Ordering of objects is important and cannot be left to replacement rules. + +SRC = head2.S stage2.c board-nanonote.c nanonote_gpm940b0.c lcd.c +OBJ = head2.o stage2.o board-nanonote.o nanonote_gpm940b0.o lcd.o + +.PHONY: all clean distclean + +all: $(PAYLOAD) + +clean: + rm -f $(OBJ) $(TARGET) $(PAYLOAD) $(DUMP) *.map + +distclean: clean + echo "Nothing else to clean." + +$(PAYLOAD): $(TARGET) + $(OBJCOPY) -O binary $(@:.bin=.elf) $@+ + $(OBJDUMP) -D $(@:.bin=.elf) > $(@:.bin=.dump) + $(OBJDUMP) -h $(@:.bin=.elf) > $(@:.bin=.map) + $(NM) -n $(@:.bin=.elf) > System.map + chmod -x $@+ + mv -f $@+ $@ + +stage2.elf: $(OBJ) + $(LD) $(LDFLAGS) -pie -T $(@:.elf=.ld) $(OBJ) -o $@ + +.c.o: + $(CC) -c $(CFLAGS) $< -o $@ + +.S.o: + $(CC) -c $(CFLAGS) $< -o $@ diff -r 9469cf34aec2 -r 5d33753dfd71 stage2/board-nanonote.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage2/board-nanonote.c Sun Jun 07 23:06:08 2015 +0200 @@ -0,0 +1,334 @@ +/* + * Ben NanoNote board late initialisation, based on uboot-xburst and xburst-tools. + * + * Copyright (C) 2015 Paul Boddie + * Copyright (C) Xiangfu Liu + * Copyright (C) 2006 Ingenic Semiconductor, + * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License as published by the Free Software + * Foundation; either version 3 of the License, or (at your option) any later + * version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "jz4740.h" +#include "configs.h" +#include "nanonote.h" + +/* Later initialisation functions. */ + +void gpio_init2(void) +{ + /* + * Initialize LCD pins + */ + __gpio_as_slcd_8bit(); + + /* + * Initialize MSC pins + */ + __gpio_as_msc(); + + /* + * Initialize Other pins + */ + unsigned int i; + for (i = 0; i < 7; i++){ + __gpio_as_input(GPIO_KEYIN_BASE + i); + __gpio_enable_pull(GPIO_KEYIN_BASE + i); + } + + for (i = 0; i < 8; i++) { + __gpio_as_output(GPIO_KEYOUT_BASE + i); + __gpio_clear_pin(GPIO_KEYOUT_BASE + i); + } + + /* enable the TP4, TP5 as UART0 */ + __gpio_jtag_to_uart0(); + + __gpio_as_input(GPIO_KEYIN_8); + __gpio_enable_pull(GPIO_KEYIN_8); + + __gpio_as_output(GPIO_AUDIO_POP); + __gpio_set_pin(GPIO_AUDIO_POP); + + __gpio_as_output(GPIO_LCD_CS); + __gpio_clear_pin(GPIO_LCD_CS); + + __gpio_as_output(GPIO_AMP_EN); + __gpio_clear_pin(GPIO_AMP_EN); + + __gpio_as_output(GPIO_SDPW_EN); + __gpio_disable_pull(GPIO_SDPW_EN); + __gpio_clear_pin(GPIO_SDPW_EN); + + __gpio_as_input(GPIO_SD_DETECT); + __gpio_disable_pull(GPIO_SD_DETECT); + + __gpio_as_input(GPIO_USB_DETECT); + __gpio_enable_pull(GPIO_USB_DETECT); +} + +void cpm_init(void) +{ + __cpm_stop_ipu(); + __cpm_stop_cim(); + __cpm_stop_i2c(); + __cpm_stop_ssi(); + __cpm_stop_uart1(); + __cpm_stop_sadc(); + __cpm_stop_uhc(); + __cpm_stop_udc(); + __cpm_stop_aic1(); +/* __cpm_stop_aic2();*/ +} + +void rtc_init(void) +{ + while ( !__rtc_write_ready()); + __rtc_enable_alarm(); /* enable alarm */ + + while ( !__rtc_write_ready()); + REG_RTC_RGR = 0x00007fff; /* type value */ + + while ( !__rtc_write_ready()); + REG_RTC_HWFCR = 0x0000ffe0; /* Power on delay 2s */ + + while ( !__rtc_write_ready()); + REG_RTC_HRCR = 0x00000fe0; /* reset delay 125ms */ +} + +unsigned long get_memory_size(void) +{ + unsigned int dmcr; + unsigned int rows, cols, dw, banks; + unsigned long size; + + dmcr = REG_EMC_DMCR; + rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT); + cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT); + dw = (dmcr & EMC_DMCR_BW) ? 2 : 4; + banks = (dmcr & EMC_DMCR_BA) ? 4 : 2; + + size = (1 << (rows + cols)) * dw * banks; + + return size; +} + +/* Timer routines. */ + +#define TIMER_CHAN 0 +#define TIMER_FDATA 0xffff /* Timer full data value */ +#define TIMER_HZ CONFIG_SYS_HZ + +#define READ_TIMER REG_TCU_TCNT(TIMER_CHAN) /* macro to read the 16 bit timer */ + +static unsigned long timestamp; +static unsigned long lastdec; + +void reset_timer_masked(void); +unsigned long get_timer_masked(void); +void udelay_masked(unsigned long usec); + +/* + * timer without interrupts + */ + +int timer_init(void) +{ + REG_TCU_TCSR(TIMER_CHAN) = TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN; + REG_TCU_TCNT(TIMER_CHAN) = 0; + REG_TCU_TDHR(TIMER_CHAN) = 0; + REG_TCU_TDFR(TIMER_CHAN) = TIMER_FDATA; + + REG_TCU_TMSR = (1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)); /* mask irqs */ + REG_TCU_TSCR = (1 << TIMER_CHAN); /* enable timer clock */ + REG_TCU_TESR = (1 << TIMER_CHAN); /* start counting up */ + + lastdec = 0; + timestamp = 0; + + return 0; +} + +void reset_timer(void) +{ + reset_timer_masked (); +} + +unsigned long get_timer(unsigned long base) +{ + return get_timer_masked () - base; +} + +void set_timer(unsigned long t) +{ + timestamp = t; +} + +void udelay (unsigned long usec) +{ + unsigned long tmo,tmp; + + /* normalize */ + if (usec >= 1000) { + tmo = usec / 1000; + tmo *= TIMER_HZ; + tmo /= 1000; + } + else { + if (usec >= 1) { + tmo = usec * TIMER_HZ; + tmo /= (1000*1000); + } + else + tmo = 1; + } + + /* check for rollover during this delay */ + tmp = get_timer (0); + if ((tmp + tmo) < tmp ) + reset_timer_masked(); /* timer would roll over */ + else + tmo += tmp; + + while (get_timer_masked () < tmo); +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = READ_TIMER; + timestamp = 0; +} + +unsigned long get_timer_masked (void) +{ + unsigned long now = READ_TIMER; + + if (lastdec <= now) { + /* normal mode */ + timestamp += (now - lastdec); + } else { + /* we have an overflow ... */ + timestamp += TIMER_FDATA + now - lastdec; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked (unsigned long usec) +{ + unsigned long tmo; + unsigned long endtime; + signed long diff; + + /* normalize */ + if (usec >= 1000) { + tmo = usec / 1000; + tmo *= TIMER_HZ; + tmo /= 1000; + } else { + if (usec > 1) { + tmo = usec * TIMER_HZ; + tmo /= (1000*1000); + } else { + tmo = 1; + } + } + + endtime = get_timer_masked () + tmo; + + do { + unsigned long now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On MIPS it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On MIPS it returns the number of timer ticks per second. + */ +unsigned long get_tbclk (void) +{ + return TIMER_HZ; +} + +/* CPU-specific routines from U-Boot. + See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c + See: u-boot/arch/mips/include/asm/cacheops.h +*/ + +#define Index_Store_Tag_I 0x08 +#define Index_Writeback_Inv_D 0x15 + +void flush_icache_all(void) +{ + u32 addr, t = 0; + + asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ + asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ + + for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; + addr += CONFIG_SYS_CACHELINE_SIZE) { + asm volatile ( + ".set mips3\n\t" + " cache %0, 0(%1)\n\t" + ".set mips2\n\t" + : + : "I" (Index_Store_Tag_I), "r"(addr)); + } + + /* invalicate btb */ + asm volatile ( + ".set mips32\n\t" + "mfc0 %0, $16, 7\n\t" + "nop\n\t" + "ori %0,2\n\t" + "mtc0 %0, $16, 7\n\t" + ".set mips2\n\t" + : + : "r" (t)); +} + +void flush_dcache_all(void) +{ + u32 addr; + + for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; + addr += CONFIG_SYS_CACHELINE_SIZE) { + asm volatile ( + ".set mips3\n\t" + " cache %0, 0(%1)\n\t" + ".set mips2\n\t" + : + : "I" (Index_Writeback_Inv_D), "r"(addr)); + } + + asm volatile ("sync"); +} + +void flush_cache_all(void) +{ + flush_dcache_all(); + flush_icache_all(); +} diff -r 9469cf34aec2 -r 5d33753dfd71 stage2/board-nanonote.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage2/board-nanonote.h Sun Jun 07 23:06:08 2015 +0200 @@ -0,0 +1,17 @@ +#ifndef __BOARD_NANONOTE2_H__ +#define __BOARD_NANONOTE2_H__ + +/* Initialisation functions. */ + +void gpio_init2(void); +void cpm_init(void); +void rtc_init(void); +int timer_init(void); + +/* Utility functions. */ + +void udelay(unsigned long usec); +void flush_cache_all(void); +unsigned long get_memory_size(void); + +#endif /* __BOARD_NANONOTE2_H__ */ diff -r 9469cf34aec2 -r 5d33753dfd71 stage2/head2.S --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage2/head2.S Sun Jun 07 23:06:08 2015 +0200 @@ -0,0 +1,33 @@ +/* + * Entry point of the firmware. + * The firmware code are executed in the ICache. + * Do not edit! + * Copyright (C) 2006 Ingenic Semiconductor Inc. + * + */ + + .text + .extern c_main + + .globl _start + .set noreorder +_start: + b real_start + nop + .word 0x0 // its address == start address + 8 + .word 0x0 + .word 0x0 + .word 0x0 + .word 0x0 + .word 0x0 + .word 0x0 + .word 0x0 + +real_start: + /* setup stack, jump to C code */ + add $29, $20, 0x3ffff0 // sp locate at start address offset 0x2ffff0 + add $25, $20, 0x40 // t9 = c_main() + j $25 + nop + + .set reorder diff -r 9469cf34aec2 -r 5d33753dfd71 stage2/lcd.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage2/lcd.c Sun Jun 07 23:06:08 2015 +0200 @@ -0,0 +1,88 @@ +/* + * Ben NanoNote LCD initialisation, based on uboot-xburst and xburst-tools. + * + * Copyright (C) 2015 Paul Boddie + * Copyright (C) 2001-2002 Wolfgang Denk, DENX Software Engineering, + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License as published by the Free Software + * Foundation; either version 3 of the License, or (at your option) any later + * version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "xburst_types.h" +#include "nanonote_gpm940b0.h" +#include "board-nanonote.h" + +#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) +#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) + +unsigned long lcd_setmem(unsigned long addr) +{ + unsigned long size; + + size = lcd_get_size(); + + /* Round up to nearest full page, or MMU section if defined */ + size = ALIGN(size, PAGE_SIZE); + addr = ALIGN(addr - PAGE_SIZE + 1, PAGE_SIZE); + + /* Allocate pages for the frame buffer. */ + addr -= size; + + return addr; +} + +#define N_BLK_VERT 2 +#define N_BLK_HOR 3 + +static int test_colors[N_BLK_HOR * N_BLK_VERT] = { + 0x00ff0000, 0x0000ff00, 0x00ffff00, + 0x000000ff, 0x00ff00ff, 0x0000ffff, +}; + +static void test_pattern(void *lcd_base) +{ + unsigned short v_max = panel_info.vl_row; + unsigned short h_max = panel_info.vl_col; + unsigned short v_step = (v_max + N_BLK_VERT - 1) / N_BLK_VERT; + unsigned short h_step = (h_max + N_BLK_HOR - 1) / N_BLK_HOR; + unsigned short v, h; + unsigned char *pix = (unsigned char *)lcd_base; + + /* WARNING: Code silently assumes 8bit/pixel */ + for (v = 0; v < v_max; ++v) { + unsigned char iy = v / v_step; + for (h = 0; h < h_max; ++h) { + unsigned char ix = N_BLK_HOR * iy + h / h_step; + *pix++ = test_colors[ix]; + } + } +} + +void lcd_clear(void *lcd_base) +{ + test_pattern(lcd_base); +} + +/* LCD initialisation. */ + +static void *lcd_base; + +void lcd_init(void) +{ + /* Start from the top of memory and obtain a framebuffer region. */ + + lcd_base = (void *) lcd_setmem(get_memory_size()); + lcd_ctrl_init(lcd_base); + lcd_clear(lcd_base); + lcd_enable(); +} diff -r 9469cf34aec2 -r 5d33753dfd71 stage2/lcd.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage2/lcd.h Sun Jun 07 23:06:08 2015 +0200 @@ -0,0 +1,8 @@ +#ifndef __LCD_H__ +#define __LCD_H__ + +/* Initialisation functions. */ + +void lcd_init(void); + +#endif /* __LCD_H__ */ diff -r 9469cf34aec2 -r 5d33753dfd71 stage2/nanonote_gpm940b0.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage2/nanonote_gpm940b0.c Sun Jun 07 23:06:08 2015 +0200 @@ -0,0 +1,403 @@ +/* + * JzRISC lcd controller + * + * Copyright (C) Xiangfu Liu + * Copyright (C) 2015 Paul Boddie + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* virt_to_phys() from u-boot/arch/mips/include/asm/addrspace.h + via u-boot/arch/mips/include/asm/io.h */ +#define virt_to_phys(n) (((int) n) & 0x1fffffff) + +#include "jz4740.h" +#include "nanonote_gpm940b0.h" +#include "board-nanonote.h" + +#define align2(n) (n)=((((n)+1)>>1)<<1) +#define align4(n) (n)=((((n)+3)>>2)<<2) +#define align8(n) (n)=((((n)+7)>>3)<<3) + +struct jzfb_info { + unsigned int cfg; /* panel mode and pin usage etc. */ + unsigned int w; + unsigned int h; + unsigned int bpp; /* bit per pixel */ + unsigned int fclk; /* frame clk */ + unsigned int hsw; /* hsync width, in pclk */ + unsigned int vsw; /* vsync width, in line count */ + unsigned int elw; /* end of line, in pclk */ + unsigned int blw; /* begin of line, in pclk */ + unsigned int efw; /* end of frame, in line count */ + unsigned int bfw; /* begin of frame, in line count */ +}; + +static struct jzfb_info jzfb = { + MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N, + 320, 240, 32, 70, 1, 1, 273, 140, 1, 20 +}; + +vidinfo_t panel_info = { + 320, 240, LCD_BPP, +}; + +unsigned long lcd_get_size(void) +{ + int line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; + return line_length * panel_info.vl_row; +} + +static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid); +static void jz_lcd_desc_init(vidinfo_t *vid); +static int jz_lcd_hw_init(vidinfo_t *vid); + +void lcd_ctrl_init (void *lcdbase) +{ + jz_lcd_init_mem(lcdbase, &panel_info); + jz_lcd_desc_init(&panel_info); + jz_lcd_hw_init(&panel_info); +} + +/* + * Before enabled lcd controller, lcd registers should be configured correctly. + */ +void lcd_enable (void) +{ + REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */ + REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/ +} + +void lcd_disable (void) +{ + REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */ + /* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */ +} + +static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid) +{ + unsigned long palette_mem_size; + struct jz_fb_info *fbi = &vid->jz_fb; + int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8; + + fbi->screen = (unsigned long)lcdbase; + fbi->palette_size = 256; + palette_mem_size = fbi->palette_size * sizeof(u16); + + /* debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (unsigned long) palette_mem_size); */ + /* locate palette and descs at end of page following fb */ + fbi->palette = (unsigned long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size; + + return 0; +} + +static void jz_lcd_desc_init(vidinfo_t *vid) +{ + struct jz_fb_info * fbi; + fbi = &vid->jz_fb; + fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16); + fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16); + fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16); + + #define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8) + + /* populate descriptors */ + fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow); + fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL)); + fbi->dmadesc_fblow->fidr = 0; + fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ; + + fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */ + + fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen); + fbi->dmadesc_fbhigh->fidr = 0; + fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */ + + fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette); + fbi->dmadesc_palette->fidr = 0; + fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28); + + if(NBITS(vid->vl_bpix) < 12) + { + /* assume any mode with <12 bpp is palette driven */ + fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh); + fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette); + /* flips back and forth between pal and fbhigh */ + fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette); + } else { + /* palette shouldn't be loaded in true-color mode */ + fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh); + fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */ + } + + flush_cache_all(); +} + +static int jz_lcd_hw_init(vidinfo_t *vid) +{ + struct jz_fb_info *fbi = &vid->jz_fb; + unsigned int val = 0; + unsigned int pclk; + unsigned int stnH; + int pll_div; + + /* Setting Control register */ + switch (jzfb.bpp) { + case 1: + val |= LCD_CTRL_BPP_1; + break; + case 2: + val |= LCD_CTRL_BPP_2; + break; + case 4: + val |= LCD_CTRL_BPP_4; + break; + case 8: + val |= LCD_CTRL_BPP_8; + break; + case 15: + val |= LCD_CTRL_RGB555; + case 16: + val |= LCD_CTRL_BPP_16; + break; + case 17 ... 32: + val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */ + break; + + default: + /* printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp); */ + val |= LCD_CTRL_BPP_16; + break; + } + + switch (jzfb.cfg & MODE_MASK) { + case MODE_STN_MONO_DUAL: + case MODE_STN_COLOR_DUAL: + case MODE_STN_MONO_SINGLE: + case MODE_STN_COLOR_SINGLE: + switch (jzfb.bpp) { + case 1: + /* val |= LCD_CTRL_PEDN; */ + case 2: + val |= LCD_CTRL_FRC_2; + break; + case 4: + val |= LCD_CTRL_FRC_4; + break; + case 8: + default: + val |= LCD_CTRL_FRC_16; + break; + } + break; + } + + val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */ + val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */ + + switch (jzfb.cfg & MODE_MASK) { + case MODE_STN_MONO_DUAL: + case MODE_STN_COLOR_DUAL: + case MODE_STN_MONO_SINGLE: + case MODE_STN_COLOR_SINGLE: + switch (jzfb.cfg & STN_DAT_PINMASK) { + case STN_DAT_PIN1: + /* Do not adjust the hori-param value. */ + break; + case STN_DAT_PIN2: + align2(jzfb.hsw); + align2(jzfb.elw); + align2(jzfb.blw); + break; + case STN_DAT_PIN4: + align4(jzfb.hsw); + align4(jzfb.elw); + align4(jzfb.blw); + break; + case STN_DAT_PIN8: + align8(jzfb.hsw); + align8(jzfb.elw); + align8(jzfb.blw); + break; + } + break; + } + + REG_LCD_CTRL = val; + + switch (jzfb.cfg & MODE_MASK) { + case MODE_STN_MONO_DUAL: + case MODE_STN_COLOR_DUAL: + case MODE_STN_MONO_SINGLE: + case MODE_STN_COLOR_SINGLE: + if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) || + ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) + stnH = jzfb.h >> 1; + else + stnH = jzfb.h; + + REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; + REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw); + + /* Screen setting */ + REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw); + REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w); + REG_LCD_DAV = (0 << 16) | (stnH); + + /* AC BIAs signal */ + REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw); + + break; + + case MODE_TFT_GEN: + case MODE_TFT_SHARP: + case MODE_TFT_CASIO: + case MODE_TFT_SAMSUNG: + case MODE_8BIT_SERIAL_TFT: + case MODE_TFT_18BIT: + REG_LCD_VSYNC = (0 << 16) | jzfb.vsw; + REG_LCD_HSYNC = (0 << 16) | jzfb.hsw; + REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h); + REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w ); + REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \ + | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw); + break; + } + + switch (jzfb.cfg & MODE_MASK) { + case MODE_TFT_SAMSUNG: + { + unsigned int total, tp_s, tp_e, ckv_s, ckv_e; + unsigned int rev_s, rev_e, inv_s, inv_e; + + pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * + (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ + + total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; + tp_s = jzfb.blw + jzfb.w + 1; + tp_e = tp_s + 1; + /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */ + ckv_s = tp_s - pclk/(1000000000/4100); + ckv_e = tp_s + total; + rev_s = tp_s - 11; /* -11.5 clk */ + rev_e = rev_s + total; + inv_s = tp_s; + inv_e = inv_s + total; + REG_LCD_CLS = (tp_s << 16) | tp_e; + REG_LCD_PS = (ckv_s << 16) | ckv_e; + REG_LCD_SPL = (rev_s << 16) | rev_e; + REG_LCD_REV = (inv_s << 16) | inv_e; + jzfb.cfg |= STFT_REVHI | STFT_SPLHI; + break; + } + case MODE_TFT_SHARP: + { + unsigned int total, cls_s, cls_e, ps_s, ps_e; + unsigned int spl_s, spl_e, rev_s, rev_e; + total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw; + spl_s = 1; + spl_e = spl_s + 1; + cls_s = 0; + cls_e = total - 60; /* > 4us (pclk = 80ns) */ + ps_s = cls_s; + ps_e = cls_e; + rev_s = total - 40; /* > 3us (pclk = 80ns) */ + rev_e = rev_s + total; + jzfb.cfg |= STFT_PSHI; + REG_LCD_SPL = (spl_s << 16) | spl_e; + REG_LCD_CLS = (cls_s << 16) | cls_e; + REG_LCD_PS = (ps_s << 16) | ps_e; + REG_LCD_REV = (rev_s << 16) | rev_e; + break; + } + case MODE_TFT_CASIO: + break; + } + + /* Configure the LCD panel */ + REG_LCD_CFG = jzfb.cfg; + + /* Timing setting */ + __cpm_stop_lcd(); + + val = jzfb.fclk; /* frame clk */ + if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) { + pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) * + (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ + } else { + /* serial mode: Hsync period = 3*Width_Pixel */ + pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) * + (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */ + } + + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || + ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) + pclk = (pclk * 3); + + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || + ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) || + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) + pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4); + + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) + pclk >>= 1; + + pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */ + pll_div = pll_div ? 1 : 2 ; + val = ( __cpm_get_pllout()/pll_div ) / pclk; + val--; + if ( val > 0x1ff ) { + /* printf("CPM_LPCDR too large, set it to 0x1ff\n"); */ + val = 0x1ff; + } + __cpm_set_pixdiv(val); + + val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */ + if ( val > 150000000 ) { + /* printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val); */ + /* printf("Change LCDClock to 150MHz\n"); */ + val = 150000000; + } + val = ( __cpm_get_pllout()/pll_div ) / val; + val--; + if ( val > 0x1f ) { + /* printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n"); */ + val = 0x1f; + } + __cpm_set_ldiv( val ); + REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */ + + __cpm_start_lcd(); + udelay(1000); + + REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/ + + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) + REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/ + + return 0; +} + +void lcd_setcolreg (unsigned short regno, unsigned short red, unsigned short green, unsigned short blue) +{ +} + +void lcd_initcolregs (void) +{ +} diff -r 9469cf34aec2 -r 5d33753dfd71 stage2/nanonote_gpm940b0.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage2/nanonote_gpm940b0.h Sun Jun 07 23:06:08 2015 +0200 @@ -0,0 +1,143 @@ +/* + * JzRISC lcd controller + * + * Xiangfu Liu + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __QI_LB60_GPM940B0_H__ +#define __QI_LB60_GPM940B0_H__ + +#include "nanonote.h" +#include "jz4740_lcd.h" + +unsigned long lcd_get_size(void); +void lcd_ctrl_init(void *lcdbase); +void lcd_enable(void); +void lcd_disable(void); + +struct lcd_desc{ + unsigned int next_desc; /* LCDDAx */ + unsigned int databuf; /* LCDSAx */ + unsigned int frame_id; /* LCDFIDx */ + unsigned int cmd; /* LCDCMDx */ +}; + +#define MODE_MASK 0x0f +#define MODE_TFT_GEN 0x00 +#define MODE_TFT_SHARP 0x01 +#define MODE_TFT_CASIO 0x02 +#define MODE_TFT_SAMSUNG 0x03 +#define MODE_CCIR656_NONINT 0x04 +#define MODE_CCIR656_INT 0x05 +#define MODE_STN_COLOR_SINGLE 0x08 +#define MODE_STN_MONO_SINGLE 0x09 +#define MODE_STN_COLOR_DUAL 0x0a +#define MODE_STN_MONO_DUAL 0x0b +#define MODE_8BIT_SERIAL_TFT 0x0c + +#define MODE_TFT_18BIT (1<<7) + +#define STN_DAT_PIN1 (0x00 << 4) +#define STN_DAT_PIN2 (0x01 << 4) +#define STN_DAT_PIN4 (0x02 << 4) +#define STN_DAT_PIN8 (0x03 << 4) +#define STN_DAT_PINMASK STN_DAT_PIN8 + +#define STFT_PSHI (1 << 15) +#define STFT_CLSHI (1 << 14) +#define STFT_SPLHI (1 << 13) +#define STFT_REVHI (1 << 12) + +#define SYNC_MASTER (0 << 16) +#define SYNC_SLAVE (1 << 16) + +#define DE_P (0 << 9) +#define DE_N (1 << 9) + +#define PCLK_P (0 << 10) +#define PCLK_N (1 << 10) + +#define HSYNC_P (0 << 11) +#define HSYNC_N (1 << 11) + +#define VSYNC_P (0 << 8) +#define VSYNC_N (1 << 8) + +#define DATA_NORMAL (0 << 17) +#define DATA_INVERSE (1 << 17) + + +/* Jz LCDFB supported I/O controls. */ +#define FBIOSETBACKLIGHT 0x4688 +#define FBIODISPON 0x4689 +#define FBIODISPOFF 0x468a +#define FBIORESET 0x468b +#define FBIOPRINT_REG 0x468c + +/* + * LCD panel specific definition + */ +#define MODE (0xc9) /* 8bit serial RGB */ + +#define __spi_write_reg1(reg, val) \ +do { \ + unsigned char no; \ + unsigned short value; \ + unsigned char a=reg; \ + unsigned char b=val; \ + __gpio_set_pin(SPEN); \ + __gpio_set_pin(SPCK); \ + __gpio_clear_pin(SPDA); \ + __gpio_clear_pin(SPEN); \ + value=((a<<8)|(b&0xFF)); \ + for(no=0;no<16;no++) \ + { \ + __gpio_clear_pin(SPCK); \ + if((value&0x8000)==0x8000) \ + __gpio_set_pin(SPDA); \ + else \ + __gpio_clear_pin(SPDA); \ + __gpio_set_pin(SPCK); \ + value=(value<<1); \ + } \ + __gpio_set_pin(SPEN); \ +} while (0) + +#define __lcd_display_pin_init() \ +do { \ + __cpm_start_tcu(); \ + __gpio_as_output(SPEN); /* use SPDA */ \ + __gpio_as_output(SPCK); /* use SPCK */ \ + __gpio_as_output(SPDA); /* use SPDA */ \ +} while (0) + +#define __lcd_display_on() \ +do { \ + __spi_write_reg1(0x05, 0x1e); \ + __spi_write_reg1(0x05, 0x5e); \ + __spi_write_reg1(0x07, 0x8d); \ + __spi_write_reg1(0x13, 0x01); \ + __spi_write_reg1(0x05, 0x5f); \ +} while (0) + +#define __lcd_display_off() \ +do { \ + __spi_write_reg1(0x05, 0x5e); \ +} while (0) + +#endif /* __QI_LB60_GPM940B0_H__ */ diff -r 9469cf34aec2 -r 5d33753dfd71 stage2/stage2.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage2/stage2.c Sun Jun 07 23:06:08 2015 +0200 @@ -0,0 +1,62 @@ +/* + * Ben NanoNote stage 2 payload test. + * + * Copyright (C) 2015 Paul Boddie + * Copyright (C) Wolfgang Spraul + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License as published by the Free Software + * Foundation; either version 3 of the License, or (at your option) any later + * version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "board-nanonote.h" +#include "lcd.h" + +void c_main(void) +{ + /* Relocate object locations. */ + + volatile unsigned int start_addr, got_start, got_end, addr, offset; + + /* get absolute start address */ + __asm__ __volatile__( + "move %0, $20\n\t" + : "=r"(start_addr) + : + ); + + /* get related GOT address */ + __asm__ __volatile__( + "la $4, _GLOBAL_OFFSET_TABLE_\n\t" + "move %0, $4\n\t" + "la $5, _got_end\n\t" + "move %1, $5\n\t" + : "=r"(got_start),"=r"(got_end) + : + ); + + /* calculate offset and correct GOT*/ + offset = start_addr - 0x80000000; + got_start += offset; + got_end += offset; + + for ( addr = got_start + 8; addr < got_end; addr += 4 ) + *((volatile unsigned int *)(addr)) += offset; // add offset to correct all GOT + + /* The actual work. */ + + gpio_init2(); + cpm_init(); + rtc_init(); + timer_init(); + lcd_init(); +} diff -r 9469cf34aec2 -r 5d33753dfd71 stage2/stage2.ld --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage2/stage2.ld Sun Jun 07 23:06:08 2015 +0200 @@ -0,0 +1,32 @@ +OUTPUT_ARCH(mips) +ENTRY(_start) +MEMORY +{ + ram : ORIGIN = 0x80000000 , LENGTH = 3M +} + +SECTIONS +{ + . = ALIGN(4); + .text : { *(.text*) } > ram + + . = ALIGN(4); + .rodata : { *(.rodata*) } > ram + + . = ALIGN(4); + .sdata : { *(.sdata*) } > ram + + . = ALIGN(4); + .data : { *(.data*) *(.scommon*) *(.reginfo*) } > ram + + _gp = ALIGN(16); + + .got : { *(.got*) } > ram + _got_end = ABSOLUTE(.); + + . = ALIGN(4); + .sbss : { *(.sbss*) } > ram + .bss : { *(.bss*) } > ram + . = ALIGN (4); +} +