# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1475523970 -7200
# Node ID 5e5623094b069cf9cd95e0a62c54b61d55be3e54
# Parent  cb43c3400045deb5d3bb424600789c7c3323c73a
Changed the GPIO mapping to use uncached memory.
Added task-based GPIO input/output functions.

diff -r cb43c3400045 -r 5e5623094b06 include/mips.h
--- a/include/mips.h	Mon Oct 03 18:27:56 2016 +0200
+++ b/include/mips.h	Mon Oct 03 21:46:10 2016 +0200
@@ -27,6 +27,7 @@
 #define CAUSE_IV	0x00800000
 
 #define TLB_CACHED	0x00000018
+#define TLB_UNCACHED	0x00000010
 #define TLB_DIRTY	0x00000004
 #define TLB_VALID	0x00000002
 #define TLB_GLOBAL	0x00000001
diff -r cb43c3400045 -r 5e5623094b06 stage2/task_gpio.c
--- a/stage2/task_gpio.c	Mon Oct 03 18:27:56 2016 +0200
+++ b/stage2/task_gpio.c	Mon Oct 03 21:46:10 2016 +0200
@@ -35,10 +35,20 @@
 		virtual += page_size(STAGE2_PAGESIZE), physical += page_size(STAGE2_PAGESIZE))
 	{
 		init_page_table(STAGE2_PAGE_TABLE_BASE, virtual, physical,
-			page_size(STAGE2_PAGESIZE), TLB_WRITE, task);
+			page_size(STAGE2_PAGESIZE), TLB_UNCACHED | TLB_DIRTY | TLB_VALID, task);
 	}
 }
 
+void task_gpio_as_input(unsigned short pin)
+{
+        TASK_REG_GPIO_PXDIRC(pin / 32) = (1 << (pin % 32));
+}
+
+void task_gpio_as_output(unsigned short pin)
+{
+        TASK_REG_GPIO_PXDIRS(pin / 32) = (1 << (pin % 32));
+}
+
 inline void task_gpio_set_pin(unsigned short pin)
 {
         TASK_REG_GPIO_PXDATS(pin / 32) = (1 << (pin % 32));
diff -r cb43c3400045 -r 5e5623094b06 stage2/task_gpio.h
--- a/stage2/task_gpio.h	Mon Oct 03 18:27:56 2016 +0200
+++ b/stage2/task_gpio.h	Mon Oct 03 21:46:10 2016 +0200
@@ -11,12 +11,22 @@
 #define TASK_GPIO_PXDATS(n)	(TASK_GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
 #define TASK_GPIO_PXDATC(n)	(TASK_GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
 
-#define TASK_REG_GPIO_PXPIN(n)	REG32(TASK_GPIO_PXPIN((n)))  /* PIN level */
-#define TASK_REG_GPIO_PXDAT(n)	REG32(TASK_GPIO_PXDAT((n)))  /* 1: interrupt pending */
+#define TASK_GPIO_PXDIR(n)	(TASK_GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
+#define TASK_GPIO_PXDIRS(n)	(TASK_GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
+#define TASK_GPIO_PXDIRC(n)	(TASK_GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
+
+#define TASK_REG_GPIO_PXPIN(n)	REG32(TASK_GPIO_PXPIN((n)))
+#define TASK_REG_GPIO_PXDAT(n)	REG32(TASK_GPIO_PXDAT((n)))
 #define TASK_REG_GPIO_PXDATS(n)	REG32(TASK_GPIO_PXDATS((n)))
 #define TASK_REG_GPIO_PXDATC(n)	REG32(TASK_GPIO_PXDATC((n)))
 
+#define TASK_REG_GPIO_PXDIR(n)	REG32(TASK_GPIO_PXDIR((n)))
+#define TASK_REG_GPIO_PXDIRS(n)	REG32(TASK_GPIO_PXDIRS((n)))
+#define TASK_REG_GPIO_PXDIRC(n)	REG32(TASK_GPIO_PXDIRC((n)))
+
 void task_gpio_init(unsigned short task);
+void task_gpio_as_input(unsigned short pin);
+void task_gpio_as_output(unsigned short pin);
 void task_gpio_set_pin(unsigned short pin);
 void task_gpio_clear_pin(unsigned short pin);
 int task_gpio_get_pin(unsigned short pin);