# HG changeset patch # User Paul Boddie # Date 1499553402 -7200 # Node ID 61ef56dfab174053e84ff22b6d4b4c1582104c59 # Parent 49f8e5bfb1cd47b79e1ce7a5693128c95f6a7c75 Parameterise LCD register operations using the display information structure, setting the memory base to zero for now. diff -r 49f8e5bfb1cd -r 61ef56dfab17 stage2/jzlcd.c --- a/stage2/jzlcd.c Sat Jul 08 23:02:30 2017 +0200 +++ b/stage2/jzlcd.c Sun Jul 09 00:36:42 2017 +0200 @@ -25,11 +25,44 @@ #include "cpu.h" #include "board.h" -#define align2(n) (n)=((((n)+1)>>1)<<1) -#define align4(n) (n)=((((n)+3)>>2)<<2) -#define align8(n) (n)=((((n)+7)>>3)<<3) +extern vidinfo_t panel_info; + +/* Useful alignment operations. */ + +static inline void align2(uint32_t *n) +{ + *n = (((*n)+1)>>1)<<1; +} + +static inline void align4(uint32_t *n) +{ + *n = (((*n)+3)>>2)<<2; +} + +static inline void align8(uint32_t *n) +{ + *n = (((*n)+7)>>3)<<3; +} -extern vidinfo_t panel_info; + + +/* Register operations. */ + +static inline uint32_t lcd_ctrl_get(vidinfo_t *vid, uint32_t reg) +{ + return REG32(vid->lcd + reg); +} + +static inline void lcd_ctrl_set(vidinfo_t *vid, uint32_t reg, uint32_t value) +{ + REG32(vid->lcd + reg) = value; +} + + + +/* Configuration operations. */ + +/* Return the number of panels available. */ static uint16_t lcd_get_panels(vidinfo_t *vid) { @@ -38,6 +71,42 @@ ((jzfb->cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ? 2 : 1; } +/* Calculate and return the pixel clock frequency. */ + +static uint32_t jz_lcd_get_pixel_clock(vidinfo_t *vid) +{ + struct jzfb_info *jzfb = vid->jz_fb; + uint32_t pclk, width_cycles, mode = jzfb->cfg & MODE_MASK; + + /* + Serial mode: 3 pixel clock cycles per pixel (one per channel). + Parallel mode: 1 pixel clock cycle per pixel. + */ + + if (mode == MODE_8BIT_SERIAL_TFT) + width_cycles = jzfb->w * 3; + else + width_cycles = jzfb->w; + + /* Derive pixel clock from frame clock. */ + + pclk = jzfb->fclk * + (width_cycles + jzfb->hsw + jzfb->elw + jzfb->blw) * + (jzfb->h + jzfb->vsw + jzfb->efw + jzfb->bfw); + + if ((mode == MODE_STN_COLOR_SINGLE) || (mode == MODE_STN_COLOR_DUAL)) + pclk = (pclk * 3); + + if ((mode == MODE_STN_COLOR_SINGLE) || (mode == MODE_STN_COLOR_DUAL) || + (mode == MODE_STN_MONO_SINGLE) || (mode == MODE_STN_MONO_DUAL)) + pclk = pclk >> ((jzfb->cfg & STN_DAT_PINMASK) >> 4); + + if ((mode == MODE_STN_COLOR_DUAL) || (mode == MODE_STN_MONO_DUAL)) + pclk >>= 1; + + return pclk; +} + /* Functions returning region sizes. */ @@ -178,51 +247,56 @@ uint32_t val = 0; switch (jzfb->bpp) { - case 1: + case 1: /* val |= LCD_CTRL_PEDN; */ - case 2: + case 2: val |= LCD_CTRL_FRC_2; break; - case 4: + + case 4: val |= LCD_CTRL_FRC_4; break; - case 8: - default: + + case 8: + default: val |= LCD_CTRL_FRC_16; break; } switch (jzfb->cfg & STN_DAT_PINMASK) { - case STN_DAT_PIN1: + case STN_DAT_PIN1: /* Do not adjust the hori-param value. */ break; - case STN_DAT_PIN2: - align2(jzfb->hsw); - align2(jzfb->elw); - align2(jzfb->blw); + + case STN_DAT_PIN2: + align2(&jzfb->hsw); + align2(&jzfb->elw); + align2(&jzfb->blw); break; - case STN_DAT_PIN4: - align4(jzfb->hsw); - align4(jzfb->elw); - align4(jzfb->blw); + + case STN_DAT_PIN4: + align4(&jzfb->hsw); + align4(&jzfb->elw); + align4(&jzfb->blw); break; - case STN_DAT_PIN8: - align8(jzfb->hsw); - align8(jzfb->elw); - align8(jzfb->blw); + + case STN_DAT_PIN8: + align8(&jzfb->hsw); + align8(&jzfb->elw); + align8(&jzfb->blw); break; } - REG_LCD_VSYNC = (0 << 16) | jzfb->vsw; - REG_LCD_HSYNC = ((jzfb->blw+jzfb->w) << 16) | (jzfb->blw+jzfb->w+jzfb->hsw); + lcd_ctrl_set(vid, LCD_VSYNC, jzfb->vsw); + lcd_ctrl_set(vid, LCD_HSYNC, ((jzfb->blw+jzfb->w) << 16) | (jzfb->blw+jzfb->w+jzfb->hsw)); /* Screen setting */ - REG_LCD_VAT = ((jzfb->blw + jzfb->w + jzfb->hsw + jzfb->elw) << 16) | (stnH + jzfb->vsw + jzfb->bfw + jzfb->efw); - REG_LCD_DAH = (jzfb->blw << 16) | (jzfb->blw + jzfb->w); - REG_LCD_DAV = (0 << 16) | (stnH); + lcd_ctrl_set(vid, LCD_VAT, ((jzfb->blw + jzfb->w + jzfb->hsw + jzfb->elw) << 16) | (stnH + jzfb->vsw + jzfb->bfw + jzfb->efw)); + lcd_ctrl_set(vid, LCD_DAH, (jzfb->blw << 16) | (jzfb->blw + jzfb->w)); + lcd_ctrl_set(vid, LCD_DAV, stnH); /* AC BIAs signal */ - REG_LCD_PS = (0 << 16) | (stnH+jzfb->vsw+jzfb->efw+jzfb->bfw); + lcd_ctrl_set(vid, LCD_PS, stnH+jzfb->vsw+jzfb->efw+jzfb->bfw); return val; } @@ -230,17 +304,18 @@ static void jz_lcd_tft_init(vidinfo_t *vid) { struct jzfb_info *jzfb = vid->jz_fb; - REG_LCD_VSYNC = (0 << 16) | jzfb->vsw; - REG_LCD_HSYNC = (0 << 16) | jzfb->hsw; - REG_LCD_DAV =((jzfb->vsw+jzfb->bfw) << 16) | (jzfb->vsw +jzfb->bfw+jzfb->h); - REG_LCD_DAH = ((jzfb->hsw + jzfb->blw) << 16) | (jzfb->hsw + jzfb->blw + jzfb->w ); - REG_LCD_VAT = (((jzfb->blw + jzfb->w + jzfb->elw + jzfb->hsw)) << 16) \ - | (jzfb->vsw + jzfb->bfw + jzfb->h + jzfb->efw); + lcd_ctrl_set(vid, LCD_VSYNC, jzfb->vsw); + lcd_ctrl_set(vid, LCD_HSYNC, jzfb->hsw); + lcd_ctrl_set(vid, LCD_DAV, ((jzfb->vsw+jzfb->bfw) << 16) | (jzfb->vsw +jzfb->bfw+jzfb->h)); + lcd_ctrl_set(vid, LCD_DAH, ((jzfb->hsw + jzfb->blw) << 16) | (jzfb->hsw + jzfb->blw + jzfb->w)); + lcd_ctrl_set(vid, LCD_VAT, (((jzfb->blw + jzfb->w + jzfb->elw + jzfb->hsw)) << 16) | + (jzfb->vsw + jzfb->bfw + jzfb->h + jzfb->efw)); } -static void jz_lcd_samsung_init(uint32_t pclk, vidinfo_t *vid) +static void jz_lcd_samsung_init(vidinfo_t *vid) { struct jzfb_info *jzfb = vid->jz_fb; + uint32_t pclk = jz_lcd_get_pixel_clock(vid); uint32_t total, tp_s, tp_e, ckv_s, ckv_e; uint32_t rev_s, rev_e, inv_s, inv_e; @@ -256,10 +331,10 @@ rev_e = rev_s + total; inv_s = tp_s; inv_e = inv_s + total; - REG_LCD_CLS = (tp_s << 16) | tp_e; - REG_LCD_PS = (ckv_s << 16) | ckv_e; - REG_LCD_SPL = (rev_s << 16) | rev_e; - REG_LCD_REV = (inv_s << 16) | inv_e; + lcd_ctrl_set(vid, LCD_CLS, (tp_s << 16) | tp_e); + lcd_ctrl_set(vid, LCD_PS, (ckv_s << 16) | ckv_e); + lcd_ctrl_set(vid, LCD_SPL, (rev_s << 16) | rev_e); + lcd_ctrl_set(vid, LCD_REV, (inv_s << 16) | inv_e); jzfb->cfg |= STFT_REVHI | STFT_SPLHI; } @@ -281,208 +356,15 @@ rev_s = total - 40; /* > 3us (pclk = 80ns) */ rev_e = rev_s + total; jzfb->cfg |= STFT_PSHI; - REG_LCD_SPL = (spl_s << 16) | spl_e; - REG_LCD_CLS = (cls_s << 16) | cls_e; - REG_LCD_PS = (ps_s << 16) | ps_e; - REG_LCD_REV = (rev_s << 16) | rev_e; -} - -static uint32_t jz_lcd_get_pixel_clock(vidinfo_t *vid) -{ - struct jzfb_info *jzfb = vid->jz_fb; - uint32_t pclk; - - /* Derive pixel clock from frame clock. */ - - if ( (jzfb->cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) { - pclk = jzfb->fclk * (jzfb->w + jzfb->hsw + jzfb->elw + jzfb->blw) * - (jzfb->h + jzfb->vsw + jzfb->efw + jzfb->bfw); - } else { - /* serial mode: Hsync period = 3*Width_Pixel */ - pclk = jzfb->fclk * (jzfb->w*3 + jzfb->hsw + jzfb->elw + jzfb->blw) * - (jzfb->h + jzfb->vsw + jzfb->efw + jzfb->bfw); - } - - if (((jzfb->cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || - ((jzfb->cfg & MODE_MASK) == MODE_STN_COLOR_DUAL)) - pclk = (pclk * 3); - - if (((jzfb->cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) || - ((jzfb->cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || - ((jzfb->cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) || - ((jzfb->cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) - pclk = pclk >> ((jzfb->cfg & STN_DAT_PINMASK) >> 4); - - if (((jzfb->cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || - ((jzfb->cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) - pclk >>= 1; - - return pclk; -} - -static void jz_lcd_set_timing(uint32_t pclk) -{ - uint32_t val; - -#ifdef CONFIG_CPU_JZ4730 - val = __cpm_get_pllout() / pclk; - REG_CPM_CFCR2 = val - 1; - val = pclk * 4 ; - if ( val > 150000000 ) { - val = 150000000; - } - val = __cpm_get_pllout() / val; - val--; - if ( val > 0xF ) - val = 0xF; -#else - int pll_div; - - pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */ - pll_div = pll_div ? 1 : 2 ; - val = ( __cpm_get_pllout()/pll_div ) / pclk; - val--; - if ( val > 0x1ff ) { - val = 0x1ff; - } - __cpm_set_pixdiv(val); - - val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */ - if ( val > 150000000 ) { - val = 150000000; - } - val = ( __cpm_get_pllout()/pll_div ) / val; - val--; - if ( val > 0x1f ) { - val = 0x1f; - } -#endif - __cpm_set_ldiv( val ); - REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */ + lcd_ctrl_set(vid, LCD_SPL, (spl_s << 16) | spl_e); + lcd_ctrl_set(vid, LCD_CLS, (cls_s << 16) | cls_e); + lcd_ctrl_set(vid, LCD_PS, (ps_s << 16) | ps_e); + lcd_ctrl_set(vid, LCD_REV, (rev_s << 16) | rev_e); } -static int jz_lcd_hw_init(vidinfo_t *vid) -{ - struct jzfb_info *jzfb = vid->jz_fb; - struct jz_mem_info *fbi = &vid->jz_mem; - uint32_t val = 0; - uint32_t pclk = jz_lcd_get_pixel_clock(vid); - /* Setting Control register */ - switch (jzfb->bpp) { - case 1: - val |= LCD_CTRL_BPP_1; - break; - case 2: - val |= LCD_CTRL_BPP_2; - break; - case 4: - val |= LCD_CTRL_BPP_4; - break; - case 8: - val |= LCD_CTRL_BPP_8; - break; - case 15: - val |= LCD_CTRL_RGB555; - case 16: - val |= LCD_CTRL_BPP_16; - break; -#ifndef CONFIG_CPU_JZ4730 - case 17 ... 32: - val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */ - break; -#endif - default: - /* printf("jz_lcd.c The BPP %d is not supported\n", jzfb->bpp); */ - val |= LCD_CTRL_BPP_16; - break; - } - - switch (jzfb->cfg & MODE_MASK) { - case MODE_STN_MONO_DUAL: - case MODE_STN_COLOR_DUAL: - val |= jz_lcd_stn_init(jzfb->h >> 1, vid); - break; - - case MODE_STN_MONO_SINGLE: - case MODE_STN_COLOR_SINGLE: - val |= jz_lcd_stn_init(jzfb->h, vid); - break; - - case MODE_TFT_GEN: - case MODE_TFT_CASIO: - case MODE_8BIT_SERIAL_TFT: - case MODE_TFT_18BIT: - jz_lcd_tft_init(vid); - break; - - case MODE_TFT_SAMSUNG: - { - jz_lcd_samsung_init(pclk, vid); - break; - } - case MODE_TFT_SHARP: - { - jz_lcd_sharp_init(vid); - break; - } - - default: - break; - } - - /* Configure the LCD panel */ - - val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */ - val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */ - REG_LCD_CTRL = val; - REG_LCD_CFG = jzfb->cfg; - - /* Timing reset. */ - - __cpm_stop_lcd(); - jz_lcd_set_timing(pclk); - __cpm_start_lcd(); - udelay(1000); - - /* Configure DMA. */ - - REG_LCD_DA0 = (uint32_t) fbi->fdadr0; /* frame descriptor */ - - if (((jzfb->cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) || - ((jzfb->cfg & MODE_MASK) == MODE_STN_MONO_DUAL)) - REG_LCD_DA1 = (uint32_t) fbi->fdadr1; /* frame descriptor */ - - return 0; -} - -/* Public operations. */ - -void lcd_set_bpp(uint8_t bpp) -{ - vidinfo_t *vid = &panel_info; - struct jzfb_info *jzfb = vid->jz_fb; - jzfb->bpp = bpp; -} - -void lcd_enable() -{ - /* Clear the disable bit and set the enable bit. */ - - REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */ - REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/ -} - -void lcd_disable() -{ - REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */ -} - -void lcd_quick_disable() -{ - REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.ENA, quick disable */ -} +/* Palette initialisation. */ static inline uint16_t rgb8_to_rgb16(uint8_t rgb) { @@ -496,7 +378,7 @@ static void lcd_init_palette(vidinfo_t *vid) { - uint16_t *palette = (uint16_t *) lcd_get_palette(get_memory_size(), vid); + uint16_t *palette = (uint16_t *) vid->jz_mem.palette; uint16_t *end = (uint16_t *) palette + (1 << (vid->jz_fb->bpp)); uint8_t value = 0; @@ -519,6 +401,189 @@ } } + + +static void jz_lcd_set_timing(vidinfo_t *vid) +{ + uint32_t pclk = jz_lcd_get_pixel_clock(vid); + uint32_t val; + +#ifdef CONFIG_CPU_JZ4730 + val = __cpm_get_pllout() / pclk; + lcd_ctrl_set(vid, CPM_CFCR2, val - 1); + val = pclk * 4 ; + if ( val > 150000000 ) { + val = 150000000; + } + val = __cpm_get_pllout() / val; + val--; + if ( val > 0xF ) + val = 0xF; +#else + int pll_div; + + pll_div = lcd_ctrl_get(vid, CPM_CPCCR) & lcd_ctrl_get(vid, CPM_CPCCR_PCS); /* clock source,0:pllout/2 1: pllout */ + pll_div = pll_div ? 1 : 2 ; + val = ( __cpm_get_pllout()/pll_div ) / pclk; + val--; + if ( val > 0x1ff ) { + val = 0x1ff; + } + __cpm_set_pixdiv(val); + + val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */ + if ( val > 150000000 ) { + val = 150000000; + } + val = ( __cpm_get_pllout()/pll_div ) / val; + val--; + if ( val > 0x1f ) { + val = 0x1f; + } +#endif + __cpm_set_ldiv( val ); + lcd_ctrl_set(vid, CPM_CPCCR, lcd_ctrl_get(vid, CPM_CPCCR) | CPM_CPCCR_CE); /* update divide */ +} + +static void jz_lcd_hw_init(vidinfo_t *vid) +{ + struct jzfb_info *jzfb = vid->jz_fb; + uint32_t val = 0; + + /* Compute control register flags. */ + + switch (jzfb->bpp) { + case 1: + val |= LCD_CTRL_BPP_1; + break; + + case 2: + val |= LCD_CTRL_BPP_2; + break; + + case 4: + val |= LCD_CTRL_BPP_4; + break; + + case 8: + val |= LCD_CTRL_BPP_8; + break; + + case 15: + val |= LCD_CTRL_RGB555; + case 16: + val |= LCD_CTRL_BPP_16; + break; + + case 17 ... 32: + val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */ + break; + + default: + val |= LCD_CTRL_BPP_16; /* default to 16bpp */ + break; + } + + /* Set various configuration registers for the panel. */ + + switch (jzfb->cfg & MODE_MASK) { + case MODE_STN_MONO_DUAL: + case MODE_STN_COLOR_DUAL: + val |= jz_lcd_stn_init(jzfb->h >> 1, vid); + break; + + case MODE_STN_MONO_SINGLE: + case MODE_STN_COLOR_SINGLE: + val |= jz_lcd_stn_init(jzfb->h, vid); + break; + + case MODE_TFT_GEN: + case MODE_TFT_CASIO: + case MODE_8BIT_SERIAL_TFT: + case MODE_TFT_18BIT: + jz_lcd_tft_init(vid); + break; + + case MODE_TFT_SAMSUNG: + jz_lcd_samsung_init(vid); + break; + + case MODE_TFT_SHARP: + jz_lcd_sharp_init(vid); + break; + + default: + break; + } + + /* Further control register and panel configuration. */ + + val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */ + val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */ + + lcd_ctrl_set(vid, LCD_CTRL, val); + lcd_ctrl_set(vid, LCD_CFG, jzfb->cfg); +} + +static void jz_lcd_timing_init(vidinfo_t *vid) +{ + __cpm_stop_lcd(); + jz_lcd_set_timing(vid); + __cpm_start_lcd(); + udelay(1000); +} + +/* Initialise DMA for the driver. */ + +static void jz_lcd_dma_init(vidinfo_t *vid) +{ + struct jz_mem_info *fbi = &vid->jz_mem; + uint32_t mode = vid->jz_fb->cfg & MODE_MASK; + + /* Configure DMA by setting frame descriptor addresses. */ + + lcd_ctrl_set(vid, LCD_DA0, (uint32_t) fbi->fdadr0); + + if ((mode == MODE_STN_COLOR_DUAL) || (mode == MODE_STN_MONO_DUAL)) + lcd_ctrl_set(vid, LCD_DA1, (uint32_t) fbi->fdadr1); +} + +/* Public operations. */ + +void lcd_set_bpp(uint8_t bpp) +{ + vidinfo_t *vid = &panel_info; + struct jzfb_info *jzfb = vid->jz_fb; + jzfb->bpp = bpp; +} + +void lcd_enable() +{ + vidinfo_t *vid = &panel_info; + + /* Clear the disable bit (DIS) and set the enable bit (ENA). */ + + lcd_ctrl_set(vid, LCD_CTRL, (lcd_ctrl_get(vid, LCD_CTRL) & ~LCD_CTRL_DIS) | LCD_CTRL_ENA); +} + +void lcd_disable() +{ + vidinfo_t *vid = &panel_info; + + /* Set the disable bit (DIS). */ + + lcd_ctrl_set(vid, LCD_CTRL, lcd_ctrl_get(vid, LCD_CTRL) | LCD_CTRL_DIS); +} + +void lcd_quick_disable() +{ + vidinfo_t *vid = &panel_info; + + /* Clear the enable bit (ENA) for quick disable. */ + + lcd_ctrl_set(vid, LCD_CTRL, lcd_ctrl_get(vid, LCD_CTRL) & ~LCD_CTRL_ENA); +} + uint32_t lcd_ctrl_init() { vidinfo_t *vid = &panel_info; @@ -534,6 +599,8 @@ jz_lcd_desc_init(vid); jz_lcd_hw_init(vid); + jz_lcd_timing_init(vid); + jz_lcd_dma_init(vid); return fbi->screen; } diff -r 49f8e5bfb1cd -r 61ef56dfab17 stage2/jzlcd.h --- a/stage2/jzlcd.h Sat Jul 08 23:02:30 2017 +0200 +++ b/stage2/jzlcd.h Sun Jul 09 00:36:42 2017 +0200 @@ -32,56 +32,57 @@ void lcd_enable(); void lcd_disable(); -/* - * Framebuffer characteristics - */ +/* Framebuffer characteristics. */ + struct jzfb_info { uint32_t cfg; /* panel mode and pin usage etc. */ - uint16_t w; - uint16_t h; - uint8_t bpp; /* bit per pixel */ - uint32_t fclk; /* frame clk */ - uint32_t hsw; /* hsync width, in pclk */ + uint16_t w; /* display width in pixels */ + uint16_t h; /* display height in pixels */ + uint8_t bpp; /* bits per pixel */ + uint32_t fclk; /* frame clock */ + uint32_t hsw; /* hsync width, in pixel clock */ uint32_t vsw; /* vsync width, in line count */ - uint32_t elw; /* end of line, in pclk */ - uint32_t blw; /* begin of line, in pclk */ + uint32_t elw; /* end of line, in pixel clock */ + uint32_t blw; /* begin of line, in pixel clock */ uint32_t efw; /* end of frame, in line count */ uint32_t bfw; /* begin of frame, in line count */ }; -/* - * LCD controller stucture for JZSOC: JZ4740 - */ +/* LCD controller stucture for jz4740. */ + struct jz_fb_dma_descriptor { - struct jz_fb_dma_descriptor *fdadr; /* Frame descriptor address register */ - uint32_t fsadr; /* Frame source address register */ - uint32_t fidr; /* Frame ID register */ - uint32_t ldcmd; /* Command register */ + struct jz_fb_dma_descriptor *fdadr; /* frame descriptor address register */ + uint32_t fsadr; /* frame source address register */ + uint32_t fidr; /* frame identifier register */ + uint32_t ldcmd; /* command register */ }; -/* - * Jz LCD info - */ +/* Framebuffer and controller memory information. */ + struct jz_mem_info { + /* DMA descriptor references (updated for transfers). */ + struct jz_fb_dma_descriptor *fdadr0; /* physical address of frame/palette descriptor */ struct jz_fb_dma_descriptor *fdadr1; /* physical address of frame descriptor */ - /* DMA descriptors */ + /* DMA descriptor references (indicating allocated regions). */ + struct jz_fb_dma_descriptor *dmadesc_fblow; struct jz_fb_dma_descriptor *dmadesc_fbhigh; struct jz_fb_dma_descriptor *dmadesc_palette; - uint32_t screen; /* address of frame buffer */ + uint32_t screen; /* address of first frame buffer (base of memory used) */ uint32_t palette; /* address of palette memory */ + uint32_t total; /* total memory used */ }; -/* - * Concise display characteristics with low-level structure reference - */ +/* Display characteristics and memory resources. */ + typedef struct vidinfo { - struct jz_mem_info jz_mem; - struct jzfb_info *jz_fb; + struct jzfb_info *jz_fb; /* framebuffer and panel properties */ + struct jz_mem_info jz_mem; /* framebuffer memory information */ + void *lcd; /* address of LCD controller registers */ } vidinfo_t; /* Alignment/rounding macros. */ diff -r 49f8e5bfb1cd -r 61ef56dfab17 stage2/minipc_claa070vc01.c --- a/stage2/minipc_claa070vc01.c Sat Jul 08 23:02:30 2017 +0200 +++ b/stage2/minipc_claa070vc01.c Sun Jul 09 00:36:42 2017 +0200 @@ -30,5 +30,6 @@ }; vidinfo_t panel_info = { - .jz_fb=&jzfb // this will need correcting for user mode usage + .jz_fb=&jzfb, // this will need correcting for user mode usage + .lcd=0, // base address for registers }; diff -r 49f8e5bfb1cd -r 61ef56dfab17 stage2/nanonote_gpm940b0.c --- a/stage2/nanonote_gpm940b0.c Sat Jul 08 23:02:30 2017 +0200 +++ b/stage2/nanonote_gpm940b0.c Sun Jul 09 00:36:42 2017 +0200 @@ -35,5 +35,6 @@ }; vidinfo_t panel_info = { - .jz_fb=&jzfb // this will need correcting for user mode usage + .jz_fb=&jzfb, // this will need correcting for user mode usage + .lcd=0, // base address for registers };