# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1449181488 -3600
# Node ID 7d722b8de42e93ff2ddcd28b76aaa5d3e3b3b6db
# Parent  064b3f328d90dd1c095d2574399ddf0e059a1501
Changed the payload to load at 0x80000000, positioning the vectors at the base
of the payload, with the start of the main program at 0x80001000.
Changed the boot script to actually work with USB Boot, given possible problems
with the provided stage1 payload (and nonsensical xbboot/usbboot behaviour).

diff -r 064b3f328d90 -r 7d722b8de42e boot_usb
--- a/boot_usb	Tue Jun 30 16:09:27 2015 +0200
+++ b/boot_usb	Thu Dec 03 23:24:48 2015 +0100
@@ -1,10 +1,3 @@
 #!/bin/sh
 
-xbboot set_addr 0x80002000
-xbboot bulk_write stage1/stage1.bin
-xbboot start1 0x80002000
-xbboot get_info
-xbboot flush_cache
-xbboot set_addr 0x80010000
-xbboot bulk_write stage2/stage2.bin
-xbboot start2 0x80010000
+xbboot -u 0x80001000 stage2/stage2.bin
diff -r 064b3f328d90 -r 7d722b8de42e stage2/Makefile
--- a/stage2/Makefile	Tue Jun 30 16:09:27 2015 +0200
+++ b/stage2/Makefile	Thu Dec 03 23:24:48 2015 +0100
@@ -76,7 +76,7 @@
 	echo "Nothing else to clean."
 
 $(UIMAGE): $(PAYLOAD)
-	$(MKIMAGE) -A mips -O linux -T kernel -C none -a 0x80010000 -e 0x80010000 -n NanoPayload -d $(PAYLOAD) $(UIMAGE)
+	$(MKIMAGE) -A mips -O linux -T kernel -C none -a 0x80000000 -e 0x80001000 -n NanoPayload -d $(PAYLOAD) $(UIMAGE)
 
 $(PAYLOAD): $(TARGET)
 	$(OBJCOPY) -O binary $(@:.bin=.elf) $@+
diff -r 064b3f328d90 -r 7d722b8de42e stage2/entry.S
--- a/stage2/entry.S	Tue Jun 30 16:09:27 2015 +0200
+++ b/stage2/entry.S	Thu Dec 03 23:24:48 2015 +0100
@@ -19,37 +19,34 @@
 
 .text
 .extern real_exception_handler
-.globl _tlb_entry
-.globl _cache_entry
-.globl _exc_entry
-.globl _irq_entry
-.globl _end_entries
 .set noreorder
 
+.section .vectors
 _tlb_entry:
 	lui $k0, %hi(real_exception_handler)
 	ori $k0, $k0, %lo(real_exception_handler)
 	jr $k0
 	nop
 
+.org 0x100
 _cache_entry:
 	lui $k0, %hi(real_exception_handler)
 	ori $k0, $k0, %lo(real_exception_handler)
 	jr $k0
 	nop
 
+.org 0x180
 _exc_entry:
 	lui $k0, %hi(real_exception_handler)
 	ori $k0, $k0, %lo(real_exception_handler)
 	jr $k0
 	nop
 
+.org 0x200
 _irq_entry:
 	lui $k0, %hi(real_exception_handler)
 	ori $k0, $k0, %lo(real_exception_handler)
 	jr $k0
 	nop
 
-_end_entries:
-
 .set reorder
diff -r 064b3f328d90 -r 7d722b8de42e stage2/head2.S
--- a/stage2/head2.S	Tue Jun 30 16:09:27 2015 +0200
+++ b/stage2/head2.S	Thu Dec 03 23:24:48 2015 +0100
@@ -22,10 +22,6 @@
 
 .text
 .extern c_main
-.extern _tlb_entry
-.extern _exc_entry
-.extern _irq_entry
-.extern _end_entries
 .globl _start
 .set noreorder
 
@@ -39,61 +35,13 @@
 	lui $gp, %hi(_GLOBAL_OFFSET_TABLE_)
 	ori $gp, $gp, %lo(_GLOBAL_OFFSET_TABLE_)
 
-	/* Copy TLB handling instructions. */
-
-	la $t0, _tlb_entry		/* start */
-	li $t1, 0x80000000
-	la $t2, _cache_entry		/* end */
-_tlb_copy:
-	lw $t3, 0($t0)
-	addiu $t0, $t0, 4
-	sw $t3, 0($t1)
-	bne $t0, $t2, _tlb_copy
-	addiu $t1, $t1, 4		/* executed in delay slot before branch */
-
-	/* Copy cache handling instructions. */
-
-	move $t0, $t2			/* start */
-	li $t1, 0x80000100
-	la $t2, _exc_entry		/* end */
-_cache_copy:
-	lw $t3, 0($t0)
-	addiu $t0, $t0, 4
-	sw $t3, 0($t1)
-	bne $t0, $t2, _cache_copy
-	addiu $t1, $t1, 4		/* executed in delay slot before branch */
-
-	/* Copy exception handling instructions. */
-
-	move $t0, $t2			/* start */
-	li $t1, 0x80000180
-	la $t2, _irq_entry		/* end */
-_exc_copy:
-	lw $t3, 0($t0)
-	addiu $t0, $t0, 4
-	sw $t3, 0($t1)
-	bne $t0, $t2, _exc_copy
-	addiu $t1, $t1, 4		/* executed in delay slot before branch */
-
-	/* Copy IRQ handling instructions. */
-
-	move $t0, $t2			/* start */
-	li $t1, 0x80000200
-	la $t2, _end_entries		/* end */
-_irq_copy:
-	lw $t3, 0($t0)
-	addiu $t0, $t0, 4
-	sw $t3, 0($t1)
-	bne $t0, $t2, _irq_copy
-	addiu $t1, $t1, 4		/* executed in delay slot before branch */
-
 	/* Initialise interrupts. */
 
 	mfc0 $t3, $12			/* CP0_STATUS */
 	nop
-	li $t4, 0xffbf00e0		/* BEV = 0 (not bootloader vectors); IM = disable all */
-	and $t3, $t3, $t4		/* ... KSU = 0 (kernel mode); ERL = 0; EXL = 0; IE = 0 */
-	li $t4, 0x0000ff04		/* IM = enable IM7..IM0; ERL = 1 (set by default) */
+	li $t4, 0xffbf00e4		/* BEV = 0 (not bootloader vectors); IM = disable all */
+	and $t3, $t3, $t4		/* ... KSU = 0 (kernel mode); EXL = 0; IE = 0 */
+	li $t4, 0x0000ff00		/* IM = enable IM7..IM0 */
 	or $t3, $t3, $t4
 	mtc0 $t3, $12
 	nop
diff -r 064b3f328d90 -r 7d722b8de42e stage2/stage2.ld
--- a/stage2/stage2.ld	Tue Jun 30 16:09:27 2015 +0200
+++ b/stage2/stage2.ld	Thu Dec 03 23:24:48 2015 +0100
@@ -5,7 +5,10 @@
 {
 	/* Program memory section. */
 
-	. = 0x80010000;
+	. = 0x80000000;
+	.vectors : { *(.vectors*) }
+
+	. = 0x80001000;
 	.text2 : { *(.text*) }
 
 	. = ALIGN(4);