# HG changeset patch # User Paul Boddie # Date 1462373955 -7200 # Node ID 8b4c47d9d10a3acb0e194bef0d615f3fd6e38da8 # Parent 34f40000b77921770310b1bb188c7f2f6bef4adc Introduced MIPS register definition symbols. diff -r 34f40000b779 -r 8b4c47d9d10a include/mips.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/include/mips.h Wed May 04 16:59:15 2016 +0200 @@ -0,0 +1,19 @@ +#ifndef __MIPS_H__ +#define __MIPS_H__ + +#define CP0_INDEX $0 +#define CP0_ENTRYLO0 $2 +#define CP0_ENTRYLO1 $3 +#define CP0_CONTEXT $4 +#define CP0_PAGEMASK $5 +#define CP0_WIRED $6 +#define CP0_ENTRYHI $10 +#define CP0_STATUS $12 +#define CP0_CAUSE $13 +#define CP0_EPC $14 +#define CP0_CONFIG $16 +#define CP0_WATCHLO $18 +#define CP0_TAGLO $28 +#define CP0_TAGHI $29 + +#endif /* __MIPS_H__ */ diff -r 34f40000b779 -r 8b4c47d9d10a stage1/head1.S --- a/stage1/head1.S Tue Apr 26 18:02:51 2016 +0200 +++ b/stage1/head1.S Wed May 04 16:59:15 2016 +0200 @@ -25,8 +25,7 @@ .globl _start .set noreorder -#define CP0_STATUS $12 -#define CP0_CAUSE $13 +#include "mips.h" _start: b real_start diff -r 34f40000b779 -r 8b4c47d9d10a stage2/entry.S --- a/stage2/entry.S Tue Apr 26 18:02:51 2016 +0200 +++ b/stage2/entry.S Wed May 04 16:59:15 2016 +0200 @@ -17,6 +17,9 @@ * along with this program. If not, see . */ +#include "mips.h" +#include "paging.h" + .text .extern interrupt_handler .extern current_registers @@ -27,12 +30,10 @@ .globl _end_entries .set noreorder -#include "paging.h" - _tlb_entry: /* Get the bad address. */ - mfc0 $k0, $10 /* CP0_ENTRYHI */ + mfc0 $k0, CP0_ENTRYHI nop andi $k1, $k0, 0xff /* ASID */ @@ -49,18 +50,18 @@ li $k1, page_table_start /* page_table */ addu $k1, $k0, $k1 /* page_table[ASID] */ - mfc0 $k0, $4 /* CP0_CONTEXT */ + mfc0 $k0, CP0_CONTEXT nop srl $k0, $k0, 1 /* use 8 byte - not 16 byte - entries */ addu $k0, $k0, $k1 /* page_table[ASID][entry] */ lw $k1, 0($k0) /* page_table[ASID][entry][0] */ - mtc0 $k1, $2 /* CP0_ENTRYLO0 */ + mtc0 $k1, CP0_ENTRYLO0 lw $k1, 4($k0) /* page_table[ASID][entry][1] */ - mtc0 $k1, $3 /* CP0_ENTRYLO1 */ + mtc0 $k1, CP0_ENTRYLO1 /* page size is 4KB */ - mtc0 $zero, $5 /* CP0_PAGEMASK */ + mtc0 $zero, CP0_PAGEMASK nop tlbwr @@ -77,11 +78,11 @@ srl $k0, $k0, 6 /* PFN (maintain 8KB resolution, bit 6 remaining zero) */ ori $k0, $k0, 0x1e /* flags */ - mtc0 $k0, $2 /* CP0_ENTRYLO0 */ + mtc0 $k0, CP0_ENTRYLO0 ori $k0, $k0, 0x40 /* page size is 4KB (bit 6 set) */ - mtc0 $k0, $3 /* CP0_ENTRYLO1 */ + mtc0 $k0, CP0_ENTRYLO1 nop /* page size is 4KB */ - mtc0 $zero, $5 /* CP0_PAGEMASK */ + mtc0 $zero, CP0_PAGEMASK nop tlbwr @@ -93,7 +94,7 @@ _exc_entry: /* Handle TLB refill exceptions. */ - mfc0 $k0, $13 /* CP0_CAUSE */ + mfc0 $k0, CP0_CAUSE li $k1, 0x0000007c and $k0, $k0, $k1 /* ExcCode << 2 */ srl $k0, $k0, 2 /* ExcCode */ @@ -109,7 +110,7 @@ _irq_entry: /* Set the ASID. */ - mtc0 $zero, $10 /* CP0_ENTRYHI */ + mtc0 $zero, CP0_ENTRYHI nop /* Obtain the kernel global offset table. */ diff -r 34f40000b779 -r 8b4c47d9d10a stage2/handlers.S --- a/stage2/handlers.S Tue Apr 26 18:02:51 2016 +0200 +++ b/stage2/handlers.S Wed May 04 16:59:15 2016 +0200 @@ -18,6 +18,8 @@ * along with this program. If not, see . */ +#include "mips.h" + .text .extern irq_handle .extern current_registers @@ -49,7 +51,7 @@ la $k0, current_task lw $k1, 0($k0) - mtc0 $k1, $10 /* CP0_ENTRYHI */ + mtc0 $k1, CP0_ENTRYHI nop /* Obtain the current task's registers. */ @@ -92,7 +94,7 @@ sw $fp, 108($k1) - mfc0 $k0, $14 /* CP0_EPC */ + mfc0 $k0, CP0_EPC nop sw $k0, 116($k1) @@ -140,7 +142,7 @@ lw $ra, 112($k1) lw $k0, 116($k1) - mtc0 $k0, $14 /* CP0_EPC */ + mtc0 $k0, CP0_EPC nop lw $k0, 120($k1) diff -r 34f40000b779 -r 8b4c47d9d10a stage2/head2.S --- a/stage2/head2.S Tue Apr 26 18:02:51 2016 +0200 +++ b/stage2/head2.S Wed May 04 16:59:15 2016 +0200 @@ -20,6 +20,7 @@ * along with this program. If not, see . */ +#include "mips.h" #include "sdram.h" .text @@ -99,7 +100,7 @@ /* Enable caching. */ li $t0, CONFIG_CM_CACHABLE_NONCOHERENT - mtc0 $t0, $16 /* CP0_CONFIG */ + mtc0 $t0, CP0_CONFIG nop /* Start the program. */