# HG changeset patch # User Paul Boddie # Date 1433694084 -7200 # Node ID 9904a4a3b363b801bf118cf4826c451a6c4433d6 # Parent 6fe88df663446799b65a42328a2d4ca975ec483e Split initialisation into separate stage-related files. Fixed the system map file generation in the Makefile. Tidied up the assembly language header sections. diff -r 6fe88df66344 -r 9904a4a3b363 Makefile --- a/Makefile Sun Jun 07 02:20:54 2015 +0200 +++ b/Makefile Sun Jun 07 18:21:24 2015 +0200 @@ -28,7 +28,7 @@ # NOTE: See: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=56888 ASM_INC = /usr/src/linux-headers-4.0.0-1-common/arch/mips/include -CFLAGS = -O2 -Wall -fno-pic -fno-unit-at-a-time -fno-zero-initialized-in-bss \ +CFLAGS = -O2 -Wall -fno-unit-at-a-time -fno-zero-initialized-in-bss \ -ffreestanding -fno-hosted -fno-builtin \ -march=mips32 -mno-abicalls \ -Iinclude -I$(ASM_INC) -I$(ASM_INC)/asm/mach-generic @@ -42,9 +42,9 @@ # Ordering of objects is important and cannot be left to replacement rules. SRC1 = head1.S stage1.c board-nanonote.c -SRC2 = head2.S stage2.c board-nanonote.c nanonote_gpm940b0.c lcd.c +SRC2 = head2.S stage2.c board-nanonote2.c nanonote_gpm940b0.c lcd.c OBJ1 = head1.o stage1.o board-nanonote.o -OBJ2 = head2.o stage2.o board-nanonote.o nanonote_gpm940b0.o lcd.o +OBJ2 = head2.o stage2.o board-nanonote2.o nanonote_gpm940b0.o lcd.o OBJ = $(OBJ1) $(OBJ2) .PHONY: all clean distclean @@ -61,7 +61,7 @@ $(OBJCOPY) -O binary $(@:.bin=.elf) $@+ $(OBJDUMP) -D $(@:.bin=.elf) > $(@:.bin=.dump) $(OBJDUMP) -h $(@:.bin=.elf) > $(@:.bin=.map) - $(NM) -n $< > System-$(@:.bin=.map) + $(NM) -n $(@:.bin=.elf) > System-$(@:.bin=.map) chmod -x $@+ mv -f $@+ $@ diff -r 6fe88df66344 -r 9904a4a3b363 board-nanonote.c --- a/board-nanonote.c Sun Jun 07 02:20:54 2015 +0200 +++ b/board-nanonote.c Sun Jun 07 18:21:24 2015 +0200 @@ -80,72 +80,6 @@ __gpio_as_sdram_32bit(); } -void gpio_init2(void) -{ - /* - * Initialize LCD pins - */ - __gpio_as_slcd_8bit(); - - /* - * Initialize MSC pins - */ - __gpio_as_msc(); - - /* - * Initialize Other pins - */ - unsigned int i; - for (i = 0; i < 7; i++){ - __gpio_as_input(GPIO_KEYIN_BASE + i); - __gpio_enable_pull(GPIO_KEYIN_BASE + i); - } - - for (i = 0; i < 8; i++) { - __gpio_as_output(GPIO_KEYOUT_BASE + i); - __gpio_clear_pin(GPIO_KEYOUT_BASE + i); - } - - /* enable the TP4, TP5 as UART0 */ - __gpio_jtag_to_uart0(); - - __gpio_as_input(GPIO_KEYIN_8); - __gpio_enable_pull(GPIO_KEYIN_8); - - __gpio_as_output(GPIO_AUDIO_POP); - __gpio_set_pin(GPIO_AUDIO_POP); - - __gpio_as_output(GPIO_LCD_CS); - __gpio_clear_pin(GPIO_LCD_CS); - - __gpio_as_output(GPIO_AMP_EN); - __gpio_clear_pin(GPIO_AMP_EN); - - __gpio_as_output(GPIO_SDPW_EN); - __gpio_disable_pull(GPIO_SDPW_EN); - __gpio_clear_pin(GPIO_SDPW_EN); - - __gpio_as_input(GPIO_SD_DETECT); - __gpio_disable_pull(GPIO_SD_DETECT); - - __gpio_as_input(GPIO_USB_DETECT); - __gpio_enable_pull(GPIO_USB_DETECT); -} - -void cpm_init(void) -{ - __cpm_stop_ipu(); - __cpm_stop_cim(); - __cpm_stop_i2c(); - __cpm_stop_ssi(); - __cpm_stop_uart1(); - __cpm_stop_sadc(); - __cpm_stop_uhc(); - __cpm_stop_udc(); - __cpm_stop_aic1(); -/* __cpm_stop_aic2();*/ -} - void pll_init(void) { register unsigned int cfcr, plcr1; @@ -278,244 +212,3 @@ /* everything is ok now */ } - -void rtc_init(void) -{ - while ( !__rtc_write_ready()); - __rtc_enable_alarm(); /* enable alarm */ - - while ( !__rtc_write_ready()); - REG_RTC_RGR = 0x00007fff; /* type value */ - - while ( !__rtc_write_ready()); - REG_RTC_HWFCR = 0x0000ffe0; /* Power on delay 2s */ - - while ( !__rtc_write_ready()); - REG_RTC_HRCR = 0x00000fe0; /* reset delay 125ms */ -} - -unsigned long get_memory_size(void) -{ - unsigned int dmcr; - unsigned int rows, cols, dw, banks; - unsigned long size; - - dmcr = REG_EMC_DMCR; - rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT); - cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT); - dw = (dmcr & EMC_DMCR_BW) ? 2 : 4; - banks = (dmcr & EMC_DMCR_BA) ? 4 : 2; - - size = (1 << (rows + cols)) * dw * banks; - - return size; -} - -/* Timer routines. */ - -#define TIMER_CHAN 0 -#define TIMER_FDATA 0xffff /* Timer full data value */ -#define TIMER_HZ CONFIG_SYS_HZ - -#define READ_TIMER REG_TCU_TCNT(TIMER_CHAN) /* macro to read the 16 bit timer */ - -static unsigned long timestamp; -static unsigned long lastdec; - -void reset_timer_masked(void); -unsigned long get_timer_masked(void); -void udelay_masked(unsigned long usec); - -/* - * timer without interrupts - */ - -int timer_init(void) -{ - REG_TCU_TCSR(TIMER_CHAN) = TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN; - REG_TCU_TCNT(TIMER_CHAN) = 0; - REG_TCU_TDHR(TIMER_CHAN) = 0; - REG_TCU_TDFR(TIMER_CHAN) = TIMER_FDATA; - - REG_TCU_TMSR = (1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)); /* mask irqs */ - REG_TCU_TSCR = (1 << TIMER_CHAN); /* enable timer clock */ - REG_TCU_TESR = (1 << TIMER_CHAN); /* start counting up */ - - lastdec = 0; - timestamp = 0; - - return 0; -} - -void reset_timer(void) -{ - reset_timer_masked (); -} - -unsigned long get_timer(unsigned long base) -{ - return get_timer_masked () - base; -} - -void set_timer(unsigned long t) -{ - timestamp = t; -} - -void udelay (unsigned long usec) -{ - unsigned long tmo,tmp; - - /* normalize */ - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= TIMER_HZ; - tmo /= 1000; - } - else { - if (usec >= 1) { - tmo = usec * TIMER_HZ; - tmo /= (1000*1000); - } - else - tmo = 1; - } - - /* check for rollover during this delay */ - tmp = get_timer (0); - if ((tmp + tmo) < tmp ) - reset_timer_masked(); /* timer would roll over */ - else - tmo += tmp; - - while (get_timer_masked () < tmo); -} - -void reset_timer_masked (void) -{ - /* reset time */ - lastdec = READ_TIMER; - timestamp = 0; -} - -unsigned long get_timer_masked (void) -{ - unsigned long now = READ_TIMER; - - if (lastdec <= now) { - /* normal mode */ - timestamp += (now - lastdec); - } else { - /* we have an overflow ... */ - timestamp += TIMER_FDATA + now - lastdec; - } - lastdec = now; - - return timestamp; -} - -void udelay_masked (unsigned long usec) -{ - unsigned long tmo; - unsigned long endtime; - signed long diff; - - /* normalize */ - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= TIMER_HZ; - tmo /= 1000; - } else { - if (usec > 1) { - tmo = usec * TIMER_HZ; - tmo /= (1000*1000); - } else { - tmo = 1; - } - } - - endtime = get_timer_masked () + tmo; - - do { - unsigned long now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On MIPS it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On MIPS it returns the number of timer ticks per second. - */ -unsigned long get_tbclk (void) -{ - return TIMER_HZ; -} - -/* CPU-specific routines from U-Boot. - See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c - See: u-boot/arch/mips/include/asm/cacheops.h -*/ - -#define Index_Store_Tag_I 0x08 -#define Index_Writeback_Inv_D 0x15 - -void flush_icache_all(void) -{ - u32 addr, t = 0; - - asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ - asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ - - for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; - addr += CONFIG_SYS_CACHELINE_SIZE) { - asm volatile ( - ".set mips3\n\t" - " cache %0, 0(%1)\n\t" - ".set mips2\n\t" - : - : "I" (Index_Store_Tag_I), "r"(addr)); - } - - /* invalicate btb */ - asm volatile ( - ".set mips32\n\t" - "mfc0 %0, $16, 7\n\t" - "nop\n\t" - "ori %0,2\n\t" - "mtc0 %0, $16, 7\n\t" - ".set mips2\n\t" - : - : "r" (t)); -} - -void flush_dcache_all(void) -{ - u32 addr; - - for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; - addr += CONFIG_SYS_CACHELINE_SIZE) { - asm volatile ( - ".set mips3\n\t" - " cache %0, 0(%1)\n\t" - ".set mips2\n\t" - : - : "I" (Index_Writeback_Inv_D), "r"(addr)); - } - - asm volatile ("sync"); -} - -void flush_cache_all(void) -{ - flush_dcache_all(); - flush_icache_all(); -} diff -r 6fe88df66344 -r 9904a4a3b363 board-nanonote.h --- a/board-nanonote.h Sun Jun 07 02:20:54 2015 +0200 +++ b/board-nanonote.h Sun Jun 07 18:21:24 2015 +0200 @@ -5,17 +5,7 @@ void load_args(void); void gpio_init(void); -void gpio_init2(void); -void cpm_init(void); void pll_init(void); void sdram_init(void); -void rtc_init(void); -int timer_init(void); - -/* Utility functions. */ - -void udelay(unsigned long usec); -void flush_cache_all(void); -unsigned long get_memory_size(void); #endif /* __BOARD_NANONOTE_H__ */ diff -r 6fe88df66344 -r 9904a4a3b363 board-nanonote2.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/board-nanonote2.c Sun Jun 07 18:21:24 2015 +0200 @@ -0,0 +1,334 @@ +/* + * Ben NanoNote board late initialisation, based on uboot-xburst and xburst-tools. + * + * Copyright (C) 2015 Paul Boddie + * Copyright (C) Xiangfu Liu + * Copyright (C) 2006 Ingenic Semiconductor, + * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License as published by the Free Software + * Foundation; either version 3 of the License, or (at your option) any later + * version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "jz4740.h" +#include "configs.h" +#include "nanonote.h" + +/* Later initialisation functions. */ + +void gpio_init2(void) +{ + /* + * Initialize LCD pins + */ + __gpio_as_slcd_8bit(); + + /* + * Initialize MSC pins + */ + __gpio_as_msc(); + + /* + * Initialize Other pins + */ + unsigned int i; + for (i = 0; i < 7; i++){ + __gpio_as_input(GPIO_KEYIN_BASE + i); + __gpio_enable_pull(GPIO_KEYIN_BASE + i); + } + + for (i = 0; i < 8; i++) { + __gpio_as_output(GPIO_KEYOUT_BASE + i); + __gpio_clear_pin(GPIO_KEYOUT_BASE + i); + } + + /* enable the TP4, TP5 as UART0 */ + __gpio_jtag_to_uart0(); + + __gpio_as_input(GPIO_KEYIN_8); + __gpio_enable_pull(GPIO_KEYIN_8); + + __gpio_as_output(GPIO_AUDIO_POP); + __gpio_set_pin(GPIO_AUDIO_POP); + + __gpio_as_output(GPIO_LCD_CS); + __gpio_clear_pin(GPIO_LCD_CS); + + __gpio_as_output(GPIO_AMP_EN); + __gpio_clear_pin(GPIO_AMP_EN); + + __gpio_as_output(GPIO_SDPW_EN); + __gpio_disable_pull(GPIO_SDPW_EN); + __gpio_clear_pin(GPIO_SDPW_EN); + + __gpio_as_input(GPIO_SD_DETECT); + __gpio_disable_pull(GPIO_SD_DETECT); + + __gpio_as_input(GPIO_USB_DETECT); + __gpio_enable_pull(GPIO_USB_DETECT); +} + +void cpm_init(void) +{ + __cpm_stop_ipu(); + __cpm_stop_cim(); + __cpm_stop_i2c(); + __cpm_stop_ssi(); + __cpm_stop_uart1(); + __cpm_stop_sadc(); + __cpm_stop_uhc(); + __cpm_stop_udc(); + __cpm_stop_aic1(); +/* __cpm_stop_aic2();*/ +} + +void rtc_init(void) +{ + while ( !__rtc_write_ready()); + __rtc_enable_alarm(); /* enable alarm */ + + while ( !__rtc_write_ready()); + REG_RTC_RGR = 0x00007fff; /* type value */ + + while ( !__rtc_write_ready()); + REG_RTC_HWFCR = 0x0000ffe0; /* Power on delay 2s */ + + while ( !__rtc_write_ready()); + REG_RTC_HRCR = 0x00000fe0; /* reset delay 125ms */ +} + +unsigned long get_memory_size(void) +{ + unsigned int dmcr; + unsigned int rows, cols, dw, banks; + unsigned long size; + + dmcr = REG_EMC_DMCR; + rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT); + cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT); + dw = (dmcr & EMC_DMCR_BW) ? 2 : 4; + banks = (dmcr & EMC_DMCR_BA) ? 4 : 2; + + size = (1 << (rows + cols)) * dw * banks; + + return size; +} + +/* Timer routines. */ + +#define TIMER_CHAN 0 +#define TIMER_FDATA 0xffff /* Timer full data value */ +#define TIMER_HZ CONFIG_SYS_HZ + +#define READ_TIMER REG_TCU_TCNT(TIMER_CHAN) /* macro to read the 16 bit timer */ + +static unsigned long timestamp; +static unsigned long lastdec; + +void reset_timer_masked(void); +unsigned long get_timer_masked(void); +void udelay_masked(unsigned long usec); + +/* + * timer without interrupts + */ + +int timer_init(void) +{ + REG_TCU_TCSR(TIMER_CHAN) = TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN; + REG_TCU_TCNT(TIMER_CHAN) = 0; + REG_TCU_TDHR(TIMER_CHAN) = 0; + REG_TCU_TDFR(TIMER_CHAN) = TIMER_FDATA; + + REG_TCU_TMSR = (1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)); /* mask irqs */ + REG_TCU_TSCR = (1 << TIMER_CHAN); /* enable timer clock */ + REG_TCU_TESR = (1 << TIMER_CHAN); /* start counting up */ + + lastdec = 0; + timestamp = 0; + + return 0; +} + +void reset_timer(void) +{ + reset_timer_masked (); +} + +unsigned long get_timer(unsigned long base) +{ + return get_timer_masked () - base; +} + +void set_timer(unsigned long t) +{ + timestamp = t; +} + +void udelay (unsigned long usec) +{ + unsigned long tmo,tmp; + + /* normalize */ + if (usec >= 1000) { + tmo = usec / 1000; + tmo *= TIMER_HZ; + tmo /= 1000; + } + else { + if (usec >= 1) { + tmo = usec * TIMER_HZ; + tmo /= (1000*1000); + } + else + tmo = 1; + } + + /* check for rollover during this delay */ + tmp = get_timer (0); + if ((tmp + tmo) < tmp ) + reset_timer_masked(); /* timer would roll over */ + else + tmo += tmp; + + while (get_timer_masked () < tmo); +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = READ_TIMER; + timestamp = 0; +} + +unsigned long get_timer_masked (void) +{ + unsigned long now = READ_TIMER; + + if (lastdec <= now) { + /* normal mode */ + timestamp += (now - lastdec); + } else { + /* we have an overflow ... */ + timestamp += TIMER_FDATA + now - lastdec; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked (unsigned long usec) +{ + unsigned long tmo; + unsigned long endtime; + signed long diff; + + /* normalize */ + if (usec >= 1000) { + tmo = usec / 1000; + tmo *= TIMER_HZ; + tmo /= 1000; + } else { + if (usec > 1) { + tmo = usec * TIMER_HZ; + tmo /= (1000*1000); + } else { + tmo = 1; + } + } + + endtime = get_timer_masked () + tmo; + + do { + unsigned long now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On MIPS it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On MIPS it returns the number of timer ticks per second. + */ +unsigned long get_tbclk (void) +{ + return TIMER_HZ; +} + +/* CPU-specific routines from U-Boot. + See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c + See: u-boot/arch/mips/include/asm/cacheops.h +*/ + +#define Index_Store_Tag_I 0x08 +#define Index_Writeback_Inv_D 0x15 + +void flush_icache_all(void) +{ + u32 addr, t = 0; + + asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ + asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ + + for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; + addr += CONFIG_SYS_CACHELINE_SIZE) { + asm volatile ( + ".set mips3\n\t" + " cache %0, 0(%1)\n\t" + ".set mips2\n\t" + : + : "I" (Index_Store_Tag_I), "r"(addr)); + } + + /* invalicate btb */ + asm volatile ( + ".set mips32\n\t" + "mfc0 %0, $16, 7\n\t" + "nop\n\t" + "ori %0,2\n\t" + "mtc0 %0, $16, 7\n\t" + ".set mips2\n\t" + : + : "r" (t)); +} + +void flush_dcache_all(void) +{ + u32 addr; + + for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; + addr += CONFIG_SYS_CACHELINE_SIZE) { + asm volatile ( + ".set mips3\n\t" + " cache %0, 0(%1)\n\t" + ".set mips2\n\t" + : + : "I" (Index_Writeback_Inv_D), "r"(addr)); + } + + asm volatile ("sync"); +} + +void flush_cache_all(void) +{ + flush_dcache_all(); + flush_icache_all(); +} diff -r 6fe88df66344 -r 9904a4a3b363 board-nanonote2.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/board-nanonote2.h Sun Jun 07 18:21:24 2015 +0200 @@ -0,0 +1,17 @@ +#ifndef __BOARD_NANONOTE2_H__ +#define __BOARD_NANONOTE2_H__ + +/* Initialisation functions. */ + +void gpio_init2(void); +void cpm_init(void); +void rtc_init(void); +int timer_init(void); + +/* Utility functions. */ + +void udelay(unsigned long usec); +void flush_cache_all(void); +unsigned long get_memory_size(void); + +#endif /* __BOARD_NANONOTE2_H__ */ diff -r 6fe88df66344 -r 9904a4a3b363 head1.S --- a/head1.S Sun Jun 07 02:20:54 2015 +0200 +++ b/head1.S Sun Jun 07 18:21:24 2015 +0200 @@ -1,12 +1,12 @@ /* - * head.S - * * Entry point of the firmware. - * The firmware code are executed in the ICache. + * The firmware code is executed in the ICache. * * Copyright 2009 (C) Qi Hardware Inc., * Author: Xiangfu Liu * + * Copyright (C) 2015 Paul Boddie + * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * version 3 as published by the Free Software Foundation. @@ -39,8 +39,7 @@ .word 0x0 .word 0x0 .word 0x0 - /* reserve 8 words for args - * this is must big then sizeof(sturct fw_args) + /* reserve 8 words for args sizeof(struct fw_args) */ real_start: /* diff -r 6fe88df66344 -r 9904a4a3b363 head2.S --- a/head2.S Sun Jun 07 02:20:54 2015 +0200 +++ b/head2.S Sun Jun 07 18:21:24 2015 +0200 @@ -1,6 +1,4 @@ /* - * head.S - * * Entry point of the firmware. * The firmware code are executed in the ICache. * Do not edit! @@ -28,7 +26,7 @@ real_start: /* setup stack, jump to C code */ add $29, $20, 0x3ffff0 // sp locate at start address offset 0x2ffff0 - add $25, $20, 0x40 // t9 = usb_main() + add $25, $20, 0x40 // t9 = c_main() j $25 nop diff -r 6fe88df66344 -r 9904a4a3b363 lcd.c --- a/lcd.c Sun Jun 07 02:20:54 2015 +0200 +++ b/lcd.c Sun Jun 07 18:21:24 2015 +0200 @@ -20,7 +20,7 @@ #include "xburst_types.h" #include "nanonote_gpm940b0.h" -#include "board-nanonote.h" +#include "board-nanonote2.h" #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) diff -r 6fe88df66344 -r 9904a4a3b363 nanonote_gpm940b0.c --- a/nanonote_gpm940b0.c Sun Jun 07 02:20:54 2015 +0200 +++ b/nanonote_gpm940b0.c Sun Jun 07 18:21:24 2015 +0200 @@ -26,7 +26,7 @@ #include "jz4740.h" #include "nanonote_gpm940b0.h" -#include "board-nanonote.h" +#include "board-nanonote2.h" #define align2(n) (n)=((((n)+1)>>1)<<1) #define align4(n) (n)=((((n)+3)>>2)<<2) diff -r 6fe88df66344 -r 9904a4a3b363 stage2.c --- a/stage2.c Sun Jun 07 02:20:54 2015 +0200 +++ b/stage2.c Sun Jun 07 18:21:24 2015 +0200 @@ -18,12 +18,11 @@ * this program. If not, see . */ -#include "board-nanonote.h" +#include "board-nanonote2.h" #include "lcd.h" void c_main(void) { - load_args(); gpio_init2(); cpm_init(); rtc_init();