# HG changeset patch # User Paul Boddie # Date 1498771599 -7200 # Node ID a6159a6780029090d8f30703b8510c772b963980 # Parent d38448b333a8793ae6694e86de63dfeb8462131d Introduced separate abstractions for GPIO keymap details and moved initialisation into the keyscan task. Disabled the power button GPIO interrupt for now. diff -r d38448b333a8 -r a6159a678002 include/minipc.h --- a/include/minipc.h Wed Jun 28 16:31:54 2017 +0200 +++ b/include/minipc.h Thu Jun 29 23:26:39 2017 +0200 @@ -3,7 +3,7 @@ * * Copyright (C) 2009 Qi Hardware Inc. * Authors: Xiangfu Liu - * Copyright (C) 2015, 2016 Paul Boddie + * Copyright (C) 2015, 2016, 2017 Paul Boddie * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -30,8 +30,6 @@ #define GPIO_PWM0 94 #define GPIO_POWER 97 -#define GPIO_KEYIN_BASE 0 /* if jz_keypad.c is understood correctly */ -#define GPIO_KEYOUT_BASE (3 * 32 + 0) #define GPIO_KEYIN_COUNT 8 #define GPIO_KEYOUT_COUNT 17 diff -r d38448b333a8 -r a6159a678002 include/nanonote.h --- a/include/nanonote.h Wed Jun 28 16:31:54 2017 +0200 +++ b/include/nanonote.h Thu Jun 29 23:26:39 2017 +0200 @@ -3,7 +3,7 @@ * * Copyright (C) 2009 Qi Hardware Inc. * Authors: Xiangfu Liu - * Copyright (C) 2015, 2016 Paul Boddie + * Copyright (C) 2015, 2016, 2017 Paul Boddie * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -38,11 +38,7 @@ #define GPIO_AUDIO_POP (1 * 32 + 29) #define GPIO_COB_TEST (1 * 32 + 30) -#define GPIO_KEYOUT_BASE (2 * 32 + 10) -#define GPIO_KEYIN_BASE (3 * 32 + 18) -#define GPIO_KEYIN_8 (3 * 32 + 26) - -#define GPIO_KEYIN_COUNT 7 +#define GPIO_KEYIN_COUNT 8 #define GPIO_KEYOUT_COUNT 8 #define GPIO_POWER (3 * 32 + 29) diff -r d38448b333a8 -r a6159a678002 stage2/Makefile --- a/stage2/Makefile Wed Jun 28 16:31:54 2017 +0200 +++ b/stage2/Makefile Thu Jun 29 23:26:39 2017 +0200 @@ -43,9 +43,9 @@ # Configure target-specific objects. -NANONOTE_SRC = board-nanonote.c nanonote_gpm940b0.c +NANONOTE_SRC = board-nanonote.c nanonote_gpm940b0.c nanonote_gpio.c NANONOTE_OBJ = $(NANONOTE_SRC:.c=.o) -MINIPC_SRC = board-minipc.c minipc_claa070vc01.c +MINIPC_SRC = board-minipc.c minipc_claa070vc01.c minipc_gpio.c MINIPC_OBJ = $(MINIPC_SRC:.c=.o) ifdef MINIPC diff -r d38448b333a8 -r a6159a678002 stage2/board-nanonote.c --- a/stage2/board-nanonote.c Wed Jun 28 16:31:54 2017 +0200 +++ b/stage2/board-nanonote.c Thu Jun 29 23:26:39 2017 +0200 @@ -37,25 +37,10 @@ /* Initialise other pins. */ - unsigned int i; - - for (i = 0; i < GPIO_KEYIN_COUNT; i++){ - __gpio_as_input(GPIO_KEYIN_BASE + i); - __gpio_enable_pull(GPIO_KEYIN_BASE + i); - } - - for (i = 0; i < GPIO_KEYOUT_COUNT; i++) { - __gpio_as_output(GPIO_KEYOUT_BASE + i); - __gpio_clear_pin(GPIO_KEYOUT_BASE + i); - } - /* Enable TP4, TP5 as UART0. */ __gpio_jtag_to_uart0(); - __gpio_as_input(GPIO_KEYIN_8); - __gpio_enable_pull(GPIO_KEYIN_8); - __gpio_as_input(GPIO_POWER); __gpio_enable_pull(GPIO_POWER); diff -r d38448b333a8 -r a6159a678002 stage2/board.h --- a/stage2/board.h Wed Jun 28 16:31:54 2017 +0200 +++ b/stage2/board.h Thu Jun 29 23:26:39 2017 +0200 @@ -40,10 +40,12 @@ #ifdef CONFIG_CPU_JZ4730_MINIPC #include "minipc.h" +#include "minipc_gpio.h" #else /* assume NanoNote */ #include "nanonote.h" +#include "nanonote_gpio.h" #endif /* CONFIG_CPU_JZ4730_MINIPC */ diff -r d38448b333a8 -r a6159a678002 stage2/irq.c --- a/stage2/irq.c Wed Jun 28 16:31:54 2017 +0200 +++ b/stage2/irq.c Thu Jun 29 23:26:39 2017 +0200 @@ -32,7 +32,7 @@ { handle_error_level(); timer_init_irq(); - gpio_init_irq(); + /* gpio_init_irq(); */ init_interrupts(); } diff -r d38448b333a8 -r a6159a678002 stage2/minipc_gpio.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage2/minipc_gpio.c Thu Jun 29 23:26:39 2017 +0200 @@ -0,0 +1,37 @@ +/* + * MiniPC GPIO details. + * + * Copyright (C) 2017 Paul Boddie + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, + * Boston, MA 02110-1301, USA + */ + +#include "minipc.h" +#include + +#define PIN(x) (3 * 32 + x) + +const uint8_t GPIO_KEYIN_ROW[GPIO_KEYIN_COUNT] = { + 0, 1, 2, 3, 4, 5, 6, 7 /* if jz_keypad.c is understood correctly */ + }; + +const uint8_t GPIO_KEYOUT_COL[GPIO_KEYOUT_COUNT] = { + PIN(0), PIN(1), PIN(2), PIN(3), PIN(4), PIN(5), PIN(6), PIN(7), + PIN(8), PIN(9), PIN(10), PIN(11), PIN(12), PIN(13), PIN(14), PIN(15), + PIN(16) + }; + +#undef PIN diff -r d38448b333a8 -r a6159a678002 stage2/minipc_gpio.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage2/minipc_gpio.h Thu Jun 29 23:26:39 2017 +0200 @@ -0,0 +1,34 @@ +/* + * MiniPC GPIO declarations. + * + * Copyright (C) 2017 Paul Boddie + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __MINIPC_GPIO_H__ +#define __MINIPC_GPIO_H__ + +#include "minipc.h" + +#ifndef __ASSEMBLER__ + +#include + +extern const uint8_t GPIO_KEYIN_ROW[GPIO_KEYIN_COUNT]; +extern const uint8_t GPIO_KEYOUT_COL[GPIO_KEYOUT_COUNT]; + +#endif /* __ASSEMBLER__ */ + +#endif /* __MINIPC_GPIO_H__ */ diff -r d38448b333a8 -r a6159a678002 stage2/nanonote_gpio.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage2/nanonote_gpio.c Thu Jun 29 23:26:39 2017 +0200 @@ -0,0 +1,38 @@ +/* + * Ben NanoNote GPIO details. + * + * Copyright (C) 2017 Paul Boddie + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, + * Boston, MA 02110-1301, USA + */ + +#include "nanonote.h" +#include + +#define PIN(x) (3 * 32 + 18 + x) + +const uint8_t GPIO_KEYIN_ROW[GPIO_KEYIN_COUNT] = { + 0, 1, 2, 3, 4, 5, 6, 7 + }; + +#undef PIN +#define PIN(x) (2 * 32 + 10 + x) + +const uint8_t GPIO_KEYOUT_COL[GPIO_KEYOUT_COUNT] = { + PIN(0), PIN(1), PIN(2), PIN(3), PIN(4), PIN(5), PIN(6), PIN(8), + }; + +#undef PIN diff -r d38448b333a8 -r a6159a678002 stage2/nanonote_gpio.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/stage2/nanonote_gpio.h Thu Jun 29 23:26:39 2017 +0200 @@ -0,0 +1,34 @@ +/* + * Ben NanoNote GPIO declarations. + * + * Copyright (C) 2017 Paul Boddie + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __NANONOTE_GPIO_H__ +#define __NANONOTE_GPIO_H__ + +#include "nanonote.h" + +#ifndef __ASSEMBLER__ + +#include + +extern const uint8_t GPIO_KEYIN_ROW[GPIO_KEYIN_COUNT]; +extern const uint8_t GPIO_KEYOUT_COL[GPIO_KEYOUT_COUNT]; + +#endif /* __ASSEMBLER__ */ + +#endif /* __NANONOTE_GPIO_H__ */ diff -r d38448b333a8 -r a6159a678002 stage2/task_gpio.c --- a/stage2/task_gpio.c Wed Jun 28 16:31:54 2017 +0200 +++ b/stage2/task_gpio.c Thu Jun 29 23:26:39 2017 +0200 @@ -41,14 +41,33 @@ void task_gpio_as_input(uint8_t pin) { + TASK_REG_GPIO_PXFUNC(pin / 32) = (1 << (pin % 32)); + TASK_REG_GPIO_PXSELC(pin / 32) = (1 << (pin % 32)); TASK_REG_GPIO_PXDIRC(pin / 32) = (1 << (pin % 32)); } void task_gpio_as_output(uint8_t pin) { + TASK_REG_GPIO_PXFUNC(pin / 32) = (1 << (pin % 32)); + TASK_REG_GPIO_PXSELC(pin / 32) = (1 << (pin % 32)); TASK_REG_GPIO_PXDIRS(pin / 32) = (1 << (pin % 32)); } +void task_gpio_enable_pull(uint8_t pin) +{ + TASK_REG_GPIO_PXPEC(pin / 32) = (1 << (pin % 32)); +} + +void task_gpio_disable_pull(uint8_t pin) +{ + TASK_REG_GPIO_PXPES(pin / 32) = (1 << (pin % 32)); +} + +inline int task_gpio_get_pin(uint8_t pin) +{ + return TASK_REG_GPIO_PXPIN(pin / 32) & (1 << (pin % 32)); +} + inline void task_gpio_set_pin(uint8_t pin) { TASK_REG_GPIO_PXDATS(pin / 32) = (1 << (pin % 32)); @@ -59,7 +78,12 @@ TASK_REG_GPIO_PXDATC(pin / 32) = (1 << (pin % 32)); } -inline int task_gpio_get_pin(uint8_t pin) +inline void task_gpio_mask_irq(uint8_t pin) { - return TASK_REG_GPIO_PXPIN(pin / 32) & (1 << (pin % 32)); + TASK_REG_GPIO_PXIMS(pin / 32) = (1 << (pin % 32)); } + +inline void task_gpio_unmask_irq(uint8_t pin) +{ + TASK_REG_GPIO_PXIMC(pin / 32) = (1 << (pin % 32)); +} diff -r d38448b333a8 -r a6159a678002 stage2/task_gpio.h --- a/stage2/task_gpio.h Wed Jun 28 16:31:54 2017 +0200 +++ b/stage2/task_gpio.h Thu Jun 29 23:26:39 2017 +0200 @@ -9,19 +9,53 @@ #define GPIO_BASE_PHYSICAL (GPIO_BASE - KSEG1_BASE) #define TASK_GPIO_PXPIN(n) (TASK_GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */ + #define TASK_GPIO_PXDAT(n) (TASK_GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */ #define TASK_GPIO_PXDATS(n) (TASK_GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */ #define TASK_GPIO_PXDATC(n) (TASK_GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */ +#define TASK_GPIO_PXIM(n) (TASK_GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */ +#define TASK_GPIO_PXIMS(n) (TASK_GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */ +#define TASK_GPIO_PXIMC(n) (TASK_GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */ + +#define TASK_GPIO_PXPE(n) (TASK_GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */ +#define TASK_GPIO_PXPES(n) (TASK_GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */ +#define TASK_GPIO_PXPEC(n) (TASK_GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */ + +#define TASK_GPIO_PXFUN(n) (TASK_GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */ +#define TASK_GPIO_PXFUNS(n) (TASK_GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */ +#define TASK_GPIO_PXFUNC(n) (TASK_GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */ + +#define TASK_GPIO_PXSEL(n) (TASK_GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */ +#define TASK_GPIO_PXSELS(n) (TASK_GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */ +#define TASK_GPIO_PXSELC(n) (TASK_GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */ + #define TASK_GPIO_PXDIR(n) (TASK_GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */ #define TASK_GPIO_PXDIRS(n) (TASK_GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */ #define TASK_GPIO_PXDIRC(n) (TASK_GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */ #define TASK_REG_GPIO_PXPIN(n) REG32(TASK_GPIO_PXPIN((n))) + #define TASK_REG_GPIO_PXDAT(n) REG32(TASK_GPIO_PXDAT((n))) #define TASK_REG_GPIO_PXDATS(n) REG32(TASK_GPIO_PXDATS((n))) #define TASK_REG_GPIO_PXDATC(n) REG32(TASK_GPIO_PXDATC((n))) +#define TASK_REG_GPIO_PXIM(n) REG32(TASK_GPIO_PXIM((n))) +#define TASK_REG_GPIO_PXIMS(n) REG32(TASK_GPIO_PXIMS((n))) +#define TASK_REG_GPIO_PXIMC(n) REG32(TASK_GPIO_PXIMC((n))) + +#define TASK_REG_GPIO_PXPE(n) REG32(TASK_GPIO_PXPE((n))) +#define TASK_REG_GPIO_PXPES(n) REG32(TASK_GPIO_PXPES((n))) +#define TASK_REG_GPIO_PXPEC(n) REG32(TASK_GPIO_PXPEC((n))) + +#define TASK_REG_GPIO_PXFUN(n) REG32(TASK_GPIO_PXFUN((n))) +#define TASK_REG_GPIO_PXFUNS(n) REG32(TASK_GPIO_PXFUNS((n))) +#define TASK_REG_GPIO_PXFUNC(n) REG32(TASK_GPIO_PXFUNC((n))) + +#define TASK_REG_GPIO_PXSEL(n) REG32(TASK_GPIO_PXSEL((n))) +#define TASK_REG_GPIO_PXSELS(n) REG32(TASK_GPIO_PXSELS((n))) +#define TASK_REG_GPIO_PXSELC(n) REG32(TASK_GPIO_PXSELC((n))) + #define TASK_REG_GPIO_PXDIR(n) REG32(TASK_GPIO_PXDIR((n))) #define TASK_REG_GPIO_PXDIRS(n) REG32(TASK_GPIO_PXDIRS((n))) #define TASK_REG_GPIO_PXDIRC(n) REG32(TASK_GPIO_PXDIRC((n))) @@ -29,8 +63,15 @@ void task_gpio_init(uint8_t task); void task_gpio_as_input(uint8_t pin); void task_gpio_as_output(uint8_t pin); + +void task_gpio_enable_pull(uint8_t pin); +void task_gpio_disable_pull(uint8_t pin); + +int task_gpio_get_pin(uint8_t pin); void task_gpio_set_pin(uint8_t pin); void task_gpio_clear_pin(uint8_t pin); -int task_gpio_get_pin(uint8_t pin); + +void task_gpio_mask_irq(uint8_t pin); +void task_gpio_unmask_irq(uint8_t pin); #endif /* __TASK_GPIO_H__ */ diff -r d38448b333a8 -r a6159a678002 stage2/tasks/keyscan.c --- a/stage2/tasks/keyscan.c Wed Jun 28 16:31:54 2017 +0200 +++ b/stage2/tasks/keyscan.c Thu Jun 29 23:26:39 2017 +0200 @@ -43,20 +43,27 @@ void init_keyscan() { - int column; + uint8_t pin; - for (column = 0; column < GPIO_KEYOUT_COUNT; column++) + for (pin = 0; pin < GPIO_KEYIN_COUNT; pin++) { - task_gpio_set_pin(GPIO_KEYOUT_BASE + column); + task_gpio_as_input(GPIO_KEYIN_ROW[pin]); + task_gpio_enable_pull(GPIO_KEYIN_ROW[pin]); } + + for (pin = 0; pin < GPIO_KEYOUT_COUNT; pin++) + { + task_gpio_as_input(GPIO_KEYOUT_COL[pin]); + } + + task_gpio_as_input(GPIO_POWER); } /* Tasks. */ void keyscan(uint8_t task) { - int column, row; - uint8_t value; + uint8_t column, row, value; init_keyscan(); @@ -66,21 +73,26 @@ for (column = 0; column < GPIO_KEYOUT_COUNT; column++) { - task_gpio_clear_pin(GPIO_KEYOUT_BASE + column); + task_gpio_as_output(GPIO_KEYOUT_COL[column]); + + for (unsigned int delay = 0; delay < 1000; delay++) + task_gpio_clear_pin(GPIO_KEYOUT_COL[column]); value = 0; for (row = 0; row < GPIO_KEYIN_COUNT; row++) { - value = (value << 1) | !task_gpio_get_pin(GPIO_KEYIN_BASE + row); + value = (value << 1) | (task_gpio_get_pin(GPIO_KEYIN_ROW[row]) ? 0 : 1); } /* Perform an operation indicating the status. */ plot_value(column * 10, column * 10 + 10, 0, 10 * GPIO_KEYIN_COUNT, value); - task_gpio_set_pin(GPIO_KEYOUT_BASE + column); + task_gpio_as_input(GPIO_KEYOUT_COL[column]); } + + plot_value(100, 110, 0, 80, task_gpio_get_pin(GPIO_POWER) ? 0xff : 0); } }