# HG changeset patch # User Paul Boddie # Date 1434144791 -7200 # Node ID aeaf45d52b69aad5620fa6896ed14f60bfec198d # Parent 5a8cf6cc82df6dff3f97c6712bcc4f37db18aaa5 Updated jz4730 MiniPC details; reformatted various definitions. diff -r 5a8cf6cc82df -r aeaf45d52b69 include/jz4730.h --- a/include/jz4730.h Fri Jun 12 18:02:08 2015 +0200 +++ b/include/jz4730.h Fri Jun 12 23:33:11 2015 +0200 @@ -29,9 +29,9 @@ /* NOTE: Independent of usbboot parameters. */ -#define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */ -#define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */ -#define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */ +#define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */ +#define CONFIG_SYS_EXTAL 3686400 /* EXTAL freq: 3.7 MHz */ +#define CONFIG_SYS_HZ (CONFIG_SYS_CPU_SPEED / (3*256)) /* incrementer freq */ #define HARB_BASE 0xB3000000 #define EMC_BASE 0xB3010000 diff -r 5a8cf6cc82df -r aeaf45d52b69 include/jz4740.h --- a/include/jz4740.h Fri Jun 12 18:02:08 2015 +0200 +++ b/include/jz4740.h Fri Jun 12 23:33:11 2015 +0200 @@ -28,9 +28,9 @@ /* NOTE: Independent of usbboot parameters. */ -#define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */ -#define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */ -#define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */ +#define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */ +#define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */ +#define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */ /* Boot ROM Specification */ /* NOR Boot config */ diff -r 5a8cf6cc82df -r aeaf45d52b69 include/sdram.h --- a/include/sdram.h Fri Jun 12 18:02:08 2015 +0200 +++ b/include/sdram.h Fri Jun 12 23:33:11 2015 +0200 @@ -37,16 +37,26 @@ /* * SDRAM configuration (timings in ns) */ -#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */ -#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ -#define SDRAM_ROW 13 /* Row address: 11 to 13 */ -#define SDRAM_COL 9 /* Column address: 8 to 12 */ -#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */ -#define SDRAM_TRAS 45 /* RAS# Active Time */ -#define SDRAM_RCD 20 /* RAS# to CAS# Delay */ -#define SDRAM_TPC 20 /* RAS# Precharge Time */ -#define SDRAM_TRWL 7 /* Write Latency Time */ -#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */ +#ifdef CONFIG_CPU_JZ4730_MINIPC +#define SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */ +#else +#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */ +#endif + +#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */ +#define SDRAM_ROW 13 /* Row address: 11 to 13 */ +#define SDRAM_COL 9 /* Column address: 8 to 12 */ +#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */ +#define SDRAM_TRAS 45 /* RAS# Active Time */ +#define SDRAM_RCD 20 /* RAS# to CAS# Delay */ +#define SDRAM_TPC 20 /* RAS# Precharge Time */ +#define SDRAM_TRWL 7 /* Write Latency Time */ + +#ifdef CONFIG_CPU_JZ4730_MINIPC +#define SDRAM_TREF 7812 /* Refresh period: 8192 cycles/64ms */ +#else +#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */ +#endif #define SDRAM_ROW0 11 /* Row address minimum */ #define SDRAM_COL0 8 /* Column address minimum */