# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1498660314 -7200
# Node ID d38448b333a8793ae6694e86de63dfeb8462131d
# Parent  44fcbb779a70f5dbb565fc8a8fe68836310429b0
Use the physical base address of the GPIO registers.

diff -r 44fcbb779a70 -r d38448b333a8 include/mips.h
--- a/include/mips.h	Wed Jun 28 01:04:22 2017 +0200
+++ b/include/mips.h	Wed Jun 28 16:31:54 2017 +0200
@@ -1,20 +1,29 @@
 #ifndef __MIPS_H__
 #define __MIPS_H__
 
+#define KSEG0_BASE	0x80000000
+#define KSEG1_BASE	0xA0000000
+
 #define CP0_INDEX	$0
 #define CP0_ENTRYLO0	$2
 #define CP0_ENTRYLO1	$3
 #define CP0_CONTEXT	$4
 #define CP0_PAGEMASK	$5
 #define CP0_WIRED	$6
+#define CP0_COUNT	$9
 #define CP0_ENTRYHI	$10
+#define CP0_COMPARE	$11
 #define CP0_STATUS	$12
+#define CP0_INTCTL	$12, 1
 #define CP0_CAUSE	$13
 #define CP0_EPC		$14
+#define CP0_EBASE	$15, 1
 #define CP0_CONFIG	$16
 #define CP0_WATCHLO	$18
+#define CP0_DEBUG	$23
 #define CP0_TAGLO	$28
 #define CP0_TAGHI	$29
+#define CP0_ERROREPC	$30, 0
 
 #define STATUS_CP0	0x10000000
 #define STATUS_BEV	0x00400000
@@ -26,6 +35,12 @@
 
 #define CAUSE_IV	0x00800000
 
+#define EBASE_MASK	0x3ffff000
+
+#define INTCTL_MASK	0x000003e0
+
+#define DEBUG_DM	0x40000000
+
 #define TLB_CACHED	0x00000018
 #define TLB_UNCACHED	0x00000010
 #define TLB_DIRTY	0x00000004
@@ -37,4 +52,8 @@
 #define TLB_ALL_READ	(TLB_CACHED | TLB_VALID | TLB_GLOBAL)
 #define TLB_ALL_WRITE	(TLB_CACHED | TLB_DIRTY | TLB_VALID | TLB_GLOBAL)
 
+#define CONFIG_K0	0x00000007
+#define CONFIG_K0_UNCACHED		2
+#define CONFIG_K0_CACHABLE_NONCOHERENT	3
+
 #endif /* __MIPS_H__ */
diff -r 44fcbb779a70 -r d38448b333a8 stage2/task_gpio.c
--- a/stage2/task_gpio.c	Wed Jun 28 01:04:22 2017 +0200
+++ b/stage2/task_gpio.c	Wed Jun 28 16:31:54 2017 +0200
@@ -30,7 +30,7 @@
 
         /* Map the I/O region to the task. */
 
-	for (virtual = TASK_GPIO_BASE, physical = GPIO_BASE;
+	for (virtual = TASK_GPIO_BASE, physical = GPIO_BASE_PHYSICAL;
 		virtual < (uint32_t) TASK_GPIO_BASE + (uint32_t) GPIO_REGION_SIZE;
 		virtual += page_size(STAGE2_PAGESIZE), physical += page_size(STAGE2_PAGESIZE))
 	{
diff -r 44fcbb779a70 -r d38448b333a8 stage2/task_gpio.h
--- a/stage2/task_gpio.h	Wed Jun 28 01:04:22 2017 +0200
+++ b/stage2/task_gpio.h	Wed Jun 28 16:31:54 2017 +0200
@@ -6,6 +6,8 @@
 
 /* Special task versions of GPIO operations. */
 
+#define GPIO_BASE_PHYSICAL	(GPIO_BASE - KSEG1_BASE)
+
 #define TASK_GPIO_PXPIN(n)	(TASK_GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
 #define TASK_GPIO_PXDAT(n)	(TASK_GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
 #define TASK_GPIO_PXDATS(n)	(TASK_GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */