# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1433784790 -7200
# Node ID da8b0234834a5ca7af8f9036d8fa551b47507c24
# Parent  df198fdec3e219571473c8c8ee26afb67090e5df
Moved various SDRAM definitions and adjusted the initialisation code to show the
presumed intent behind the use of these definitions more clearly.

diff -r df198fdec3e2 -r da8b0234834a include/nanonote.h
--- a/include/nanonote.h	Mon Jun 08 19:20:02 2015 +0200
+++ b/include/nanonote.h	Mon Jun 08 19:33:10 2015 +0200
@@ -53,6 +53,10 @@
 #define SDRAM_TRWL			7       /* Write Latency Time */
 #define SDRAM_TREF			15625   /* Refresh period: 8192 cycles/64ms */
 
+#define SDRAM_ROW0			11	/* Row address minimum */
+#define SDRAM_COL0			8	/* Column address minimum */
+#define SDRAM_BANK40			0	/* Bank minimum */
+
 /*
  * Cache configuration
  */
diff -r df198fdec3e2 -r da8b0234834a stage1/board-nanonote.c
--- a/stage1/board-nanonote.c	Mon Jun 08 19:20:02 2015 +0200
+++ b/stage1/board-nanonote.c	Mon Jun 08 19:33:10 2015 +0200
@@ -132,21 +132,17 @@
 	REG_EMC_RTCSR = 0;	/* Disable clock for counting */
 
 	/* Fault DMCR value for mode register setting*/
-#define SDRAM_ROW0    11
-#define SDRAM_COL0     8
-#define SDRAM_BANK40   0
-
-	dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) |
-		((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) |
-		(SDRAM_BANK40<<EMC_DMCR_BA_BIT) |
+	dmcr0 = (0<<EMC_DMCR_RA_BIT) |
+		(0<<EMC_DMCR_CA_BIT) |
+		(0<<EMC_DMCR_BA_BIT) |
 		(FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) |
 		EMC_DMCR_EPIN |
 		cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
 
 	/* Basic DMCR value */
-	dmcr = ((FW_SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
-		((FW_SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
-		(FW_SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
+	dmcr = ((FW_SDRAM_ROW-SDRAM_ROW0)<<EMC_DMCR_RA_BIT) |
+		((FW_SDRAM_COL-SDRAM_COL0)<<EMC_DMCR_CA_BIT) |
+		((FW_SDRAM_BANK4-SDRAM_BANK40)<<EMC_DMCR_BA_BIT) |
 		(FW_SDRAM_BW16<<EMC_DMCR_BW_BIT) |
 		EMC_DMCR_EPIN |
 		cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];