1.1 --- a/include/mips.h Wed May 04 22:07:41 2016 +0200
1.2 +++ b/include/mips.h Wed May 04 22:57:56 2016 +0200
1.3 @@ -16,4 +16,12 @@
1.4 #define CP0_TAGLO $28
1.5 #define CP0_TAGHI $29
1.6
1.7 +#define STATUS_BEV 0x00400000
1.8 +#define STATUS_IRQ 0xfc00
1.9 +#define STATUS_ERL 4
1.10 +#define STATUS_EXL 2
1.11 +#define STATUS_IE 1
1.12 +
1.13 +#define CAUSE_IV 0x00800000
1.14 +
1.15 #endif /* __MIPS_H__ */
2.1 --- a/stage2/cpu_op.S Wed May 04 22:07:41 2016 +0200
2.2 +++ b/stage2/cpu_op.S Wed May 04 22:57:56 2016 +0200
2.3 @@ -78,7 +78,7 @@
2.4
2.5 handle_error_level:
2.6 mfc0 $t3, CP0_STATUS
2.7 - li $t4, 0xfffffffb /* ERL = 0 */
2.8 + li $t4, ~STATUS_ERL
2.9 and $t3, $t3, $t4
2.10 mtc0 $t3, CP0_STATUS
2.11 jr $ra
2.12 @@ -88,8 +88,7 @@
2.13
2.14 enable_interrupts:
2.15 mfc0 $t3, CP0_STATUS
2.16 - li $t4, 0x0000fc01 /* IE = enable interrupts */
2.17 - or $t3, $t3, $t4
2.18 + ori $t3, $t3, STATUS_IRQ | STATUS_IE
2.19 mtc0 $t3, CP0_STATUS
2.20 jr $ra
2.21 nop
2.22 @@ -101,10 +100,10 @@
2.23 /* Set exception registers. */
2.24
2.25 mtc0 $zero, CP0_WATCHLO
2.26 - li $t3, 0x00800000 /* IV = 1 (use 0x80000200 for interrupts) */
2.27 + li $t3, CAUSE_IV /* IV = 1 (use 0x80000200 for interrupts) */
2.28 mtc0 $t3, CP0_CAUSE
2.29 mfc0 $t4, CP0_STATUS
2.30 - li $t3, 0xffbfffff /* BEV=0 */
2.31 + li $t3, ~STATUS_BEV
2.32 and $t3, $t3, $t4
2.33 mtc0 $t3, CP0_STATUS
2.34 jr $ra
2.35 @@ -128,7 +127,7 @@
2.36 lw $gp, 104($t3)
2.37 mtc0 $t9, CP0_EPC
2.38 mfc0 $t3, CP0_STATUS
2.39 - ori $t3, $t3, 0x2 /* EXL = 1 */
2.40 + ori $t3, $t3, STATUS_EXL
2.41 mtc0 $t3, CP0_STATUS
2.42 eret
2.43 nop