1.1 --- a/stage2/cpu.c Wed May 04 16:59:15 2016 +0200
1.2 +++ b/stage2/cpu.c Wed May 04 17:03:35 2016 +0200
1.3 @@ -250,16 +250,12 @@
1.4 /* Each page table entry corresponds to a pair of 4KB pages and holds two values. */
1.5
1.6 u32 entry = ((virtual & 0xffffe000) >> 13) * 8;
1.7 - u32 address = base + entry;
1.8 + u32 *address = (u32 *) (base + entry);
1.9
1.10 /* The page tables should be permanently mapped to avoid hierarchical TLB miss handling. */
1.11
1.12 - asm volatile(
1.13 - "sw %1, 0(%0)\n"
1.14 - "sw %2, 4(%0)\n"
1.15 - :
1.16 - : "r" (address), "r" (lower), "r" (upper)
1.17 - );
1.18 + *address = lower;
1.19 + *(address + 1) = upper;
1.20 }
1.21
1.22 void map_page(u32 virtual, u32 physical, u32 pagesize, u8 flags, u8 asid)