1.1 --- a/stage2/cpu.c Wed May 04 23:35:03 2016 +0200
1.2 +++ b/stage2/cpu.c Wed May 04 23:59:04 2016 +0200
1.3 @@ -73,9 +73,9 @@
1.4 base[29] = (u32) function - 0x80000000; /* store the function address as EPC (for the handler) */
1.5 }
1.6
1.7 -void init_tlb(void)
1.8 +void init_tlb(u8 first_random)
1.9 {
1.10 - u32 limit = configure_tlb(), i;
1.11 + u32 limit = configure_tlb(first_random), i;
1.12
1.13 /* Reset the mappings. The total number is bits 30..25 of Config1. */
1.14
2.1 --- a/stage2/cpu.h Wed May 04 23:35:03 2016 +0200
2.2 +++ b/stage2/cpu.h Wed May 04 23:59:04 2016 +0200
2.3 @@ -5,7 +5,7 @@
2.4
2.5 void flush_cache_all();
2.6 void init_registers(u32 *, u32, void (*)(), u32[], u8);
2.7 -void init_tlb();
2.8 +void init_tlb(u8);
2.9 void init_page_table(u32, u32, u32, u32, u8, u8);
2.10 void map_page(u32, u32, u32, u8, u8);
2.11 void map_page_index(u32, u32, u32, u8, u8, u32);
3.1 --- a/stage2/cpu_op.S Wed May 04 23:35:03 2016 +0200
3.2 +++ b/stage2/cpu_op.S Wed May 04 23:59:04 2016 +0200
3.3 @@ -136,7 +136,7 @@
3.4
3.5 configure_tlb:
3.6 mtc0 $zero, CP0_CONTEXT
3.7 - mtc0 $zero, CP0_WIRED /* first random entry is zero */
3.8 + mtc0 $a0, CP0_WIRED /* first random entry is defined by the parameter */
3.9 mfc0 $v0, CP0_CONFIG /* return the limit */
3.10 jr $ra
3.11 nop
4.1 --- a/stage2/cpu_op.h Wed May 04 23:35:03 2016 +0200
4.2 +++ b/stage2/cpu_op.h Wed May 04 23:59:04 2016 +0200
4.3 @@ -11,7 +11,7 @@
4.4 void enable_interrupts();
4.5 void init_interrupts();
4.6 void invoke_task(u8, u32 *, u32 *);
4.7 -u32 configure_tlb();
4.8 +u32 configure_tlb(u32);
4.9 void map_page_set_index(u32);
4.10 void map_page_op(u32, u32, u32, u32);
4.11 void map_page_index_op(u32, u32, u32, u32);
5.1 --- a/stage2/stage2.c Wed May 04 23:35:03 2016 +0200
5.2 +++ b/stage2/stage2.c Wed May 04 23:59:04 2016 +0200
5.3 @@ -30,7 +30,7 @@
5.4 {
5.5 volatile int started;
5.6
5.7 - init_tlb();
5.8 + init_tlb(0);
5.9 flush_cache_all();
5.10
5.11 /* The actual work. */