1.1 --- a/stage2/cpu.c Tue Jun 30 16:09:27 2015 +0200
1.2 +++ b/stage2/cpu.c Tue Jun 30 16:10:40 2015 +0200
1.3 @@ -76,13 +76,71 @@
1.4 flush_icache_all();
1.5 }
1.6
1.7 +void handle_error_level(void)
1.8 +{
1.9 + asm volatile(
1.10 + "mfc0 $t3, $12\n" /* CP0_STATUS */
1.11 + "nop\n"
1.12 + "li $t4, 0xfffffffb\n" /* ERL = 0 */
1.13 + "and $t3, $t3, $t4\n"
1.14 + "mtc0 $t3, $12\n"
1.15 + "nop\n");
1.16 +}
1.17 +
1.18 void enable_interrupts(void)
1.19 {
1.20 asm volatile(
1.21 "mfc0 $t3, $12\n" /* CP0_STATUS */
1.22 "nop\n"
1.23 - "li $t4, 0x00000001\n" /* IE = enable interrupts */
1.24 + "li $t4, 0x0000fc01\n" /* IE = enable interrupts */
1.25 "or $t3, $t3, $t4\n"
1.26 "mtc0 $t3, $12\n"
1.27 "nop\n");
1.28 }
1.29 +
1.30 +void init_interrupts(void)
1.31 +{
1.32 + /* Set exception registers. */
1.33 +
1.34 + asm volatile(
1.35 + "mtc0 $zero, $18\n" /* CP0_WATCHLO */
1.36 + "nop\n"
1.37 + "li $t3, 0x00800000\n" /* IV = 1 (use 0x80000200 for interrupts) */
1.38 + "mtc0 $t3, $13\n" /* CP0_CAUSE */
1.39 + "nop\n"
1.40 + "mtc0 $zero, $12\n" /* CP0_STATUS */
1.41 + "nop\n"
1.42 + "mtc0 $zero, $15\n" /* CP0_EBASE (should be zero anyway) */
1.43 + "nop\n");
1.44 +}
1.45 +
1.46 +void init_tlb(void)
1.47 +{
1.48 + asm volatile(
1.49 + "li $t0, 0x001fe000\n" /* 1MB */
1.50 + "mtc0 $t0, $5\n" /* CP0_PAGEMASK */
1.51 + "nop\n"
1.52 + "mtc0 $zero, $6\n" /* CP0_WIRED */
1.53 + "nop\n"
1.54 +
1.55 + /* Set physical address. */
1.56 +
1.57 + "li $t0, 0x00000003\n" /* 0x000000.. global, valid */
1.58 + "mtc0 $t0, $2\n" /* CP0_ENTRYLO0 */
1.59 + "nop\n"
1.60 + "li $t0, 0x00000003\n" /* 0x000000.. global, valid */
1.61 + "mtc0 $zero, $3\n" /* CP0_ENTRYLO1 */
1.62 + "nop\n"
1.63 +
1.64 + /* Set virtual address. */
1.65 +
1.66 + "li $t0, 0x80000000\n" /* 0x80000... */
1.67 + "mtc0 $t0, $10\n" /* CP0_ENTRYHI */
1.68 + "nop\n"
1.69 +
1.70 + /* Set index. */
1.71 +
1.72 + "mtc0 $zero, $0\n" /* CP0_INDEX */
1.73 + "nop\n"
1.74 + "tlbwi\n");
1.75 +}
2.1 --- a/stage2/cpu.h Tue Jun 30 16:09:27 2015 +0200
2.2 +++ b/stage2/cpu.h Tue Jun 30 16:10:40 2015 +0200
2.3 @@ -2,6 +2,9 @@
2.4 #define __CPU_H__
2.5
2.6 void flush_cache_all(void);
2.7 +void handle_error_level(void);
2.8 void enable_interrupts(void);
2.9 +void init_interrupts(void);
2.10 +void init_tlb(void);
2.11
2.12 #endif /* __CPU_H__ */
3.1 --- a/stage2/head2.S Tue Jun 30 16:09:27 2015 +0200
3.2 +++ b/stage2/head2.S Tue Jun 30 16:10:40 2015 +0200
3.3 @@ -20,6 +20,8 @@
3.4 * along with this program. If not, see <http://www.gnu.org/licenses/>.
3.5 */
3.6
3.7 +#include "sdram.h"
3.8 +
3.9 .text
3.10 .extern c_main
3.11 .extern _tlb_entry
3.12 @@ -87,22 +89,10 @@
3.13 bne $t0, $t2, _irq_copy
3.14 addiu $t1, $t1, 4 /* executed in delay slot before branch */
3.15
3.16 - /* Initialise interrupts. */
3.17 + /* Enable caching. */
3.18
3.19 - mfc0 $t3, $12 /* CP0_STATUS */
3.20 - nop
3.21 - li $t4, 0xffbf00e0 /* BEV = 0 (not bootloader vectors); IM = disable all */
3.22 - and $t3, $t3, $t4 /* ... KSU = 0 (kernel mode); ERL = 0; EXL = 0; IE = 0 */
3.23 - li $t4, 0x0000ff04 /* IM = enable IM7..IM0; ERL = 1 (set by default) */
3.24 - or $t3, $t3, $t4
3.25 - mtc0 $t3, $12
3.26 - nop
3.27 -
3.28 - li $t3, 0x00800000 /* IV = 1 (use 0x80000200 for interrupts) */
3.29 - mtc0 $t3, $13 /* CP0_CAUSE */
3.30 - nop
3.31 -
3.32 - mtc0 $zero, $15 /* CP0_EBASE (should be zero anyway) */
3.33 + li $t0, CONFIG_CM_CACHABLE_NONCOHERENT
3.34 + mtc0 $t0, $16 /* CP0_CONFIG */
3.35 nop
3.36
3.37 /* Start the program. */
4.1 --- a/stage2/irq.c Tue Jun 30 16:09:27 2015 +0200
4.2 +++ b/stage2/irq.c Tue Jun 30 16:10:40 2015 +0200
4.3 @@ -59,7 +59,9 @@
4.4 {
4.5 timer_init_irq();
4.6 x = 0; y = 0; pixel_type = 1;
4.7 - enable_interrupts();
4.8 + /* handle_error_level(); */
4.9 + /* enable_interrupts(); */
4.10 + init_interrupts();
4.11 }
4.12
4.13 void irq_handle()
5.1 --- a/stage2/stage2.c Tue Jun 30 16:09:27 2015 +0200
5.2 +++ b/stage2/stage2.c Tue Jun 30 16:10:40 2015 +0200
5.3 @@ -28,6 +28,7 @@
5.4 {
5.5 volatile int started;
5.6
5.7 + init_tlb();
5.8 flush_cache_all();
5.9
5.10 /* The actual work. */