1.1 --- a/stage2/jzlcd.c Sun Jul 09 16:00:26 2017 +0200
1.2 +++ b/stage2/jzlcd.c Sun Jul 09 16:48:29 2017 +0200
1.3 @@ -366,7 +366,7 @@
1.4
1.5 #ifdef CONFIG_CPU_JZ4730
1.6 val = __cpm_get_pllout() / pclk;
1.7 - lcd_ctrl_set(vid, CPM_CFCR2, val - 1);
1.8 + REG_CPM_CFCR2 = val - 1;
1.9 val = pclk * 4 ;
1.10 if ( val > 150000000 ) {
1.11 val = 150000000;
1.12 @@ -378,7 +378,7 @@
1.13 #else
1.14 int pll_div;
1.15
1.16 - pll_div = lcd_ctrl_get(vid, CPM_CPCCR) & lcd_ctrl_get(vid, CPM_CPCCR_PCS); /* clock source,0:pllout/2 1: pllout */
1.17 + pll_div = REG_CPM_CPCCR & CPM_CPCCR_PCS; /* clock source,0:pllout/2 1: pllout */
1.18 pll_div = pll_div ? 1 : 2 ;
1.19 val = ( __cpm_get_pllout()/pll_div ) / pclk;
1.20 val--;
1.21 @@ -398,7 +398,7 @@
1.22 }
1.23 #endif
1.24 __cpm_set_ldiv( val );
1.25 - lcd_ctrl_set(vid, CPM_CPCCR, lcd_ctrl_get(vid, CPM_CPCCR) | CPM_CPCCR_CE); /* update divide */
1.26 + REG_CPM_CPCCR = REG_CPM_CPCCR | CPM_CPCCR_CE; /* update divide */
1.27 }
1.28
1.29 /* Initialise the LCD controller with the memory, panel and framebuffer details.