1.1 --- a/include/jz4730.h Sun Jul 09 19:04:49 2017 +0200
1.2 +++ b/include/jz4730.h Tue Jul 11 00:03:30 2017 +0200
1.3 @@ -33,6 +33,10 @@
1.4 #define CONFIG_SYS_EXTAL 3686400 /* EXTAL freq: 3.7 MHz */
1.5 #define CONFIG_SYS_HZ (CONFIG_SYS_CPU_SPEED / (3*256)) /* incrementer freq */
1.6
1.7 +#define JZ_EXTAL CONFIG_SYS_EXTAL
1.8 +#define JZ_EXTAL2 32768 /* RTC clock */
1.9 +
1.10 +/* Register Definitions */
1.11 #define HARB_BASE 0xB3000000
1.12 #define EMC_BASE 0xB3010000
1.13 #define DMAC_BASE 0xB3020000
1.14 @@ -2198,41 +2202,8 @@
1.15 /*************************************************************************
1.16 * CPM
1.17 *************************************************************************/
1.18 -#define CPM_CFCR (CPM_BASE+0x00)
1.19 -#define CPM_PLCR1 (CPM_BASE+0x10)
1.20 -#define CPM_OCR (CPM_BASE+0x1c)
1.21 -#define CPM_CFCR2 (CPM_BASE+0x60)
1.22 -#define CPM_LPCR (CPM_BASE+0x04)
1.23 -#define CPM_RSTR (CPM_BASE+0x08)
1.24 -#define CPM_MSCR (CPM_BASE+0x20)
1.25 -#define CPM_SCR (CPM_BASE+0x24)
1.26 -#define CPM_WRER (CPM_BASE+0x28)
1.27 -#define CPM_WFER (CPM_BASE+0x2c)
1.28 -#define CPM_WER (CPM_BASE+0x30)
1.29 -#define CPM_WSR (CPM_BASE+0x34)
1.30 -#define CPM_GSR0 (CPM_BASE+0x38)
1.31 -#define CPM_GSR1 (CPM_BASE+0x3c)
1.32 -#define CPM_GSR2 (CPM_BASE+0x40)
1.33 -#define CPM_SPR (CPM_BASE+0x44)
1.34 -#define CPM_GSR3 (CPM_BASE+0x48)
1.35 -
1.36 -#define REG_CPM_CFCR REG32(CPM_CFCR)
1.37 -#define REG_CPM_PLCR1 REG32(CPM_PLCR1)
1.38 -#define REG_CPM_OCR REG32(CPM_OCR)
1.39 -#define REG_CPM_CFCR2 REG32(CPM_CFCR2)
1.40 -#define REG_CPM_LPCR REG32(CPM_LPCR)
1.41 -#define REG_CPM_RSTR REG32(CPM_RSTR)
1.42 -#define REG_CPM_MSCR REG32(CPM_MSCR)
1.43 -#define REG_CPM_SCR REG32(CPM_SCR)
1.44 -#define REG_CPM_WRER REG32(CPM_WRER)
1.45 -#define REG_CPM_WFER REG32(CPM_WFER)
1.46 -#define REG_CPM_WER REG32(CPM_WER)
1.47 -#define REG_CPM_WSR REG32(CPM_WSR)
1.48 -#define REG_CPM_GSR0 REG32(CPM_GSR0)
1.49 -#define REG_CPM_GSR1 REG32(CPM_GSR1)
1.50 -#define REG_CPM_GSR2 REG32(CPM_GSR2)
1.51 -#define REG_CPM_SPR REG32(CPM_SPR)
1.52 -#define REG_CPM_GSR3 REG32(CPM_GSR3)
1.53 +
1.54 +/* Register definitions with absolute positioning have been removed. */
1.55
1.56 #define CPM_CFCR_SSI (1 << 31)
1.57 #define CPM_CFCR_LCD (1 << 30)
1.58 @@ -4477,204 +4448,8 @@
1.59 /***************************************************************************
1.60 * CPM
1.61 ***************************************************************************/
1.62 -#define __cpm_plcr1_fd() \
1.63 - ((REG_CPM_PLCR1 & CPM_PLCR1_PLL1FD_MASK) >> CPM_PLCR1_PLL1FD_BIT)
1.64 -#define __cpm_plcr1_rd() \
1.65 - ((REG_CPM_PLCR1 & CPM_PLCR1_PLL1RD_MASK) >> CPM_PLCR1_PLL1RD_BIT)
1.66 -#define __cpm_plcr1_od() \
1.67 - ((REG_CPM_PLCR1 & CPM_PLCR1_PLL1OD_MASK) >> CPM_PLCR1_PLL1OD_BIT)
1.68 -#define __cpm_cfcr_mfr() \
1.69 - ((REG_CPM_CFCR & CPM_CFCR_MFR_MASK) >> CPM_CFCR_MFR_BIT)
1.70 -#define __cpm_cfcr_pfr() \
1.71 - ((REG_CPM_CFCR & CPM_CFCR_PFR_MASK) >> CPM_CFCR_PFR_BIT)
1.72 -#define __cpm_cfcr_sfr() \
1.73 - ((REG_CPM_CFCR & CPM_CFCR_SFR_MASK) >> CPM_CFCR_SFR_BIT)
1.74 -#define __cpm_cfcr_ifr() \
1.75 - ((REG_CPM_CFCR & CPM_CFCR_IFR_MASK) >> CPM_CFCR_IFR_BIT)
1.76 -
1.77 -static __inline__ unsigned int __cpm_divisor_encode(unsigned int n)
1.78 -{
1.79 - unsigned int encode[10] = {1,2,3,4,6,8,12,16,24,32};
1.80 - int i;
1.81 - for (i=0;i<10;i++)
1.82 - if (n < encode[i])
1.83 - break;
1.84 - return i;
1.85 -}
1.86 -
1.87 -#define __cpm_set_mclk_div(n) \
1.88 -do { \
1.89 - REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_MFR_MASK) | \
1.90 - ((n) << (CPM_CFCR_MFR_BIT)); \
1.91 -} while (0)
1.92 -
1.93 -#define __cpm_set_pclk_div(n) \
1.94 -do { \
1.95 - REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_PFR_MASK) | \
1.96 - ((n) << (CPM_CFCR_PFR_BIT)); \
1.97 -} while (0)
1.98 -
1.99 -#define __cpm_set_sclk_div(n) \
1.100 -do { \
1.101 - REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_SFR_MASK) | \
1.102 - ((n) << (CPM_CFCR_SFR_BIT)); \
1.103 -} while (0)
1.104 -
1.105 -#define __cpm_set_iclk_div(n) \
1.106 -do { \
1.107 - REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_IFR_MASK) | \
1.108 - ((n) << (CPM_CFCR_IFR_BIT)); \
1.109 -} while (0)
1.110 -
1.111 -#define __cpm_set_lcdclk_div(n) \
1.112 -do { \
1.113 - REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_LFR_MASK) | \
1.114 - ((n) << (CPM_CFCR_LFR_BIT)); \
1.115 -} while (0)
1.116 -
1.117 -#define __cpm_enable_cko1() (REG_CPM_CFCR |= CPM_CFCR_CKOEN1)
1.118 -#define __cpm_enable_cko2() (REG_CPM_CFCR |= CPM_CFCR_CKOEN2)
1.119 -#define __cpm_disable_cko1() (REG_CPM_CFCR &= ~CPM_CFCR_CKOEN1)
1.120 -#define __cpm_disable_cko2() (REG_CPM_CFCR &= ~CPM_CFCR_CKOEN2)
1.121 -
1.122 -#define __cpm_idle_mode() \
1.123 - (REG_CPM_LPCR = (REG_CPM_LPCR & ~CPM_LPCR_LPM_MASK) | \
1.124 - CPM_LPCR_LPM_IDLE)
1.125 -#define __cpm_sleep_mode() \
1.126 - (REG_CPM_LPCR = (REG_CPM_LPCR & ~CPM_LPCR_LPM_MASK) | \
1.127 - CPM_LPCR_LPM_SLEEP)
1.128 -#define __cpm_hibernate_mode() \
1.129 - (REG_CPM_LPCR = (REG_CPM_LPCR & ~CPM_LPCR_LPM_MASK) | \
1.130 - CPM_LPCR_LPM_HIBERNATE)
1.131 -
1.132 -#define __cpm_start_uart0() \
1.133 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UART0))
1.134 -#define __cpm_start_uart1() \
1.135 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UART1))
1.136 -#define __cpm_start_uart2() \
1.137 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UART2))
1.138 -#define __cpm_start_uart3() \
1.139 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UART3))
1.140 -#define __cpm_start_ost() \
1.141 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_OST))
1.142 -#define __cpm_start_dmac() \
1.143 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_DMAC))
1.144 -#define __cpm_start_uhc() \
1.145 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UHC))
1.146 -#define __cpm_start_lcd() \
1.147 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_LCD))
1.148 -#define __cpm_start_i2c() \
1.149 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_I2C))
1.150 -#define __cpm_start_aic_pclk() \
1.151 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_AICPCLK))
1.152 -#define __cpm_start_aic_bitclk() \
1.153 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_AICBCLK))
1.154 -#define __cpm_start_pwm0() \
1.155 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_PWM0))
1.156 -#define __cpm_start_pwm1() \
1.157 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_PWM1))
1.158 -#define __cpm_start_ssi() \
1.159 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_SSI))
1.160 -#define __cpm_start_msc() \
1.161 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_MSC))
1.162 -#define __cpm_start_scc() \
1.163 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_SCC))
1.164 -#define __cpm_start_eth() \
1.165 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_ETH))
1.166 -#define __cpm_start_kbc() \
1.167 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_KBC))
1.168 -#define __cpm_start_cim() \
1.169 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_CIM))
1.170 -#define __cpm_start_udc() \
1.171 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UDC))
1.172 -#define __cpm_start_uprt() \
1.173 - (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UPRT))
1.174 -#define __cpm_start_all() (REG_CPM_MSCR = 0)
1.175 -
1.176 -#define __cpm_stop_uart0() \
1.177 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UART0))
1.178 -#define __cpm_stop_uart1() \
1.179 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UART1))
1.180 -#define __cpm_stop_uart2() \
1.181 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UART2))
1.182 -#define __cpm_stop_uart3() \
1.183 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UART3))
1.184 -#define __cpm_stop_ost() \
1.185 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_OST))
1.186 -#define __cpm_stop_dmac() \
1.187 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_DMAC))
1.188 -#define __cpm_stop_uhc() \
1.189 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UHC))
1.190 -#define __cpm_stop_lcd() \
1.191 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_LCD))
1.192 -#define __cpm_stop_i2c() \
1.193 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_I2C))
1.194 -#define __cpm_stop_aic_pclk() \
1.195 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_AICPCLK))
1.196 -#define __cpm_stop_aic_bitclk() \
1.197 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_AICBCLK))
1.198 -#define __cpm_stop_pwm0() \
1.199 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_PWM0))
1.200 -#define __cpm_stop_pwm1() \
1.201 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_PWM1))
1.202 -#define __cpm_stop_ssi() \
1.203 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_SSI))
1.204 -#define __cpm_stop_msc() \
1.205 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_MSC))
1.206 -#define __cpm_stop_scc() \
1.207 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_SCC))
1.208 -#define __cpm_stop_eth() \
1.209 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_ETH))
1.210 -#define __cpm_stop_kbc() \
1.211 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_KBC))
1.212 -#define __cpm_stop_cim() \
1.213 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_CIM))
1.214 -#define __cpm_stop_udc() \
1.215 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UDC))
1.216 -#define __cpm_stop_uprt() \
1.217 - (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UPRT))
1.218 -#define __cpm_stop_all() (REG_CPM_MSCR = 0xffffffff)
1.219 -
1.220 -#define __cpm_set_pin(n) \
1.221 -do { \
1.222 - unsigned int p, o; \
1.223 - p = (n) / 32; \
1.224 - o = (n) % 32; \
1.225 - if (p == 0) \
1.226 - REG_CPM_GSR0 |= (1 << o); \
1.227 - else if (p == 1) \
1.228 - REG_CPM_GSR1 |= (1 << o); \
1.229 - else if (p == 2) \
1.230 - REG_CPM_GSR2 |= (1 << o); \
1.231 - else if (p == 3) \
1.232 - REG_CPM_GSR3 |= (1 << o); \
1.233 -} while (0)
1.234 -
1.235 -#define __cpm_clear_pin(n) \
1.236 -do { \
1.237 - unsigned int p, o; \
1.238 - p = (n) / 32; \
1.239 - o = (n) % 32; \
1.240 - if (p == 0) \
1.241 - REG_CPM_GSR0 &= ~(1 << o); \
1.242 - else if (p == 1) \
1.243 - REG_CPM_GSR1 &= ~(1 << o); \
1.244 - else if (p == 2) \
1.245 - REG_CPM_GSR2 &= ~(1 << o); \
1.246 - else if (p == 3) \
1.247 - REG_CPM_GSR3 &= ~(1 << o); \
1.248 -} while (0)
1.249 -
1.250 -
1.251 -#define __cpm_select_msc_clk(type) \
1.252 -do { \
1.253 - if (type == 0) \
1.254 - REG_CPM_CFCR &= ~CPM_CFCR_MSC; \
1.255 - else \
1.256 - REG_CPM_CFCR |= CPM_CFCR_MSC; \
1.257 - REG_CPM_CFCR |= CPM_CFCR_UPE; \
1.258 -} while(0)
1.259 -
1.260 +
1.261 +/* Register operations using absolute positioning have been removed. */
1.262
1.263 /***************************************************************************
1.264 * SSI
1.265 @@ -4837,101 +4612,6 @@
1.266 #define __wdt_start() ( REG_WDT_WTCSR |= WDT_WTCSR_START )
1.267 #define __wdt_stop() ( REG_WDT_WTCSR &= ~WDT_WTCSR_START )
1.268
1.269 -
1.270 -/***************************************************************************
1.271 - ***************************************************************************/
1.272 -
1.273 -/*
1.274 - * CPU clocks
1.275 - */
1.276 -#define JZ_EXTAL CONFIG_SYS_EXTAL
1.277 -#define JZ_EXTAL2 32768 /* RTC clock */
1.278 -
1.279 -static __inline__ unsigned int __cpm_get_pllout(void)
1.280 -{
1.281 - unsigned int nf, nr, no, pllout;
1.282 - unsigned long plcr = REG_CPM_PLCR1;
1.283 - unsigned long od[4] = {1, 2, 2, 4};
1.284 - if (plcr & CPM_PLCR1_PLL1EN) {
1.285 - nf = (plcr & CPM_PLCR1_PLL1FD_MASK) >> CPM_PLCR1_PLL1FD_BIT;
1.286 - nr = (plcr & CPM_PLCR1_PLL1RD_MASK) >> CPM_PLCR1_PLL1RD_BIT;
1.287 - no = od[((plcr & CPM_PLCR1_PLL1OD_MASK) >> CPM_PLCR1_PLL1OD_BIT)];
1.288 - pllout = (JZ_EXTAL) / ((nr+2) * no) * (nf+2);
1.289 - } else
1.290 - pllout = JZ_EXTAL;
1.291 - return pllout;
1.292 -}
1.293 -
1.294 -static __inline__ unsigned int __cpm_get_iclk(void)
1.295 -{
1.296 - unsigned int iclk;
1.297 - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.298 - unsigned long cfcr = REG_CPM_CFCR;
1.299 - unsigned long plcr = REG_CPM_PLCR1;
1.300 - if (plcr & CPM_PLCR1_PLL1EN)
1.301 - iclk = __cpm_get_pllout() /
1.302 - div[(cfcr & CPM_CFCR_IFR_MASK) >> CPM_CFCR_IFR_BIT];
1.303 - else
1.304 - iclk = JZ_EXTAL;
1.305 - return iclk;
1.306 -}
1.307 -
1.308 -static __inline__ unsigned int __cpm_get_sclk(void)
1.309 -{
1.310 - unsigned int sclk;
1.311 - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.312 - unsigned long cfcr = REG_CPM_CFCR;
1.313 - unsigned long plcr = REG_CPM_PLCR1;
1.314 - if (plcr & CPM_PLCR1_PLL1EN)
1.315 - sclk = __cpm_get_pllout() /
1.316 - div[(cfcr & CPM_CFCR_SFR_MASK) >> CPM_CFCR_SFR_BIT];
1.317 - else
1.318 - sclk = JZ_EXTAL;
1.319 - return sclk;
1.320 -}
1.321 -
1.322 -static __inline__ unsigned int __cpm_get_mclk(void)
1.323 -{
1.324 - unsigned int mclk;
1.325 - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.326 - unsigned long cfcr = REG_CPM_CFCR;
1.327 - unsigned long plcr = REG_CPM_PLCR1;
1.328 - if (plcr & CPM_PLCR1_PLL1EN)
1.329 - mclk = __cpm_get_pllout() /
1.330 - div[(cfcr & CPM_CFCR_MFR_MASK) >> CPM_CFCR_MFR_BIT];
1.331 - else
1.332 - mclk = JZ_EXTAL;
1.333 - return mclk;
1.334 -}
1.335 -
1.336 -static __inline__ unsigned int __cpm_get_pclk(void)
1.337 -{
1.338 - unsigned int devclk;
1.339 - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.340 - unsigned long cfcr = REG_CPM_CFCR;
1.341 - unsigned long plcr = REG_CPM_PLCR1;
1.342 - if (plcr & CPM_PLCR1_PLL1EN)
1.343 - devclk = __cpm_get_pllout() /
1.344 - div[(cfcr & CPM_CFCR_PFR_MASK) >> CPM_CFCR_PFR_BIT];
1.345 - else
1.346 - devclk = JZ_EXTAL;
1.347 - return devclk;
1.348 -}
1.349 -
1.350 -static __inline__ unsigned int __cpm_get_devclk(void)
1.351 -{
1.352 - unsigned int devclk;
1.353 - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.354 - unsigned long cfcr = REG_CPM_CFCR;
1.355 - unsigned long plcr = REG_CPM_PLCR1;
1.356 - if (plcr & CPM_PLCR1_PLL1EN)
1.357 - devclk = __cpm_get_pllout() /
1.358 - div[(cfcr & CPM_CFCR_PFR_MASK) >> CPM_CFCR_PFR_BIT];
1.359 - else
1.360 - devclk = JZ_EXTAL;
1.361 - return devclk;
1.362 -}
1.363 -
1.364 #endif /* !__ASSEMBLY__ */
1.365
1.366 #endif /* __JZ4730_H__ */
2.1 --- a/include/jz4730_compat.h Sun Jul 09 19:04:49 2017 +0200
2.2 +++ b/include/jz4730_compat.h Tue Jul 11 00:03:30 2017 +0200
2.3 @@ -1,7 +1,7 @@
2.4 /*
2.5 * Compatibility definitions for using jz4740 code with the jz4730.
2.6 *
2.7 - * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
2.8 + * Copyright (C) 2015, 2017 Paul Boddie <paul@boddie.org.uk>
2.9 *
2.10 * This program is free software: you can redistribute it and/or modify
2.11 * it under the terms of the GNU General Public License as published by
2.12 @@ -20,9 +20,6 @@
2.13 #ifndef __JZ4730_COMPAT_H__
2.14 #define __JZ4730_COMPAT_H__
2.15
2.16 -#define REG_CPM_CPCCR REG_CPM_CFCR
2.17 -#define REG_CPM_CPPCR REG_CPM_PLCR1
2.18 -
2.19 #define CPM_CPCCR_CE CPM_CFCR_UPE
2.20 #define CPM_CPCCR_CDIV_BIT CPM_CFCR_IFR_BIT
2.21 #define CPM_CPCCR_HDIV_BIT CPM_CFCR_SFR_BIT
2.22 @@ -30,12 +27,16 @@
2.23 #define CPM_CPCCR_MDIV_BIT CPM_CFCR_LFR_BIT
2.24 #define CPM_CPCCR_LDIV_BIT CPM_CFCR_MFR_BIT
2.25
2.26 +#define CPM_CPCCR_LDIV_MASK CPM_CFCR_LFR_MASK
2.27 +
2.28 #define CPM_CPPCR_PLLM_BIT CPM_PLCR1_PLL1FD_BIT
2.29 #define CPM_CPPCR_PLLN_BIT CPM_PLCR1_PLL1RD_BIT
2.30 #define CPM_CPPCR_PLLOD_BIT CPM_PLCR1_PLL1OD_BIT
2.31 #define CPM_CPPCR_PLLST_BIT CPM_PLCR1_PLL1ST_BIT
2.32 #define CPM_CPPCR_PLLEN CPM_PLCR1_PLL1EN
2.33
2.34 -#define __cpm_set_ldiv __cpm_set_lcdclk_div
2.35 +#define CPM_CPPCR_PLLM_MASK CPM_PLCR1_PLL1FD_MASK
2.36 +#define CPM_CPPCR_PLLN_MASK CPM_PLCR1_PLL1RD_MASK
2.37 +#define CPM_CPPCR_PLLOD_MASK CPM_PLCR1_PLL1OD_MASK
2.38
2.39 #endif /* __JZ4730_COMPAT_H__ */
3.1 --- a/include/jz4740.h Sun Jul 09 19:04:49 2017 +0200
3.2 +++ b/include/jz4740.h Tue Jul 11 00:03:30 2017 +0200
3.3 @@ -4,7 +4,7 @@
3.4 * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
3.5 * Copyright (C) 2009 Qi Hardware Inc.
3.6 * Author: Xiangfu Liu <xiangfu@sharism.cc>
3.7 - * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
3.8 + * Copyright (C) 2015, 2017 Paul Boddie <paul@boddie.org.uk>
3.9 *
3.10 * This program is free software; you can redistribute it and/or
3.11 * modify it under the terms of the GNU General Public License as
3.12 @@ -32,6 +32,9 @@
3.13 #define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
3.14 #define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */
3.15
3.16 +#define JZ_EXTAL CONFIG_SYS_EXTAL
3.17 +#define JZ_EXTAL2 32768 /* RTC clock */
3.18 +
3.19 /* Boot ROM Specification */
3.20 /* NOR Boot config */
3.21 #define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */
3.22 @@ -180,47 +183,6 @@
3.23
3.24 /* Register definitions with absolute positioning have been removed. */
3.25
3.26 -#define CPM_CPCCR (CPM_BASE+0x00)
3.27 -#define CPM_CPPCR (CPM_BASE+0x10)
3.28 -#define CPM_I2SCDR (CPM_BASE+0x60)
3.29 -#define CPM_LPCDR (CPM_BASE+0x64)
3.30 -#define CPM_MSCCDR (CPM_BASE+0x68)
3.31 -#define CPM_UHCCDR (CPM_BASE+0x6C)
3.32 -
3.33 -#define CPM_LCR (CPM_BASE+0x04)
3.34 -#define CPM_CLKGR (CPM_BASE+0x20)
3.35 -#define CPM_SCR (CPM_BASE+0x24)
3.36 -
3.37 -#define CPM_HCR (CPM_BASE+0x30)
3.38 -#define CPM_HWFCR (CPM_BASE+0x34)
3.39 -#define CPM_HRCR (CPM_BASE+0x38)
3.40 -#define CPM_HWCR (CPM_BASE+0x3c)
3.41 -#define CPM_HWSR (CPM_BASE+0x40)
3.42 -#define CPM_HSPR (CPM_BASE+0x44)
3.43 -
3.44 -#define CPM_RSR (CPM_BASE+0x08)
3.45 -
3.46 -
3.47 -#define REG_CPM_CPCCR REG32(CPM_CPCCR)
3.48 -#define REG_CPM_CPPCR REG32(CPM_CPPCR)
3.49 -#define REG_CPM_I2SCDR REG32(CPM_I2SCDR)
3.50 -#define REG_CPM_LPCDR REG32(CPM_LPCDR)
3.51 -#define REG_CPM_MSCCDR REG32(CPM_MSCCDR)
3.52 -#define REG_CPM_UHCCDR REG32(CPM_UHCCDR)
3.53 -
3.54 -#define REG_CPM_LCR REG32(CPM_LCR)
3.55 -#define REG_CPM_CLKGR REG32(CPM_CLKGR)
3.56 -#define REG_CPM_SCR REG32(CPM_SCR)
3.57 -#define REG_CPM_HCR REG32(CPM_HCR)
3.58 -#define REG_CPM_HWFCR REG32(CPM_HWFCR)
3.59 -#define REG_CPM_HRCR REG32(CPM_HRCR)
3.60 -#define REG_CPM_HWCR REG32(CPM_HWCR)
3.61 -#define REG_CPM_HWSR REG32(CPM_HWSR)
3.62 -#define REG_CPM_HSPR REG32(CPM_HSPR)
3.63 -
3.64 -#define REG_CPM_RSR REG32(CPM_RSR)
3.65 -
3.66 -
3.67 /* Clock Control Register */
3.68 #define CPM_CPCCR_I2CS (1 << 31)
3.69 #define CPM_CPCCR_CLKOEN (1 << 30)
3.70 @@ -246,7 +208,7 @@
3.71
3.72 /* LCD Pixel Clock Divider Register */
3.73 #define CPM_LPCDR_PIXDIV_BIT 0
3.74 -#define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT)
3.75 +#define CPM_LPCDR_PIXDIV_MASK (0x7ff << CPM_LPCDR_PIXDIV_BIT)
3.76
3.77 /* MSC Clock Divider Register */
3.78 #define CPM_MSCCDR_MSCDIV_BIT 0
3.79 @@ -3054,248 +3016,8 @@
3.80 /***************************************************************************
3.81 * CPM
3.82 ***************************************************************************/
3.83 -#define __cpm_get_pllm() \
3.84 - ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT)
3.85 -#define __cpm_get_plln() \
3.86 - ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT)
3.87 -#define __cpm_get_pllod() \
3.88 - ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT)
3.89 -
3.90 -#define __cpm_get_cdiv() \
3.91 - ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT)
3.92 -#define __cpm_get_hdiv() \
3.93 - ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT)
3.94 -#define __cpm_get_pdiv() \
3.95 - ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT)
3.96 -#define __cpm_get_mdiv() \
3.97 - ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT)
3.98 -#define __cpm_get_ldiv() \
3.99 - ((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT)
3.100 -#define __cpm_get_udiv() \
3.101 - ((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT)
3.102 -#define __cpm_get_i2sdiv() \
3.103 - ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT)
3.104 -#define __cpm_get_pixdiv() \
3.105 - ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT)
3.106 -#define __cpm_get_mscdiv() \
3.107 - ((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT)
3.108 -
3.109 -#define __cpm_set_cdiv(v) \
3.110 - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT)))
3.111 -#define __cpm_set_hdiv(v) \
3.112 - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT)))
3.113 -#define __cpm_set_pdiv(v) \
3.114 - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT)))
3.115 -#define __cpm_set_mdiv(v) \
3.116 - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT)))
3.117 -#define __cpm_set_ldiv(v) \
3.118 - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT)))
3.119 -#define __cpm_set_udiv(v) \
3.120 - (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT)))
3.121 -#define __cpm_set_i2sdiv(v) \
3.122 - (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT)))
3.123 -#define __cpm_set_pixdiv(v) \
3.124 - (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT)))
3.125 -#define __cpm_set_mscdiv(v) \
3.126 - (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT)))
3.127 -
3.128 -#define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS)
3.129 -#define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS)
3.130 -#define __cpm_enable_cko() (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN)
3.131 -#define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS)
3.132 -#define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS)
3.133 -#define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE)
3.134 -#define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS)
3.135 -#define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS)
3.136 -
3.137 -#define __cpm_pll_is_on() (REG_CPM_CPPCR & CPM_CPPCR_PLLS)
3.138 -#define __cpm_pll_bypass() (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP)
3.139 -#define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN)
3.140 -
3.141 -#define __cpm_get_cclk_doze_duty() \
3.142 - ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT)
3.143 -#define __cpm_set_cclk_doze_duty(v) \
3.144 - (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT)))
3.145 -
3.146 -#define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON)
3.147 -#define __cpm_idle_mode() \
3.148 - (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE)
3.149 -#define __cpm_sleep_mode() \
3.150 - (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP)
3.151 -
3.152 -#define __cpm_stop_all() (REG_CPM_CLKGR = 0x7fff)
3.153 -#define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1)
3.154 -#define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC)
3.155 -#define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU)
3.156 -#define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC)
3.157 -#define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC)
3.158 -#define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD)
3.159 -#define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM)
3.160 -#define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC)
3.161 -#define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC)
3.162 -#define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1)
3.163 -#define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2)
3.164 -#define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI)
3.165 -#define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C)
3.166 -#define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC)
3.167 -#define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU)
3.168 -#define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0)
3.169 -
3.170 -#define __cpm_start_all() (REG_CPM_CLKGR = 0x0)
3.171 -#define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1)
3.172 -#define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC)
3.173 -#define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU)
3.174 -#define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC)
3.175 -#define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC)
3.176 -#define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD)
3.177 -#define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM)
3.178 -#define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC)
3.179 -#define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC)
3.180 -#define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1)
3.181 -#define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2)
3.182 -#define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI)
3.183 -#define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C)
3.184 -#define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC)
3.185 -#define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU)
3.186 -#define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0)
3.187 -
3.188 -#define __cpm_get_o1st() \
3.189 - ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT)
3.190 -#define __cpm_set_o1st(v) \
3.191 - (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT)))
3.192 -#define __cpm_suspend_udcphy() (REG_CPM_SCR &= ~CPM_SCR_UDCPHY_ENABLE)
3.193 -#define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_DISABLE)
3.194 -#define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE)
3.195 -
3.196 -#define JZ_EXTAL CONFIG_SYS_EXTAL
3.197 -#define JZ_EXTAL2 32768 /* RTC clock */
3.198 -
3.199 -/* PLL output frequency */
3.200 -static __inline__ unsigned int __cpm_get_pllout(void)
3.201 -{
3.202 - unsigned long m, n, no, pllout;
3.203 - unsigned long cppcr = REG_CPM_CPPCR;
3.204 - unsigned long od[4] = {1, 2, 2, 4};
3.205 - if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) {
3.206 - m = __cpm_get_pllm() + 2;
3.207 - n = __cpm_get_plln() + 2;
3.208 - no = od[__cpm_get_pllod()];
3.209 - pllout = ((JZ_EXTAL) / (n * no)) * m;
3.210 - } else
3.211 - pllout = JZ_EXTAL;
3.212 - return pllout;
3.213 -}
3.214 -
3.215 -/* PLL output frequency for MSC/I2S/LCD/USB */
3.216 -static __inline__ unsigned int __cpm_get_pllout2(void)
3.217 -{
3.218 - if (REG_CPM_CPCCR & CPM_CPCCR_PCS)
3.219 - return __cpm_get_pllout();
3.220 - else
3.221 - return __cpm_get_pllout()/2;
3.222 -}
3.223 -
3.224 -/* CPU core clock */
3.225 -static __inline__ unsigned int __cpm_get_cclk(void)
3.226 -{
3.227 - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3.228 -
3.229 - return __cpm_get_pllout() / div[__cpm_get_cdiv()];
3.230 -}
3.231 -
3.232 -/* AHB system bus clock */
3.233 -static __inline__ unsigned int __cpm_get_hclk(void)
3.234 -{
3.235 - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3.236 -
3.237 - return __cpm_get_pllout() / div[__cpm_get_hdiv()];
3.238 -}
3.239 -
3.240 -/* Memory bus clock */
3.241 -static __inline__ unsigned int __cpm_get_mclk(void)
3.242 -{
3.243 - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3.244 -
3.245 - return __cpm_get_pllout() / div[__cpm_get_mdiv()];
3.246 -}
3.247 -
3.248 -/* APB peripheral bus clock */
3.249 -static __inline__ unsigned int __cpm_get_pclk(void)
3.250 -{
3.251 - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3.252 -
3.253 - return __cpm_get_pllout() / div[__cpm_get_pdiv()];
3.254 -}
3.255 -
3.256 -/* LCDC module clock */
3.257 -static __inline__ unsigned int __cpm_get_lcdclk(void)
3.258 -{
3.259 - return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1);
3.260 -}
3.261 -
3.262 -/* LCD pixel clock */
3.263 -static __inline__ unsigned int __cpm_get_pixclk(void)
3.264 -{
3.265 - return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1);
3.266 -}
3.267 -
3.268 -/* I2S clock */
3.269 -static __inline__ unsigned int __cpm_get_i2sclk(void)
3.270 -{
3.271 - if (REG_CPM_CPCCR & CPM_CPCCR_I2CS) {
3.272 - return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1);
3.273 - }
3.274 - else {
3.275 - return JZ_EXTAL;
3.276 - }
3.277 -}
3.278 -
3.279 -/* USB clock */
3.280 -static __inline__ unsigned int __cpm_get_usbclk(void)
3.281 -{
3.282 - if (REG_CPM_CPCCR & CPM_CPCCR_UCS) {
3.283 - return __cpm_get_pllout2() / (__cpm_get_udiv() + 1);
3.284 - }
3.285 - else {
3.286 - return JZ_EXTAL;
3.287 - }
3.288 -}
3.289 -
3.290 -/* MSC clock */
3.291 -static __inline__ unsigned int __cpm_get_mscclk(void)
3.292 -{
3.293 - return __cpm_get_pllout2() / (__cpm_get_mscdiv() + 1);
3.294 -}
3.295 -
3.296 -/* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */
3.297 -static __inline__ unsigned int __cpm_get_extalclk(void)
3.298 -{
3.299 - return JZ_EXTAL;
3.300 -}
3.301 -
3.302 -/* RTC clock for CPM,INTC,RTC,TCU,WDT */
3.303 -static __inline__ unsigned int __cpm_get_rtcclk(void)
3.304 -{
3.305 - return JZ_EXTAL2;
3.306 -}
3.307 -
3.308 -/*
3.309 - * Output 24MHz for SD and 16MHz for MMC.
3.310 - */
3.311 -static inline void __cpm_select_msc_clk(int sd)
3.312 -{
3.313 - unsigned int pllout2 = __cpm_get_pllout2();
3.314 - unsigned int div = 0;
3.315 -
3.316 - if (sd) {
3.317 - div = pllout2 / 24000000;
3.318 - }
3.319 - else {
3.320 - div = pllout2 / 16000000;
3.321 - }
3.322 -
3.323 - REG_CPM_MSCCDR = div - 1;
3.324 -}
3.325 +
3.326 +/* Register operations using absolute positioning have been removed. */
3.327
3.328 /*
3.329 * TCU
4.1 --- a/stage1/Makefile Sun Jul 09 19:04:49 2017 +0200
4.2 +++ b/stage1/Makefile Tue Jul 11 00:03:30 2017 +0200
4.3 @@ -1,6 +1,6 @@
4.4 # Makefile - Build the NanoNote payload
4.5 #
4.6 -# Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
4.7 +# Copyright (C) 2015, 2017 Paul Boddie <paul@boddie.org.uk>
4.8 # Copyright (C) Xiangfu Liu <xiangfu@sharism.cc>
4.9 #
4.10 # This program is free software: you can redistribute it and/or modify
4.11 @@ -41,8 +41,8 @@
4.12
4.13 # Ordering of objects is important and cannot be left to replacement rules.
4.14
4.15 -SRC = head1.S stage1.c board.c
4.16 -OBJ = head1.o stage1.o board.o
4.17 +SRC = head1.S stage1.c board.c cpm.c
4.18 +OBJ = head1.o stage1.o board.o cpm.o
4.19
4.20 .PHONY: all clean distclean
4.21
5.1 --- a/stage1/board.c Sun Jul 09 19:04:49 2017 +0200
5.2 +++ b/stage1/board.c Tue Jul 11 00:03:30 2017 +0200
5.3 @@ -30,6 +30,7 @@
5.4
5.5 #include "memory.h"
5.6 #include "sdram.h"
5.7 +#include "cpm.h"
5.8 #include "usb_boot_defines.h"
5.9
5.10 /* These arguments are initialised by usbboot and are defined in...
5.11 @@ -111,7 +112,7 @@
5.12 pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
5.13
5.14 /* Divisor == UHCCDR + 1 */
5.15 - REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
5.16 + jz4740_cpm_ctrl_set((void *) CPM_BASE, CPM_UHCCDR, pllout2 / 48000000 - 1);
5.17 #endif
5.18
5.19 nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
5.20 @@ -122,15 +123,14 @@
5.21
5.22 /* Update PLL and wait. */
5.23
5.24 - REG_CPM_CPCCR = cfcr;
5.25 - REG_CPM_CPPCR = plcr1;
5.26 - while (!__cpm_pll_is_on());
5.27 + jz4740_cpm_ctrl_set((void *) CPM_BASE, CPM_CPCCR, cfcr);
5.28 + jz4740_cpm_ctrl_set((void *) CPM_BASE, CPM_CPPCR, plcr1);
5.29 + while (!jz4740_cpm_have_pll((void *) CPM_BASE));
5.30 }
5.31
5.32 void sdram_init()
5.33 {
5.34 register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
5.35 - unsigned int pllout = __cpm_get_pllout();
5.36
5.37 unsigned int cas_latency_sdmr[2] = {
5.38 EMC_SDMR_CAS_2,
5.39 @@ -142,12 +142,8 @@
5.40 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
5.41 };
5.42
5.43 - /* Divisors for CPCCR values. */
5.44 -
5.45 - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
5.46 -
5.47 - cpu_clk = pllout / div[__cpm_get_cdiv()];
5.48 - mem_clk = pllout / div[__cpm_get_mdiv()];
5.49 + cpu_clk = jz4740_cpm_get_cpu_frequency((void *) CPM_BASE);
5.50 + mem_clk = jz4740_cpm_get_memory_frequency((void *) CPM_BASE);
5.51
5.52 REG_EMC_BCR = 0; /* Disable bus release */
5.53 REG_EMC_RTCSR = 0; /* Disable clock for counting */
6.1 --- a/stage1/board.h Sun Jul 09 19:04:49 2017 +0200
6.2 +++ b/stage1/board.h Tue Jul 11 00:03:30 2017 +0200
6.3 @@ -8,4 +8,17 @@
6.4 void pll_init();
6.5 void sdram_init();
6.6
6.7 +/* Select the CPU definitions according to the configuration. */
6.8 +
6.9 +#ifdef CONFIG_CPU_JZ4730
6.10 +
6.11 +#include "jz4730.h"
6.12 +#include "jz4730_compat.h"
6.13 +
6.14 +#else
6.15 +
6.16 +#include "jz4740.h"
6.17 +
6.18 +#endif
6.19 +
6.20 #endif /* __BOARD_H__ */
7.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
7.2 +++ b/stage1/cpm.c Tue Jul 11 00:03:30 2017 +0200
7.3 @@ -0,0 +1,1 @@
7.4 +../stage2/cpm.c
7.5 \ No newline at end of file
8.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
8.2 +++ b/stage1/cpm.h Tue Jul 11 00:03:30 2017 +0200
8.3 @@ -0,0 +1,1 @@
8.4 +../stage2/cpm.h
8.5 \ No newline at end of file
9.1 --- a/stage2/Makefile Sun Jul 09 19:04:49 2017 +0200
9.2 +++ b/stage2/Makefile Tue Jul 11 00:03:30 2017 +0200
9.3 @@ -1,6 +1,6 @@
9.4 # Makefile - Build the NanoNote payload
9.5 #
9.6 -# Copyright (C) 2015, 2016 Paul Boddie <paul@boddie.org.uk>
9.7 +# Copyright (C) 2015, 2016, 2017 Paul Boddie <paul@boddie.org.uk>
9.8 # Copyright (C) Xiangfu Liu <xiangfu@sharism.cc>
9.9 #
9.10 # This program is free software: you can redistribute it and/or modify
9.11 @@ -60,7 +60,7 @@
9.12
9.13 # Configure generic objects.
9.14
9.15 -CORE_SRC = stage2.c cpu.c lcd.c jzlcd.c board.c irq.c paging.c tasks.c task_gpio.c
9.16 +CORE_SRC = stage2.c cpm.c cpu.c lcd.c jzlcd.c board.c irq.c paging.c tasks.c task_gpio.c
9.17 CORE_OBJ = $(CORE_SRC:.c=.o)
9.18
9.19 # Add tasks.
10.1 --- a/stage2/board-minipc.c Sun Jul 09 19:04:49 2017 +0200
10.2 +++ b/stage2/board-minipc.c Tue Jul 11 00:03:30 2017 +0200
10.3 @@ -59,11 +59,6 @@
10.4 }
10.5 }
10.6
10.7 -void cpm_init()
10.8 -{
10.9 - __cpm_stop_all();
10.10 -}
10.11 -
10.12 void rtc_init()
10.13 {
10.14 /* NOTE: May only be accessible via I2C. */
10.15 @@ -85,7 +80,7 @@
10.16 __ost_set_count(TIMER_CHAN, TIMER_FDATA);
10.17 __ost_enable_channel(TIMER_CHAN);
10.18
10.19 - __cpm_start_ost();
10.20 + jz4740_cpm_start_clock((void *) CPM_BASE);
10.21
10.22 lastdec = TIMER_FDATA;
10.23 timestamp = 0;
10.24 @@ -125,5 +120,5 @@
10.25
10.26 int is_started()
10.27 {
10.28 - return REG_CPM_MSCR != 0;
10.29 + return jz4740_cpm_have_clock((void *) CPM_BASE);
10.30 }
11.1 --- a/stage2/board-nanonote.c Sun Jul 09 19:04:49 2017 +0200
11.2 +++ b/stage2/board-nanonote.c Tue Jul 11 00:03:30 2017 +0200
11.3 @@ -22,6 +22,7 @@
11.4
11.5 #include "board.h"
11.6 #include "nanonote.h"
11.7 +#include "cpm.h"
11.8
11.9 /* Later initialisation functions. */
11.10
11.11 @@ -68,20 +69,6 @@
11.12 __gpio_as_pwm4();
11.13 }
11.14
11.15 -void cpm_init()
11.16 -{
11.17 - __cpm_stop_ipu();
11.18 - __cpm_stop_cim();
11.19 - __cpm_stop_i2c();
11.20 - __cpm_stop_ssi();
11.21 - __cpm_stop_uart1();
11.22 - __cpm_stop_sadc();
11.23 - __cpm_stop_uhc();
11.24 - __cpm_stop_udc();
11.25 - __cpm_stop_aic1();
11.26 -/* __cpm_stop_aic2();*/
11.27 -}
11.28 -
11.29 void rtc_init()
11.30 {
11.31 while ( !__rtc_write_ready());
11.32 @@ -120,7 +107,7 @@
11.33 __tcu_start_timer_clock(TIMER_CHAN);
11.34 __tcu_start_counter(TIMER_CHAN);
11.35
11.36 - __cpm_start_tcu();
11.37 + jz4740_cpm_start_clock((void *) CPM_BASE);
11.38
11.39 lastdec = 0;
11.40 timestamp = 0;
11.41 @@ -158,5 +145,5 @@
11.42
11.43 int is_started()
11.44 {
11.45 - return REG_CPM_CLKGR != 0;
11.46 + return jz4740_cpm_have_clock((void *) CPM_BASE);
11.47 }
12.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
12.2 +++ b/stage2/cpm.c Tue Jul 11 00:03:30 2017 +0200
12.3 @@ -0,0 +1,260 @@
12.4 +/*
12.5 + * Clock and power management.
12.6 + *
12.7 + * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc>
12.8 + * Copyright (C) 2015, 2016, 2017 Paul Boddie <paul@boddie.org.uk>
12.9 + *
12.10 + * This program is free software: you can redistribute it and/or modify
12.11 + * it under the terms of the GNU General Public License as published by
12.12 + * the Free Software Foundation, either version 3 of the License, or
12.13 + * (at your option) any later version.
12.14 + *
12.15 + * This program is distributed in the hope that it will be useful,
12.16 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
12.17 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12.18 + * GNU General Public License for more details.
12.19 + *
12.20 + * You should have received a copy of the GNU General Public License
12.21 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
12.22 + */
12.23 +
12.24 +#include "xburst_types.h"
12.25 +#include "cpm.h"
12.26 +#include "board.h"
12.27 +
12.28 +static uint32_t cpm_ctrl_get(void *cpm_base, uint32_t reg)
12.29 +{
12.30 + return REG32(cpm_base + reg);
12.31 +}
12.32 +
12.33 +static void cpm_ctrl_set(void *cpm_base, uint32_t reg, uint32_t value)
12.34 +{
12.35 + REG32(cpm_base + reg) = value;
12.36 +}
12.37 +
12.38 +static int pll_enabled(void *cpm_base)
12.39 +{
12.40 + return cpm_ctrl_get(cpm_base, CPM_CPPCR) & CPM_CPPCR_PLLEN;
12.41 +}
12.42 +
12.43 +static int pll_bypassed(void *cpm_base)
12.44 +{
12.45 + return cpm_ctrl_get(cpm_base, CPM_CPPCR) & CPM_CPPCR_PLLBP;
12.46 +}
12.47 +
12.48 +// Feedback (9-bit) divider.
12.49 +
12.50 +static uint16_t get_multiplier(void *cpm_base)
12.51 +{
12.52 + return ((cpm_ctrl_get(cpm_base, CPM_CPPCR) & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT) + 2;
12.53 +}
12.54 +
12.55 +// Input (5-bit) divider.
12.56 +
12.57 +static uint8_t get_input_divider(void *cpm_base)
12.58 +{
12.59 + return ((cpm_ctrl_get(cpm_base, CPM_CPPCR) & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT) + 2;
12.60 +}
12.61 +
12.62 +// Output divider.
12.63 +
12.64 +static uint8_t get_output_divider(void *cpm_base)
12.65 +{
12.66 + uint8_t od[] = {1, 2, 2, 4};
12.67 + return od[(cpm_ctrl_get(cpm_base, CPM_CPPCR) & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT];
12.68 +}
12.69 +
12.70 +// General clock divider.
12.71 +
12.72 +static uint8_t _get_divider(void *cpm_base, uint32_t reg, uint32_t mask, uint8_t shift)
12.73 +{
12.74 + uint8_t cd[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
12.75 + uint8_t d = (cpm_ctrl_get(cpm_base, reg) & mask) >> shift;
12.76 + return (d < 10) ? cd[d] : 1;
12.77 +}
12.78 +
12.79 +// CPU clock divider.
12.80 +
12.81 +static uint8_t get_cpu_divider(void *cpm_base)
12.82 +{
12.83 + return _get_divider(cpm_base, CPM_CPCCR, CPM_CPCCR_CDIV_MASK, CPM_CPCCR_CDIV_BIT);
12.84 +}
12.85 +
12.86 +// Memory clock divider.
12.87 +
12.88 +static uint8_t get_memory_divider(void *cpm_base)
12.89 +{
12.90 + return _get_divider(cpm_base, CPM_CPCCR, CPM_CPCCR_MDIV_MASK, CPM_CPCCR_MDIV_BIT);
12.91 +}
12.92 +
12.93 +// Clock source divider for MSC, I2S, LCD and USB.
12.94 +
12.95 +static uint8_t get_source_divider(void *cpm_base)
12.96 +{
12.97 +#ifdef CONFIG_CPU_JZ4730
12.98 + return 1;
12.99 +#else
12.100 + return cpm_ctrl_get(cpm_base, CPM_CPCCR) & CPM_CPCCR_PCS ? 1 : 2;
12.101 +#endif
12.102 +}
12.103 +
12.104 +// LCD device clock divider.
12.105 +
12.106 +static void set_lcd_device_divider(void *cpm_base, uint8_t division)
12.107 +{
12.108 + if (division == 0)
12.109 + division = 1;
12.110 +#ifdef CONFIG_CPU_JZ4730
12.111 + else if (division > 16)
12.112 + division = 16;
12.113 +#else
12.114 + else if (division > 32)
12.115 + division = 32;
12.116 +#endif
12.117 +
12.118 + cpm_ctrl_set(cpm_base, CPM_CPCCR,
12.119 + (cpm_ctrl_get(cpm_base, CPM_CPCCR) & ~CPM_CPCCR_LDIV_MASK) |
12.120 + ((division - 1) << CPM_CPCCR_LDIV_BIT));
12.121 +}
12.122 +
12.123 +// LCD pixel clock divider.
12.124 +
12.125 +static void set_lcd_pixel_divider(void *cpm_base, uint16_t division)
12.126 +{
12.127 +#ifndef CONFIG_CPU_JZ4730
12.128 + if (division == 0)
12.129 + division = 1;
12.130 + else if (division > 2048)
12.131 + division = 2048;
12.132 +
12.133 + cpm_ctrl_set(cpm_base, CPM_LPCDR,
12.134 + (cpm_ctrl_get(cpm_base, CPM_LPCDR) & ~CPM_LPCDR_PIXDIV_MASK) |
12.135 + (division - 1));
12.136 +#endif
12.137 +}
12.138 +
12.139 +static uint32_t get_pll_frequency(void *cpm_base)
12.140 +{
12.141 + // Test for PLL enable and not PLL bypass.
12.142 +
12.143 + if (pll_enabled(cpm_base) && !pll_bypassed(cpm_base))
12.144 + return (JZ_EXTAL * get_multiplier(cpm_base)) /
12.145 + (get_input_divider(cpm_base) * get_output_divider(cpm_base));
12.146 + else
12.147 + return JZ_EXTAL;
12.148 +}
12.149 +
12.150 +// Clock frequency for MSC, I2S, LCD and USB.
12.151 +
12.152 +static uint32_t get_output_frequency(void *cpm_base)
12.153 +{
12.154 + return get_pll_frequency(cpm_base) / get_source_divider(cpm_base);
12.155 +}
12.156 +
12.157 +
12.158 +
12.159 +/* Public functions. */
12.160 +
12.161 +// Clock frequency for the CPU.
12.162 +
12.163 +uint32_t jz4740_cpm_get_cpu_frequency(void *cpm_base)
12.164 +{
12.165 + return get_pll_frequency(cpm_base) / get_cpu_divider(cpm_base);
12.166 +}
12.167 +
12.168 +// Clock frequency for the memory.
12.169 +
12.170 +uint32_t jz4740_cpm_get_memory_frequency(void *cpm_base)
12.171 +{
12.172 + return get_pll_frequency(cpm_base) / get_memory_divider(cpm_base);
12.173 +}
12.174 +
12.175 +// Set the device and pixel frequencies, indicating the latter and
12.176 +// providing the device:pixel frequency ratio.
12.177 +
12.178 +void jz4740_cpm_set_lcd_frequencies(void *cpm_base, uint32_t pclk, uint8_t ratio)
12.179 +{
12.180 + uint32_t out = get_output_frequency(cpm_base), lcd = pclk * ratio;
12.181 +
12.182 + set_lcd_pixel_divider(cpm_base, out / pclk);
12.183 +
12.184 + // Limit the device frequency to 150MHz.
12.185 +
12.186 + if (lcd > 150000000) lcd = 150000000;
12.187 +
12.188 + set_lcd_device_divider(cpm_base, out / lcd);
12.189 +}
12.190 +
12.191 +// Update the clock output frequency.
12.192 +
12.193 +void jz4740_cpm_update_output_frequency(void *cpm_base)
12.194 +{
12.195 + cpm_ctrl_set(cpm_base, CPM_CPCCR, cpm_ctrl_get(cpm_base, CPM_CPCCR) | CPM_CPCCR_CE);
12.196 +}
12.197 +
12.198 +// General clock functions.
12.199 +
12.200 +int jz4740_cpm_have_clock(void *cpm_base)
12.201 +{
12.202 + // NOTE: To check.
12.203 +#ifdef CONFIG_CPU_JZ4730
12.204 + return cpm_ctrl_get(cpm_base, CPM_MSCR) != 0;
12.205 +#else
12.206 + return cpm_ctrl_get(cpm_base, CPM_CLKGR) != 0;
12.207 +#endif
12.208 +}
12.209 +
12.210 +int jz4740_cpm_have_pll(void *cpm_base)
12.211 +{
12.212 + return cpm_ctrl_get(cpm_base, CPM_CPPCR) & CPM_CPPCR_PLLS;
12.213 +}
12.214 +
12.215 +void jz4740_cpm_start_clock(void *cpm_base)
12.216 +{
12.217 +#ifdef CONFIG_CPU_JZ4730
12.218 + cpm_start_ost(cpm_base);
12.219 + cpm_ctrl_set(cpm_base, CPM_MSCR, cpm_ctrl_get(cpm_base, CPM_MSCR) & ~CPM_MSCR_MSTP_OST);
12.220 +#else
12.221 + cpm_ctrl_set(cpm_base, CPM_CLKGR, cpm_ctrl_get(cpm_base, CPM_CLKGR) & ~CPM_CLKGR_TCU);
12.222 +#endif
12.223 +}
12.224 +
12.225 +// Peripheral clock control.
12.226 +
12.227 +void jz4740_cpm_start_lcd(void *cpm_base)
12.228 +{
12.229 +#ifndef CONFIG_CPU_JZ4730
12.230 + cpm_ctrl_set(cpm_base, CPM_CLKGR, cpm_ctrl_get(cpm_base, CPM_CLKGR) & ~CPM_CLKGR_LCD);
12.231 +#endif
12.232 +}
12.233 +
12.234 +void jz4740_cpm_stop_lcd(void *cpm_base)
12.235 +{
12.236 +#ifndef CONFIG_CPU_JZ4730
12.237 + cpm_ctrl_set(cpm_base, CPM_CLKGR, cpm_ctrl_get(cpm_base, CPM_CLKGR) | CPM_CLKGR_LCD);
12.238 +#endif
12.239 +}
12.240 +
12.241 +// Register access.
12.242 +
12.243 +uint32_t jz4740_cpm_ctrl_get(void *cpm_base, uint32_t reg)
12.244 +{
12.245 + return cpm_ctrl_get(cpm_base, reg);
12.246 +}
12.247 +
12.248 +void jz4740_cpm_ctrl_set(void *cpm_base, uint32_t reg, uint32_t value)
12.249 +{
12.250 + cpm_ctrl_set(cpm_base, reg, value);
12.251 +}
12.252 +
12.253 +/* Top-level initialisation. */
12.254 +
12.255 +void cpm_init()
12.256 +{
12.257 +#ifdef CONFIG_CPU_JZ4730
12.258 + cpm_ctrl_set((void *) CPM_BASE, CPM_MSCR, 0xffffffff);
12.259 +#else
12.260 + cpm_ctrl_set((void *) CPM_BASE, CPM_CLKGR, 0x7fff);
12.261 +#endif
12.262 +}
12.263 +
13.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
13.2 +++ b/stage2/cpm.h Tue Jul 11 00:03:30 2017 +0200
13.3 @@ -0,0 +1,77 @@
13.4 +#ifndef __CPM_H__
13.5 +#define __CPM_H__
13.6 +
13.7 +#include <stdint.h>
13.8 +
13.9 +/* Public functions. */
13.10 +
13.11 +int jz4740_init();
13.12 +
13.13 +int jz4740_cpm_have_pll(void *cpm_base);
13.14 +
13.15 +int jz4740_cpm_have_clock(void *cpm_base);
13.16 +void jz4740_cpm_start_clock(void *cpm_base);
13.17 +
13.18 +uint32_t jz4740_cpm_get_cpu_frequency(void *cpm_base);
13.19 +uint32_t jz4740_cpm_get_memory_frequency(void *cpm_base);
13.20 +
13.21 +void jz4740_cpm_set_lcd_frequencies(void *cpm_base, uint32_t pclk, uint8_t ratio);
13.22 +void jz4740_cpm_update_output_frequency(void *cpm_base);
13.23 +
13.24 +void jz4740_cpm_start_lcd(void *cpm_base);
13.25 +void jz4740_cpm_stop_lcd(void *cpm_base);
13.26 +
13.27 +uint32_t jz4740_cpm_ctrl_get(void *cpm_base, uint32_t reg);
13.28 +void jz4740_cpm_ctrl_set(void *cpm_base, uint32_t reg, uint32_t value);
13.29 +
13.30 +/* Register offsets. */
13.31 +
13.32 +#define CPM_CPCCR 0x00
13.33 +#define CPM_LCR 0x04
13.34 +#define CPM_RSR 0x08
13.35 +#define CPM_CPPCR 0x10
13.36 +
13.37 +#ifdef CONFIG_CPU_JZ4730
13.38 +
13.39 +/* Names used by the jz4730. */
13.40 +
13.41 +#define CPM_CFCR CPM_CPCCR
13.42 +#define CPM_LPCR CPM_LCR
13.43 +#define CPM_RSTR CPM_RSR
13.44 +#define CPM_PLCR1 CPM_CPPCR
13.45 +#define CPM_CFCR2 CPM_I2SCDR /* apparently used by the LCD */
13.46 +
13.47 +/* Registers used by the jz4730. */
13.48 +
13.49 +#define CPM_OCR 0x1c
13.50 +#define CPM_MSCR 0x20 /* different layout to CLKGR */
13.51 +#define CPM_WRER 0x28
13.52 +#define CPM_WFER 0x2c
13.53 +#define CPM_WER 0x30
13.54 +#define CPM_WSR 0x34
13.55 +#define CPM_GSR0 0x38
13.56 +#define CPM_GSR1 0x3c
13.57 +#define CPM_GSR2 0x40
13.58 +#define CPM_SPR 0x44
13.59 +#define CPM_GSR3 0x48
13.60 +
13.61 +#else
13.62 +
13.63 +/* Registers used by the jz4740. */
13.64 +
13.65 +#define CPM_CLKGR 0x20
13.66 +#define CPM_SCR 0x24
13.67 +#define CPM_HCR 0x30
13.68 +#define CPM_HWFCR 0x34
13.69 +#define CPM_HRCR 0x38
13.70 +#define CPM_HWCR 0x3c
13.71 +#define CPM_HWSR 0x40
13.72 +#define CPM_HSPR 0x44
13.73 +#define CPM_I2SCDR 0x60
13.74 +#define CPM_LPCDR 0x64
13.75 +#define CPM_MSCCDR 0x68
13.76 +#define CPM_UHCCDR 0x6C
13.77 +
13.78 +#endif
13.79 +
13.80 +#endif /* __CPM_H__ */
14.1 --- a/stage2/lcd.c Sun Jul 09 19:04:49 2017 +0200
14.2 +++ b/stage2/lcd.c Tue Jul 11 00:03:30 2017 +0200
14.3 @@ -24,6 +24,7 @@
14.4 #include "jzlcd.h"
14.5 #include "sdram.h"
14.6 #include "cpu.h"
14.7 +#include "cpm.h"
14.8 #include "board.h"
14.9
14.10 extern vidinfo_t panel_info;
14.11 @@ -262,76 +263,14 @@
14.12
14.13 /* LCD initialisation. */
14.14
14.15 -#ifdef CONFIG_CPU_JZ4730
14.16 -void jz4730_set_lcd_frequencies(uint32_t pclk, uint8_t ratio)
14.17 -{
14.18 - uint32_t val;
14.19 -
14.20 - val = __cpm_get_pllout() / pclk;
14.21 - REG_CPM_CFCR2 = val - 1;
14.22 - val = pclk * ratio;
14.23 -
14.24 - if (val > 150000000) {
14.25 - val = 150000000;
14.26 - }
14.27 -
14.28 - val = __cpm_get_pllout() / val;
14.29 - val--;
14.30 -
14.31 - if (val > 0xF)
14.32 - val = 0xF;
14.33 -
14.34 - __cpm_set_ldiv(val);
14.35 - REG_CPM_CPCCR = REG_CPM_CPCCR | CPM_CPCCR_CE; /* update divide */
14.36 -}
14.37 -#else
14.38 -void jz4740_set_lcd_frequencies(uint32_t pclk, uint8_t ratio)
14.39 -{
14.40 - uint32_t val;
14.41 - int pll_div;
14.42 -
14.43 - pll_div = REG_CPM_CPCCR & CPM_CPCCR_PCS; /* clock source,0:pllout/2 1: pllout */
14.44 - pll_div = pll_div ? 1 : 2;
14.45 - val = (__cpm_get_pllout() / pll_div) / pclk;
14.46 - val--;
14.47 -
14.48 - if ( val > 0x1ff ) {
14.49 - val = 0x1ff;
14.50 - }
14.51 -
14.52 - __cpm_set_pixdiv(val);
14.53 -
14.54 - val = pclk * ratio; /* LCDClock > 2.5*Pixclock */
14.55 -
14.56 - if ( val > 150000000 ) {
14.57 - val = 150000000;
14.58 - }
14.59 -
14.60 - val = (__cpm_get_pllout() / pll_div) / val;
14.61 - val--;
14.62 -
14.63 - if (val > 0x1f)
14.64 - val = 0x1f;
14.65 -
14.66 - __cpm_set_ldiv(val);
14.67 - REG_CPM_CPCCR = REG_CPM_CPCCR | CPM_CPCCR_CE; /* update divide */
14.68 -}
14.69 -#endif
14.70 -
14.71 void lcd_set_timing(vidinfo_t *vid)
14.72 {
14.73 uint32_t pclk = jz4740_lcd_get_pixel_clock(vid);
14.74
14.75 - __cpm_stop_lcd();
14.76 -
14.77 -#ifdef CONFIG_CPU_JZ4730
14.78 - jz4730_set_lcd_frequencies(pclk, 4);
14.79 -#else
14.80 - jz4740_set_lcd_frequencies(pclk, 3);
14.81 -#endif
14.82 -
14.83 - __cpm_start_lcd();
14.84 - udelay(1000);
14.85 + jz4740_cpm_stop_lcd((void *) CPM_BASE);
14.86 + jz4740_cpm_set_lcd_frequencies((void *) CPM_BASE, pclk, 3);
14.87 + jz4740_cpm_start_lcd((void *) CPM_BASE);
14.88 + udelay(1000);
14.89 }
14.90
14.91 static void lcd_display_pin_init()
14.92 @@ -374,7 +313,7 @@
14.93
14.94 fb_vaddr = (void *) (get_memory_size() - jz4740_lcd_get_total_size(vid));
14.95
14.96 - jz4740_lcd_ctrl_init((void *) LCD_BASE_KSEG1, fb_vaddr, vid);
14.97 + jz4740_lcd_ctrl_init((void *) LCD_BASE, fb_vaddr, vid);
14.98 flush_cache_all();
14.99 jz4740_lcd_hw_init(vid);
14.100 lcd_set_timing(vid);
15.1 --- a/stage2/lcd.h Sun Jul 09 19:04:49 2017 +0200
15.2 +++ b/stage2/lcd.h Tue Jul 11 00:03:30 2017 +0200
15.3 @@ -3,8 +3,6 @@
15.4
15.5 #include <stdint.h>
15.6
15.7 -#define LCD_BASE_KSEG1 0xB3050000
15.8 -
15.9 /* Initialisation functions. */
15.10
15.11 void lcd_init();
16.1 --- a/stage2/nanonote_gpm940b0.h Sun Jul 09 19:04:49 2017 +0200
16.2 +++ b/stage2/nanonote_gpm940b0.h Tue Jul 11 00:03:30 2017 +0200
16.3 @@ -55,7 +55,6 @@
16.4
16.5 static inline void __lcd_display_pin_init()
16.6 {
16.7 - __cpm_start_tcu();
16.8 __gpio_as_output(SPEN);
16.9 __gpio_as_output(SPCK);
16.10 __gpio_as_output(SPDA);