1.1 --- a/include/jz4740.h Sun Jul 09 01:47:02 2017 +0200
1.2 +++ b/include/jz4740.h Sun Jul 09 16:00:26 2017 +0200
1.3 @@ -2080,49 +2080,8 @@
1.4 /*************************************************************************
1.5 * LCD (LCD Controller)
1.6 *************************************************************************/
1.7 -#define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */
1.8 -#define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */
1.9 -#define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */
1.10 -#define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */
1.11 -#define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */
1.12 -#define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */
1.13 -#define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */
1.14 -#define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */
1.15 -#define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */
1.16 -#define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */
1.17 -#define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */
1.18 -#define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */
1.19 -#define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */
1.20 -#define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */
1.21 -#define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */
1.22 -#define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */
1.23 -#define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */
1.24 -#define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */
1.25 -#define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */
1.26 -#define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */
1.27 -#define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */
1.28 -
1.29 -#define REG_LCD_CFG REG32(LCD_CFG)
1.30 -#define REG_LCD_VSYNC REG32(LCD_VSYNC)
1.31 -#define REG_LCD_HSYNC REG32(LCD_HSYNC)
1.32 -#define REG_LCD_VAT REG32(LCD_VAT)
1.33 -#define REG_LCD_DAH REG32(LCD_DAH)
1.34 -#define REG_LCD_DAV REG32(LCD_DAV)
1.35 -#define REG_LCD_PS REG32(LCD_PS)
1.36 -#define REG_LCD_CLS REG32(LCD_CLS)
1.37 -#define REG_LCD_SPL REG32(LCD_SPL)
1.38 -#define REG_LCD_REV REG32(LCD_REV)
1.39 -#define REG_LCD_CTRL REG32(LCD_CTRL)
1.40 -#define REG_LCD_STATE REG32(LCD_STATE)
1.41 -#define REG_LCD_IID REG32(LCD_IID)
1.42 -#define REG_LCD_DA0 REG32(LCD_DA0)
1.43 -#define REG_LCD_SA0 REG32(LCD_SA0)
1.44 -#define REG_LCD_FID0 REG32(LCD_FID0)
1.45 -#define REG_LCD_CMD0 REG32(LCD_CMD0)
1.46 -#define REG_LCD_DA1 REG32(LCD_DA1)
1.47 -#define REG_LCD_SA1 REG32(LCD_SA1)
1.48 -#define REG_LCD_FID1 REG32(LCD_FID1)
1.49 -#define REG_LCD_CMD1 REG32(LCD_CMD1)
1.50 +
1.51 +/* Register definitions with absolute positioning have been removed. */
1.52
1.53 /* LCD Configure Register */
1.54 #define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */
2.1 --- a/stage2/jzlcd.c Sun Jul 09 01:47:02 2017 +0200
2.2 +++ b/stage2/jzlcd.c Sun Jul 09 16:00:26 2017 +0200
2.3 @@ -632,7 +632,7 @@
2.4
2.5 fb_vaddr = (void *) lcd_get_framebuffer(0, vid);
2.6
2.7 - jz_lcd_ctrl_init(0, fb_vaddr, vid);
2.8 + jz_lcd_ctrl_init((void *) LCD_BASE_KSEG1, fb_vaddr, vid);
2.9 flush_cache_all();
2.10 jz_lcd_hw_init(vid);
2.11 jz_lcd_timing_init(vid);
3.1 --- a/stage2/jzlcd.h Sun Jul 09 01:47:02 2017 +0200
3.2 +++ b/stage2/jzlcd.h Sun Jul 09 16:00:26 2017 +0200
3.3 @@ -136,6 +136,34 @@
3.4 #define DATA_NORMAL (0 << 17)
3.5 #define DATA_INVERSE (1 << 17)
3.6
3.7 +/* LCD register base. */
3.8 +
3.9 +#define LCD_BASE_KSEG1 0xB3050000
3.10 +
3.11 +/* Register offsets. */
3.12 +
3.13 +#define LCD_CFG 0x00 /* LCD Configure Register */
3.14 +#define LCD_VSYNC 0x04 /* Vertical Synchronize Register */
3.15 +#define LCD_HSYNC 0x08 /* Horizontal Synchronize Register */
3.16 +#define LCD_VAT 0x0c /* Virtual Area Setting Register */
3.17 +#define LCD_DAH 0x10 /* Display Area Horizontal Start/End Point */
3.18 +#define LCD_DAV 0x14 /* Display Area Vertical Start/End Point */
3.19 +#define LCD_PS 0x18 /* PS Signal Setting */
3.20 +#define LCD_CLS 0x1c /* CLS Signal Setting */
3.21 +#define LCD_SPL 0x20 /* SPL Signal Setting */
3.22 +#define LCD_REV 0x24 /* REV Signal Setting */
3.23 +#define LCD_CTRL 0x30 /* LCD Control Register */
3.24 +#define LCD_STATE 0x34 /* LCD Status Register */
3.25 +#define LCD_IID 0x38 /* Interrupt ID Register */
3.26 +#define LCD_DA0 0x40 /* Descriptor Address Register 0 */
3.27 +#define LCD_SA0 0x44 /* Source Address Register 0 */
3.28 +#define LCD_FID0 0x48 /* Frame ID Register 0 */
3.29 +#define LCD_CMD0 0x4c /* DMA Command Register 0 */
3.30 +#define LCD_DA1 0x50 /* Descriptor Address Register 1 */
3.31 +#define LCD_SA1 0x54 /* Source Address Register 1 */
3.32 +#define LCD_FID1 0x58 /* Frame ID Register 1 */
3.33 +#define LCD_CMD1 0x5c /* DMA Command Register 1 */
3.34 +
3.35 /* Palette buffer (LCD_CMDx.PAL). */
3.36
3.37 #define LCD_CMD_PAL (1 << 28)