1.1 --- a/include/sdram.h Tue Jun 23 23:04:17 2015 +0200
1.2 +++ b/include/sdram.h Tue Jun 23 23:05:00 2015 +0200
1.3 @@ -1,8 +1,11 @@
1.4 /*
1.5 * Common SDRAM configuration.
1.6 *
1.7 + * Copyright (C) 1996, 1997 by Ralf Baechle
1.8 + *
1.9 * Copyright (C) 2009 Qi Hardware Inc.
1.10 * Authors: Xiangfu Liu <xiangfu@openmobilefree.net>
1.11 + *
1.12 * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
1.13 *
1.14 * This program is free software: you can redistribute it and/or modify
1.15 @@ -67,6 +70,15 @@
1.16 #define CONFIG_SYS_ICACHE_SIZE 16384
1.17 #define CONFIG_SYS_CACHELINE_SIZE 32
1.18
1.19 +#define Index_Invalidate_I 0x00
1.20 +#define Index_Writeback_Inv_D 0x01
1.21 +#define Index_Store_Tag_I 0x08
1.22 +#define Index_Store_Tag_D 0x09
1.23 +#define Hit_Writeback_Inv_D 0x15
1.24 +
1.25 +#define CONFIG_CM_UNCACHED 2
1.26 +#define CONFIG_CM_CACHABLE_NONCOHERENT 3
1.27 +
1.28 /*
1.29 * Memory configuration
1.30 */
2.1 --- a/stage2/cpu.c Tue Jun 23 23:04:17 2015 +0200
2.2 +++ b/stage2/cpu.c Tue Jun 23 23:05:00 2015 +0200
2.3 @@ -24,9 +24,6 @@
2.4 #include "xburst_types.h"
2.5 #include "sdram.h"
2.6
2.7 -#define Index_Store_Tag_I 0x08
2.8 -#define Index_Writeback_Inv_D 0x15
2.9 -
2.10 void flush_icache_all(void)
2.11 {
2.12 u32 addr, t = 0;
2.13 @@ -78,3 +75,14 @@
2.14 flush_dcache_all();
2.15 flush_icache_all();
2.16 }
2.17 +
2.18 +void enable_interrupts(void)
2.19 +{
2.20 + asm volatile(
2.21 + "mfc0 $t3, $12\n" /* CP0_STATUS */
2.22 + "nop\n"
2.23 + "li $t4, 0x00000001\n" /* IE = enable interrupts */
2.24 + "or $t3, $t3, $t4\n"
2.25 + "mtc0 $t3, $12\n"
2.26 + "nop\n");
2.27 +}
3.1 --- a/stage2/cpu.h Tue Jun 23 23:04:17 2015 +0200
3.2 +++ b/stage2/cpu.h Tue Jun 23 23:05:00 2015 +0200
3.3 @@ -2,5 +2,6 @@
3.4 #define __CPU_H__
3.5
3.6 void flush_cache_all(void);
3.7 +void enable_interrupts(void);
3.8
3.9 #endif /* __CPU_H__ */