NanoPayload

Changeset

228:58cf8c659804
2017-07-09 Paul Boddie raw files shortlog changelog graph Removed superfluous definitions.
include/jz4730.h (file) include/jz4740.h (file)
     1.1 --- a/include/jz4730.h	Sun Jul 09 17:14:00 2017 +0200
     1.2 +++ b/include/jz4730.h	Sun Jul 09 18:31:15 2017 +0200
     1.3 @@ -4,7 +4,7 @@
     1.4   * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
     1.5   * Copyright (C) 2009 Qi Hardware Inc.
     1.6   * Author: Xiangfu Liu <xiangfu@sharism.cc>
     1.7 - * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
     1.8 + * Copyright (C) 2015, 2017 Paul Boddie <paul@boddie.org.uk>
     1.9   *
    1.10   * This program is free software; you can redistribute it and/or
    1.11   * modify it under the terms of the GNU General Public License as
    1.12 @@ -2044,49 +2044,8 @@
    1.13  /*************************************************************************
    1.14   * LCD 
    1.15   *************************************************************************/
    1.16 -#define LCD_CFG		(LCD_BASE + 0x00)
    1.17 -#define LCD_VSYNC	(LCD_BASE + 0x04)
    1.18 -#define LCD_HSYNC	(LCD_BASE + 0x08)
    1.19 -#define LCD_VAT		(LCD_BASE + 0x0c)
    1.20 -#define LCD_DAH		(LCD_BASE + 0x10)
    1.21 -#define LCD_DAV		(LCD_BASE + 0x14)
    1.22 -#define LCD_PS		(LCD_BASE + 0x18)
    1.23 -#define LCD_CLS		(LCD_BASE + 0x1c)
    1.24 -#define LCD_SPL		(LCD_BASE + 0x20)
    1.25 -#define LCD_REV		(LCD_BASE + 0x24)
    1.26 -#define LCD_CTRL	(LCD_BASE + 0x30)
    1.27 -#define LCD_STATE	(LCD_BASE + 0x34)
    1.28 -#define LCD_IID		(LCD_BASE + 0x38)
    1.29 -#define LCD_DA0		(LCD_BASE + 0x40)
    1.30 -#define LCD_SA0		(LCD_BASE + 0x44)
    1.31 -#define LCD_FID0	(LCD_BASE + 0x48)
    1.32 -#define LCD_CMD0	(LCD_BASE + 0x4c)
    1.33 -#define LCD_DA1		(LCD_BASE + 0x50)
    1.34 -#define LCD_SA1		(LCD_BASE + 0x54)
    1.35 -#define LCD_FID1	(LCD_BASE + 0x58)
    1.36 -#define LCD_CMD1	(LCD_BASE + 0x5c)
    1.37 -
    1.38 -#define REG_LCD_CFG	REG32(LCD_CFG)
    1.39 -#define REG_LCD_VSYNC	REG32(LCD_VSYNC)
    1.40 -#define REG_LCD_HSYNC	REG32(LCD_HSYNC)
    1.41 -#define REG_LCD_VAT	REG32(LCD_VAT)
    1.42 -#define REG_LCD_DAH	REG32(LCD_DAH)
    1.43 -#define REG_LCD_DAV	REG32(LCD_DAV)
    1.44 -#define REG_LCD_PS	REG32(LCD_PS)
    1.45 -#define REG_LCD_CLS	REG32(LCD_CLS)
    1.46 -#define REG_LCD_SPL	REG32(LCD_SPL)
    1.47 -#define REG_LCD_REV	REG32(LCD_REV)
    1.48 -#define REG_LCD_CTRL	REG32(LCD_CTRL)
    1.49 -#define REG_LCD_STATE	REG32(LCD_STATE)
    1.50 -#define REG_LCD_IID	REG32(LCD_IID)
    1.51 -#define REG_LCD_DA0	REG32(LCD_DA0)
    1.52 -#define REG_LCD_SA0	REG32(LCD_SA0)
    1.53 -#define REG_LCD_FID0	REG32(LCD_FID0)
    1.54 -#define REG_LCD_CMD0	REG32(LCD_CMD0)
    1.55 -#define REG_LCD_DA1	REG32(LCD_DA1)
    1.56 -#define REG_LCD_SA1	REG32(LCD_SA1)
    1.57 -#define REG_LCD_FID1	REG32(LCD_FID1)
    1.58 -#define REG_LCD_CMD1	REG32(LCD_CMD1)
    1.59 +
    1.60 +/* Register definitions with absolute positioning have been removed. */
    1.61  
    1.62  #define LCD_CFG_PDW_BIT		4
    1.63  #define LCD_CFG_PDW_MASK	(0x03 << LCD_DEV_PDW_BIT)
    1.64 @@ -4508,215 +4467,7 @@
    1.65   * LCD
    1.66   ***************************************************************************/
    1.67  
    1.68 -#define __lcd_set_dis()			( REG_LCD_CTRL |= LCD_CTRL_DIS )
    1.69 -#define __lcd_clr_dis()			( REG_LCD_CTRL &= ~LCD_CTRL_DIS )
    1.70 -
    1.71 -#define __lcd_set_ena()			( REG_LCD_CTRL |= LCD_CTRL_ENA )
    1.72 -#define __lcd_clr_ena()			( REG_LCD_CTRL &= ~LCD_CTRL_ENA )
    1.73 -
    1.74 -/* n=1,2,4,8,16 */
    1.75 -#define __lcd_set_bpp(n) \
    1.76 -  ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n )
    1.77 -
    1.78 -/* n=4,8,16 */
    1.79 -#define __lcd_set_burst_length(n) 		\
    1.80 -do {						\
    1.81 -	REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK;	\
    1.82 -	REG_LCD_CTRL |= LCD_CTRL_BST_n##;	\
    1.83 -} while (0)
    1.84 -
    1.85 -#define __lcd_select_rgb565()		( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 )
    1.86 -#define __lcd_select_rgb555()		( REG_LCD_CTRL |= LCD_CTRL_RGB555 )
    1.87 -
    1.88 -#define __lcd_set_ofup()		( REG_LCD_CTRL |= LCD_CTRL_OFUP )
    1.89 -#define __lcd_clr_ofup()		( REG_LCD_CTRL &= ~LCD_CTRL_OFUP )
    1.90 -
    1.91 -/* n=2,4,16 */
    1.92 -#define __lcd_set_stn_frc(n) 			\
    1.93 -do {						\
    1.94 -	REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK;	\
    1.95 -	REG_LCD_CTRL |= LCD_CTRL_FRC_n##;	\
    1.96 -} while (0)
    1.97 -
    1.98 -
    1.99 -#define __lcd_pixel_endian_little()	( REG_LCD_CTRL |= LCD_CTRL_PEDN )
   1.100 -#define __lcd_pixel_endian_big()	( REG_LCD_CTRL &= ~LCD_CTRL_PEDN )
   1.101 -
   1.102 -#define __lcd_reverse_byte_endian()	( REG_LCD_CTRL |= LCD_CTRL_BEDN )
   1.103 -#define __lcd_normal_byte_endian()	( REG_LCD_CTRL &= ~LCD_CTRL_BEDN )
   1.104 -
   1.105 -#define __lcd_enable_eof_intr()		( REG_LCD_CTRL |= LCD_CTRL_EOFM )
   1.106 -#define __lcd_disable_eof_intr()	( REG_LCD_CTRL &= ~LCD_CTRL_EOFM )
   1.107 -
   1.108 -#define __lcd_enable_sof_intr()		( REG_LCD_CTRL |= LCD_CTRL_SOFM )
   1.109 -#define __lcd_disable_sof_intr()	( REG_LCD_CTRL &= ~LCD_CTRL_SOFM )
   1.110 -
   1.111 -#define __lcd_enable_ofu_intr()		( REG_LCD_CTRL |= LCD_CTRL_OFUM )
   1.112 -#define __lcd_disable_ofu_intr()	( REG_LCD_CTRL &= ~LCD_CTRL_OFUM )
   1.113 -
   1.114 -#define __lcd_enable_ifu0_intr()	( REG_LCD_CTRL |= LCD_CTRL_IFUM0 )
   1.115 -#define __lcd_disable_ifu0_intr()	( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 )
   1.116 -
   1.117 -#define __lcd_enable_ifu1_intr()	( REG_LCD_CTRL |= LCD_CTRL_IFUM1 )
   1.118 -#define __lcd_disable_ifu1_intr()	( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 )
   1.119 -
   1.120 -#define __lcd_enable_ldd_intr()		( REG_LCD_CTRL |= LCD_CTRL_LDDM )
   1.121 -#define __lcd_disable_ldd_intr()	( REG_LCD_CTRL &= ~LCD_CTRL_LDDM )
   1.122 -
   1.123 -#define __lcd_enable_qd_intr()		( REG_LCD_CTRL |= LCD_CTRL_QDM )
   1.124 -#define __lcd_disable_qd_intr()		( REG_LCD_CTRL &= ~LCD_CTRL_QDM )
   1.125 -
   1.126 -
   1.127 -/* LCD status register indication */
   1.128 -
   1.129 -#define __lcd_quick_disable_done()	( REG_LCD_STATE & LCD_STATE_QD )
   1.130 -#define __lcd_disable_done()		( REG_LCD_STATE & LCD_STATE_LDD )
   1.131 -#define __lcd_infifo0_underrun()	( REG_LCD_STATE & LCD_STATE_IFU0 )
   1.132 -#define __lcd_infifo1_underrun()	( REG_LCD_STATE & LCD_STATE_IFU1 )
   1.133 -#define __lcd_outfifo_underrun()	( REG_LCD_STATE & LCD_STATE_OFU )
   1.134 -#define __lcd_start_of_frame()		( REG_LCD_STATE & LCD_STATE_SOF )
   1.135 -#define __lcd_end_of_frame()		( REG_LCD_STATE & LCD_STATE_EOF )
   1.136 -
   1.137 -#define __lcd_clr_outfifounderrun()	( REG_LCD_STATE &= ~LCD_STATE_OFU )
   1.138 -#define __lcd_clr_sof()			( REG_LCD_STATE &= ~LCD_STATE_SOF )
   1.139 -#define __lcd_clr_eof()			( REG_LCD_STATE &= ~LCD_STATE_EOF )
   1.140 -
   1.141 -#define __lcd_panel_white()		( REG_LCD_DEV |= LCD_DEV_WHITE )
   1.142 -#define __lcd_panel_black()		( REG_LCD_DEV &= ~LCD_DEV_WHITE )
   1.143 -
   1.144 -/* n=1,2,4,8 for single mono-STN 
   1.145 - * n=4,8 for dual mono-STN
   1.146 - */
   1.147 -#define __lcd_set_panel_datawidth(n) 		\
   1.148 -do { 						\
   1.149 -	REG_LCD_DEV &= ~LCD_DEV_PDW_MASK; 	\
   1.150 -	REG_LCD_DEV |= LCD_DEV_PDW_n##;		\
   1.151 -} while (0)
   1.152 -
   1.153 -/* m=LCD_DEV_MODE_GENERUIC_TFT_xxx */
   1.154 -#define __lcd_set_panel_mode(m) 		\
   1.155 -do {						\
   1.156 -	REG_LCD_DEV &= ~LCD_DEV_MODE_MASK;	\
   1.157 -	REG_LCD_DEV |= (m);			\
   1.158 -} while(0)
   1.159 -
   1.160 -/* n = 0-255 */
   1.161 -#define __lcd_disable_ac_bias()		( REG_LCD_IO = 0xff )
   1.162 -#define __lcd_set_ac_bias(n) 			\
   1.163 -do {						\
   1.164 -	REG_LCD_IO &= ~LCD_IO_ACB_MASK;		\
   1.165 -	REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT);	\
   1.166 -} while(0)
   1.167 -
   1.168 -#define __lcd_io_set_dir()		( REG_LCD_IO |= LCD_IO_DIR )
   1.169 -#define __lcd_io_clr_dir()		( REG_LCD_IO &= ~LCD_IO_DIR )
   1.170 -
   1.171 -#define __lcd_io_set_dep()		( REG_LCD_IO |= LCD_IO_DEP )
   1.172 -#define __lcd_io_clr_dep()		( REG_LCD_IO &= ~LCD_IO_DEP )
   1.173 -
   1.174 -#define __lcd_io_set_vsp()		( REG_LCD_IO |= LCD_IO_VSP )
   1.175 -#define __lcd_io_clr_vsp()		( REG_LCD_IO &= ~LCD_IO_VSP )
   1.176 -
   1.177 -#define __lcd_io_set_hsp()		( REG_LCD_IO |= LCD_IO_HSP )
   1.178 -#define __lcd_io_clr_hsp()		( REG_LCD_IO &= ~LCD_IO_HSP )
   1.179 -
   1.180 -#define __lcd_io_set_pcp()		( REG_LCD_IO |= LCD_IO_PCP )
   1.181 -#define __lcd_io_clr_pcp()		( REG_LCD_IO &= ~LCD_IO_PCP )
   1.182 -
   1.183 -#define __lcd_vsync_get_vps() \
   1.184 -  ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT )
   1.185 -
   1.186 -#define __lcd_vsync_get_vpe() \
   1.187 -  ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT )
   1.188 -#define __lcd_vsync_set_vpe(n) 				\
   1.189 -do {							\
   1.190 -	REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK;		\
   1.191 -	REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT;	\
   1.192 -} while (0)
   1.193 -
   1.194 -#define __lcd_hsync_get_hps() \
   1.195 -  ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT )
   1.196 -#define __lcd_hsync_set_hps(n) 				\
   1.197 -do {							\
   1.198 -	REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK;		\
   1.199 -	REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT;	\
   1.200 -} while (0)
   1.201 -
   1.202 -#define __lcd_hsync_get_hpe() \
   1.203 -  ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT )
   1.204 -#define __lcd_hsync_set_hpe(n) 				\
   1.205 -do {							\
   1.206 -	REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK;		\
   1.207 -	REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT;	\
   1.208 -} while (0)
   1.209 -
   1.210 -#define __lcd_vat_get_ht() \
   1.211 -  ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT )
   1.212 -#define __lcd_vat_set_ht(n) 				\
   1.213 -do {							\
   1.214 -	REG_LCD_VAT &= ~LCD_VAT_HT_MASK;		\
   1.215 -	REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT;		\
   1.216 -} while (0)
   1.217 -
   1.218 -#define __lcd_vat_get_vt() \
   1.219 -  ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT )
   1.220 -#define __lcd_vat_set_vt(n) 				\
   1.221 -do {							\
   1.222 -	REG_LCD_VAT &= ~LCD_VAT_VT_MASK;		\
   1.223 -	REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT;		\
   1.224 -} while (0)
   1.225 -
   1.226 -#define __lcd_dah_get_hds() \
   1.227 -  ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT )
   1.228 -#define __lcd_dah_set_hds(n) 				\
   1.229 -do {							\
   1.230 -	REG_LCD_DAH &= ~LCD_DAH_HDS_MASK;		\
   1.231 -	REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT;		\
   1.232 -} while (0)
   1.233 -
   1.234 -#define __lcd_dah_get_hde() \
   1.235 -  ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT )
   1.236 -#define __lcd_dah_set_hde(n) 				\
   1.237 -do {							\
   1.238 -	REG_LCD_DAH &= ~LCD_DAH_HDE_MASK;		\
   1.239 -	REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT;		\
   1.240 -} while (0)
   1.241 -
   1.242 -#define __lcd_dav_get_vds() \
   1.243 -  ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT )
   1.244 -#define __lcd_dav_set_vds(n) 				\
   1.245 -do {							\
   1.246 -	REG_LCD_DAV &= ~LCD_DAV_VDS_MASK;		\
   1.247 -	REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT;		\
   1.248 -} while (0)
   1.249 -
   1.250 -#define __lcd_dav_get_vde() \
   1.251 -  ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT )
   1.252 -#define __lcd_dav_set_vde(n) 				\
   1.253 -do {							\
   1.254 -	REG_LCD_DAV &= ~LCD_DAV_VDE_MASK;		\
   1.255 -	REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT;		\
   1.256 -} while (0)
   1.257 -
   1.258 -#define __lcd_cmd0_set_sofint()		( REG_LCD_CMD0 |= LCD_CMD_SOFINT )
   1.259 -#define __lcd_cmd0_clr_sofint()		( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT )
   1.260 -#define __lcd_cmd1_set_sofint()		( REG_LCD_CMD1 |= LCD_CMD_SOFINT )
   1.261 -#define __lcd_cmd1_clr_sofint()		( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT )
   1.262 -
   1.263 -#define __lcd_cmd0_set_eofint()		( REG_LCD_CMD0 |= LCD_CMD_EOFINT )
   1.264 -#define __lcd_cmd0_clr_eofint()		( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT )
   1.265 -#define __lcd_cmd1_set_eofint()		( REG_LCD_CMD1 |= LCD_CMD_EOFINT )
   1.266 -#define __lcd_cmd1_clr_eofint()		( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT )
   1.267 -
   1.268 -#define __lcd_cmd0_set_pal()		( REG_LCD_CMD0 |= LCD_CMD_PAL )
   1.269 -#define __lcd_cmd0_clr_pal()		( REG_LCD_CMD0 &= ~LCD_CMD_PAL )
   1.270 -
   1.271 -#define __lcd_cmd0_get_len() \
   1.272 -  ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
   1.273 -#define __lcd_cmd1_get_len() \
   1.274 -  ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
   1.275 -
   1.276 -
   1.277 +/* Register operations using absolute positioning have been removed. */
   1.278  
   1.279  /***************************************************************************
   1.280   * DES
     2.1 --- a/include/jz4740.h	Sun Jul 09 17:14:00 2017 +0200
     2.2 +++ b/include/jz4740.h	Sun Jul 09 18:31:15 2017 +0200
     2.3 @@ -177,6 +177,9 @@
     2.4  /*************************************************************************
     2.5   * CPM (Clock reset and Power control Management)
     2.6   *************************************************************************/
     2.7 +
     2.8 +/* Register definitions with absolute positioning have been removed. */
     2.9 +
    2.10  #define CPM_CPCCR	(CPM_BASE+0x00)
    2.11  #define CPM_CPPCR	(CPM_BASE+0x10)
    2.12  #define CPM_I2SCDR	(CPM_BASE+0x60)
    2.13 @@ -4327,216 +4330,8 @@
    2.14  /***************************************************************************
    2.15   * LCD
    2.16   ***************************************************************************/
    2.17 -#define __lcd_as_smart_lcd() 		( REG_LCD_CFG |= (1<<LCD_CFG_LCDPIN_BIT) )
    2.18 -#define __lcd_as_general_lcd() 		( REG_LCD_CFG &= ~(1<<LCD_CFG_LCDPIN_BIT) )
    2.19 -
    2.20 -#define __lcd_set_dis()			( REG_LCD_CTRL |= LCD_CTRL_DIS )
    2.21 -#define __lcd_clr_dis()			( REG_LCD_CTRL &= ~LCD_CTRL_DIS )
    2.22 -
    2.23 -#define __lcd_set_ena()			( REG_LCD_CTRL |= LCD_CTRL_ENA )
    2.24 -#define __lcd_clr_ena()			( REG_LCD_CTRL &= ~LCD_CTRL_ENA )
    2.25 -
    2.26 -/* n=1,2,4,8,16 */
    2.27 -#define __lcd_set_bpp(n) \
    2.28 -  ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n )
    2.29 -
    2.30 -/* n=4,8,16 */
    2.31 -#define __lcd_set_burst_length(n) 		\
    2.32 -do {						\
    2.33 -	REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK;	\
    2.34 -	REG_LCD_CTRL |= LCD_CTRL_BST_n##;	\
    2.35 -} while (0)
    2.36 -
    2.37 -#define __lcd_select_rgb565()		( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 )
    2.38 -#define __lcd_select_rgb555()		( REG_LCD_CTRL |= LCD_CTRL_RGB555 )
    2.39 -
    2.40 -#define __lcd_set_ofup()		( REG_LCD_CTRL |= LCD_CTRL_OFUP )
    2.41 -#define __lcd_clr_ofup()		( REG_LCD_CTRL &= ~LCD_CTRL_OFUP )
    2.42 -
    2.43 -/* n=2,4,16 */
    2.44 -#define __lcd_set_stn_frc(n) 			\
    2.45 -do {						\
    2.46 -	REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK;	\
    2.47 -	REG_LCD_CTRL |= LCD_CTRL_FRC_n##;	\
    2.48 -} while (0)
    2.49 -
    2.50 -
    2.51 -#define __lcd_pixel_endian_little()	( REG_LCD_CTRL |= LCD_CTRL_PEDN )
    2.52 -#define __lcd_pixel_endian_big()	( REG_LCD_CTRL &= ~LCD_CTRL_PEDN )
    2.53 -
    2.54 -#define __lcd_reverse_byte_endian()	( REG_LCD_CTRL |= LCD_CTRL_BEDN )
    2.55 -#define __lcd_normal_byte_endian()	( REG_LCD_CTRL &= ~LCD_CTRL_BEDN )
    2.56 -
    2.57 -#define __lcd_enable_eof_intr()		( REG_LCD_CTRL |= LCD_CTRL_EOFM )
    2.58 -#define __lcd_disable_eof_intr()	( REG_LCD_CTRL &= ~LCD_CTRL_EOFM )
    2.59 -
    2.60 -#define __lcd_enable_sof_intr()		( REG_LCD_CTRL |= LCD_CTRL_SOFM )
    2.61 -#define __lcd_disable_sof_intr()	( REG_LCD_CTRL &= ~LCD_CTRL_SOFM )
    2.62 -
    2.63 -#define __lcd_enable_ofu_intr()		( REG_LCD_CTRL |= LCD_CTRL_OFUM )
    2.64 -#define __lcd_disable_ofu_intr()	( REG_LCD_CTRL &= ~LCD_CTRL_OFUM )
    2.65 -
    2.66 -#define __lcd_enable_ifu0_intr()	( REG_LCD_CTRL |= LCD_CTRL_IFUM0 )
    2.67 -#define __lcd_disable_ifu0_intr()	( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 )
    2.68 -
    2.69 -#define __lcd_enable_ifu1_intr()	( REG_LCD_CTRL |= LCD_CTRL_IFUM1 )
    2.70 -#define __lcd_disable_ifu1_intr()	( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 )
    2.71 -
    2.72 -#define __lcd_enable_ldd_intr()		( REG_LCD_CTRL |= LCD_CTRL_LDDM )
    2.73 -#define __lcd_disable_ldd_intr()	( REG_LCD_CTRL &= ~LCD_CTRL_LDDM )
    2.74 -
    2.75 -#define __lcd_enable_qd_intr()		( REG_LCD_CTRL |= LCD_CTRL_QDM )
    2.76 -#define __lcd_disable_qd_intr()		( REG_LCD_CTRL &= ~LCD_CTRL_QDM )
    2.77 -
    2.78 -
    2.79 -/* LCD status register indication */
    2.80 -
    2.81 -#define __lcd_quick_disable_done()	( REG_LCD_STATE & LCD_STATE_QD )
    2.82 -#define __lcd_disable_done()		( REG_LCD_STATE & LCD_STATE_LDD )
    2.83 -#define __lcd_infifo0_underrun()	( REG_LCD_STATE & LCD_STATE_IFU0 )
    2.84 -#define __lcd_infifo1_underrun()	( REG_LCD_STATE & LCD_STATE_IFU1 )
    2.85 -#define __lcd_outfifo_underrun()	( REG_LCD_STATE & LCD_STATE_OFU )
    2.86 -#define __lcd_start_of_frame()		( REG_LCD_STATE & LCD_STATE_SOF )
    2.87 -#define __lcd_end_of_frame()		( REG_LCD_STATE & LCD_STATE_EOF )
    2.88 -
    2.89 -#define __lcd_clr_outfifounderrun()	( REG_LCD_STATE &= ~LCD_STATE_OFU )
    2.90 -#define __lcd_clr_sof()			( REG_LCD_STATE &= ~LCD_STATE_SOF )
    2.91 -#define __lcd_clr_eof()			( REG_LCD_STATE &= ~LCD_STATE_EOF )
    2.92 -
    2.93 -#define __lcd_panel_white()		( REG_LCD_CFG |= LCD_CFG_WHITE )
    2.94 -#define __lcd_panel_black()		( REG_LCD_CFG &= ~LCD_CFG_WHITE )
    2.95 -
    2.96 -/* n=1,2,4,8 for single mono-STN 
    2.97 - * n=4,8 for dual mono-STN
    2.98 - */
    2.99 -#define __lcd_set_panel_datawidth(n) 		\
   2.100 -do { 						\
   2.101 -	REG_LCD_CFG &= ~LCD_CFG_PDW_MASK; 	\
   2.102 -	REG_LCD_CFG |= LCD_CFG_PDW_n##;		\
   2.103 -} while (0)
   2.104 -
   2.105 -/* m=LCD_CFG_MODE_GENERUIC_TFT_xxx */
   2.106 -#define __lcd_set_panel_mode(m) 		\
   2.107 -do {						\
   2.108 -	REG_LCD_CFG &= ~LCD_CFG_MODE_MASK;	\
   2.109 -	REG_LCD_CFG |= (m);			\
   2.110 -} while(0)
   2.111 -
   2.112 -/* n = 0-255 */
   2.113 -#define __lcd_disable_ac_bias()		( REG_LCD_IO = 0xff )
   2.114 -#define __lcd_set_ac_bias(n) 			\
   2.115 -do {						\
   2.116 -	REG_LCD_IO &= ~LCD_IO_ACB_MASK;		\
   2.117 -	REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT);	\
   2.118 -} while(0)
   2.119 -
   2.120 -#define __lcd_io_set_dir()		( REG_LCD_IO |= LCD_IO_DIR )
   2.121 -#define __lcd_io_clr_dir()		( REG_LCD_IO &= ~LCD_IO_DIR )
   2.122 -
   2.123 -#define __lcd_io_set_dep()		( REG_LCD_IO |= LCD_IO_DEP )
   2.124 -#define __lcd_io_clr_dep()		( REG_LCD_IO &= ~LCD_IO_DEP )
   2.125 -
   2.126 -#define __lcd_io_set_vsp()		( REG_LCD_IO |= LCD_IO_VSP )
   2.127 -#define __lcd_io_clr_vsp()		( REG_LCD_IO &= ~LCD_IO_VSP )
   2.128 -
   2.129 -#define __lcd_io_set_hsp()		( REG_LCD_IO |= LCD_IO_HSP )
   2.130 -#define __lcd_io_clr_hsp()		( REG_LCD_IO &= ~LCD_IO_HSP )
   2.131 -
   2.132 -#define __lcd_io_set_pcp()		( REG_LCD_IO |= LCD_IO_PCP )
   2.133 -#define __lcd_io_clr_pcp()		( REG_LCD_IO &= ~LCD_IO_PCP )
   2.134 -
   2.135 -#define __lcd_vsync_get_vps() \
   2.136 -  ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT )
   2.137 -
   2.138 -#define __lcd_vsync_get_vpe() \
   2.139 -  ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT )
   2.140 -#define __lcd_vsync_set_vpe(n) 				\
   2.141 -do {							\
   2.142 -	REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK;		\
   2.143 -	REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT;	\
   2.144 -} while (0)
   2.145 -
   2.146 -#define __lcd_hsync_get_hps() \
   2.147 -  ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT )
   2.148 -#define __lcd_hsync_set_hps(n) 				\
   2.149 -do {							\
   2.150 -	REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK;		\
   2.151 -	REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT;	\
   2.152 -} while (0)
   2.153 -
   2.154 -#define __lcd_hsync_get_hpe() \
   2.155 -  ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT )
   2.156 -#define __lcd_hsync_set_hpe(n) 				\
   2.157 -do {							\
   2.158 -	REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK;		\
   2.159 -	REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT;	\
   2.160 -} while (0)
   2.161 -
   2.162 -#define __lcd_vat_get_ht() \
   2.163 -  ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT )
   2.164 -#define __lcd_vat_set_ht(n) 				\
   2.165 -do {							\
   2.166 -	REG_LCD_VAT &= ~LCD_VAT_HT_MASK;		\
   2.167 -	REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT;		\
   2.168 -} while (0)
   2.169 -
   2.170 -#define __lcd_vat_get_vt() \
   2.171 -  ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT )
   2.172 -#define __lcd_vat_set_vt(n) 				\
   2.173 -do {							\
   2.174 -	REG_LCD_VAT &= ~LCD_VAT_VT_MASK;		\
   2.175 -	REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT;		\
   2.176 -} while (0)
   2.177 -
   2.178 -#define __lcd_dah_get_hds() \
   2.179 -  ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT )
   2.180 -#define __lcd_dah_set_hds(n) 				\
   2.181 -do {							\
   2.182 -	REG_LCD_DAH &= ~LCD_DAH_HDS_MASK;		\
   2.183 -	REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT;		\
   2.184 -} while (0)
   2.185 -
   2.186 -#define __lcd_dah_get_hde() \
   2.187 -  ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT )
   2.188 -#define __lcd_dah_set_hde(n) 				\
   2.189 -do {							\
   2.190 -	REG_LCD_DAH &= ~LCD_DAH_HDE_MASK;		\
   2.191 -	REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT;		\
   2.192 -} while (0)
   2.193 -
   2.194 -#define __lcd_dav_get_vds() \
   2.195 -  ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT )
   2.196 -#define __lcd_dav_set_vds(n) 				\
   2.197 -do {							\
   2.198 -	REG_LCD_DAV &= ~LCD_DAV_VDS_MASK;		\
   2.199 -	REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT;		\
   2.200 -} while (0)
   2.201 -
   2.202 -#define __lcd_dav_get_vde() \
   2.203 -  ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT )
   2.204 -#define __lcd_dav_set_vde(n) 				\
   2.205 -do {							\
   2.206 -	REG_LCD_DAV &= ~LCD_DAV_VDE_MASK;		\
   2.207 -	REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT;		\
   2.208 -} while (0)
   2.209 -
   2.210 -#define __lcd_cmd0_set_sofint()		( REG_LCD_CMD0 |= LCD_CMD_SOFINT )
   2.211 -#define __lcd_cmd0_clr_sofint()		( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT )
   2.212 -#define __lcd_cmd1_set_sofint()		( REG_LCD_CMD1 |= LCD_CMD_SOFINT )
   2.213 -#define __lcd_cmd1_clr_sofint()		( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT )
   2.214 -
   2.215 -#define __lcd_cmd0_set_eofint()		( REG_LCD_CMD0 |= LCD_CMD_EOFINT )
   2.216 -#define __lcd_cmd0_clr_eofint()		( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT )
   2.217 -#define __lcd_cmd1_set_eofint()		( REG_LCD_CMD1 |= LCD_CMD_EOFINT )
   2.218 -#define __lcd_cmd1_clr_eofint()		( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT )
   2.219 -
   2.220 -#define __lcd_cmd0_set_pal()		( REG_LCD_CMD0 |= LCD_CMD_PAL )
   2.221 -#define __lcd_cmd0_clr_pal()		( REG_LCD_CMD0 &= ~LCD_CMD_PAL )
   2.222 -
   2.223 -#define __lcd_cmd0_get_len() \
   2.224 -  ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
   2.225 -#define __lcd_cmd1_get_len() \
   2.226 -  ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
   2.227 +
   2.228 +/* Register operations using absolute positioning have been removed. */
   2.229  
   2.230  /***************************************************************************
   2.231   * RTC ops