1.1 --- a/include/mips.h Sat May 14 21:40:59 2016 +0200
1.2 +++ b/include/mips.h Sat May 14 22:47:06 2016 +0200
1.3 @@ -16,6 +16,7 @@
1.4 #define CP0_TAGLO $28
1.5 #define CP0_TAGHI $29
1.6
1.7 +#define STATUS_CP0 0x10000000
1.8 #define STATUS_BEV 0x00400000
1.9 #define STATUS_IRQ 0x0000fc00
1.10 #define STATUS_UM 0x00000010
2.1 --- a/include/nanonote.h Sat May 14 21:40:59 2016 +0200
2.2 +++ b/include/nanonote.h Sat May 14 22:47:06 2016 +0200
2.3 @@ -53,4 +53,6 @@
2.4 #define SPDA (2 * 32 + 22) /* LCDSCL:Serial command clock input */
2.5 #define SPCK (2 * 32 + 23) /* LCDSDA:Serial command data input */
2.6
2.7 +#define GPIO_IRQ IRQ_GPIO3
2.8 +
2.9 #endif /* __NANONOTE_H__ */
3.1 --- a/stage2/board-nanonote.c Sat May 14 21:40:59 2016 +0200
3.2 +++ b/stage2/board-nanonote.c Sat May 14 22:47:06 2016 +0200
3.3 @@ -153,6 +153,45 @@
3.4 __tcu_clear_full_match_flag(TIMER_CHAN);
3.5 }
3.6
3.7 +/* GPIO interrupt activation. */
3.8 +
3.9 +void gpio_init_irq()
3.10 +{
3.11 +/*
3.12 + unsigned int i;
3.13 + for (i = 0; i < 7; i++) {
3.14 + __gpio_as_irq_rise_edge(GPIO_KEYIN_BASE + i);
3.15 + }
3.16 +*/
3.17 + __gpio_as_irq_low_level(GPIO_POWER);
3.18 + __intc_unmask_irq(GPIO_IRQ);
3.19 +}
3.20 +
3.21 +int gpio_have_irq(u8 gpio)
3.22 +{
3.23 + return (REG_GPIO_PXFLG(gpio / 32) & (1 << (gpio % 32)));
3.24 +}
3.25 +
3.26 +void gpio_clear(u8 gpio)
3.27 +{
3.28 + /* Clear interrupt status. */
3.29 +
3.30 + __gpio_ack_irq(gpio);
3.31 + __intc_ack_irq(GPIO_IRQ);
3.32 +}
3.33 +
3.34 +/* Miscellaneous interrupt administration. */
3.35 +
3.36 +void irq_clear()
3.37 +{
3.38 + u8 i;
3.39 +
3.40 + for (i = 0; i < 32; i++) {
3.41 + if (REG_INTC_IPR & (1 << i))
3.42 + __intc_ack_irq(i);
3.43 + }
3.44 +}
3.45 +
3.46 /* Board startup detection. */
3.47
3.48 int is_started()
4.1 --- a/stage2/cpu_op.S Sat May 14 21:40:59 2016 +0200
4.2 +++ b/stage2/cpu_op.S Sat May 14 22:47:06 2016 +0200
4.3 @@ -131,6 +131,8 @@
4.4 enter_task:
4.5 mfc0 $t3, CP0_STATUS
4.6 ori $t3, $t3, STATUS_EXL | STATUS_UM
4.7 + /* li $t4, STATUS_CP0 ** flag resides in the upper 16 bits, needed... */
4.8 + /* or $t3, $t3, $t4 ** for debugging by accessing CP0 in user mode */
4.9 mtc0 $t3, CP0_STATUS
4.10 eret
4.11 nop
5.1 --- a/stage2/init.h Sat May 14 21:40:59 2016 +0200
5.2 +++ b/stage2/init.h Sat May 14 22:47:06 2016 +0200
5.3 @@ -1,14 +1,31 @@
5.4 #ifndef __INIT_H__
5.5 #define __INIT_H__
5.6
5.7 +#include "xburst_types.h"
5.8 +
5.9 /* Initialisation functions. */
5.10
5.11 void gpio_init2();
5.12 void cpm_init();
5.13 void rtc_init();
5.14 +
5.15 +/* Timer. */
5.16 +
5.17 void timer_init();
5.18 void timer_init_irq();
5.19 void timer_clear();
5.20 +
5.21 +/* GPIO. */
5.22 +
5.23 +void gpio_init_irq();
5.24 +int gpio_have_irq(u8);
5.25 +void gpio_clear(u8);
5.26 +
5.27 +/* General. */
5.28 +void irq_clear();
5.29 +
5.30 +/* Test for initialisation. */
5.31 +
5.32 int is_started();
5.33
5.34 #endif /* __INIT_H__ */
6.1 --- a/stage2/irq.c Sat May 14 21:40:59 2016 +0200
6.2 +++ b/stage2/irq.c Sat May 14 22:47:06 2016 +0200
6.3 @@ -32,31 +32,40 @@
6.4 {
6.5 handle_error_level();
6.6 timer_init_irq();
6.7 + gpio_init_irq();
6.8 init_interrupts();
6.9 }
6.10
6.11 void irq_handle()
6.12 {
6.13 - unsigned short i;
6.14 -
6.15 /* Check interrupt identity. */
6.16
6.17 if (REG_INTC_IPR & (1 << TIMER_CHAN_IRQ)) {
6.18
6.19 - /* Switch task. */
6.20 -
6.21 - switch_task();
6.22 -
6.23 /* Clear interrupt status. */
6.24
6.25 timer_clear();
6.26 + }
6.27 +
6.28 + /* GPIO interrupts. */
6.29 +
6.30 + if (REG_INTC_IPR & (1 << GPIO_IRQ)) {
6.31 +
6.32 + /* Check for the power button. */
6.33 +
6.34 + if (gpio_have_irq(GPIO_POWER)) {
6.35 +
6.36 + /* Switch task. */
6.37 +
6.38 + switch_task();
6.39 +
6.40 + /* Clear interrupt status. */
6.41 +
6.42 + gpio_clear(GPIO_POWER);
6.43 + }
6.44 + }
6.45
6.46 /* Handle other interrupts, anyway. */
6.47
6.48 - } else {
6.49 - for (i = 0; i < 32; i++) {
6.50 - if (REG_INTC_IPR & (1 << i))
6.51 - __intc_ack_irq(i);
6.52 - }
6.53 - }
6.54 + irq_clear();
6.55 }