3.1 --- a/stage2/entry.S Tue Jun 30 16:09:27 2015 +0200
3.2 +++ b/stage2/entry.S Thu Dec 03 23:24:48 2015 +0100
3.3 @@ -19,37 +19,34 @@
3.4
3.5 .text
3.6 .extern real_exception_handler
3.7 -.globl _tlb_entry
3.8 -.globl _cache_entry
3.9 -.globl _exc_entry
3.10 -.globl _irq_entry
3.11 -.globl _end_entries
3.12 .set noreorder
3.13
3.14 +.section .vectors
3.15 _tlb_entry:
3.16 lui $k0, %hi(real_exception_handler)
3.17 ori $k0, $k0, %lo(real_exception_handler)
3.18 jr $k0
3.19 nop
3.20
3.21 +.org 0x100
3.22 _cache_entry:
3.23 lui $k0, %hi(real_exception_handler)
3.24 ori $k0, $k0, %lo(real_exception_handler)
3.25 jr $k0
3.26 nop
3.27
3.28 +.org 0x180
3.29 _exc_entry:
3.30 lui $k0, %hi(real_exception_handler)
3.31 ori $k0, $k0, %lo(real_exception_handler)
3.32 jr $k0
3.33 nop
3.34
3.35 +.org 0x200
3.36 _irq_entry:
3.37 lui $k0, %hi(real_exception_handler)
3.38 ori $k0, $k0, %lo(real_exception_handler)
3.39 jr $k0
3.40 nop
3.41
3.42 -_end_entries:
3.43 -
3.44 .set reorder
4.1 --- a/stage2/head2.S Tue Jun 30 16:09:27 2015 +0200
4.2 +++ b/stage2/head2.S Thu Dec 03 23:24:48 2015 +0100
4.3 @@ -22,10 +22,6 @@
4.4
4.5 .text
4.6 .extern c_main
4.7 -.extern _tlb_entry
4.8 -.extern _exc_entry
4.9 -.extern _irq_entry
4.10 -.extern _end_entries
4.11 .globl _start
4.12 .set noreorder
4.13
4.14 @@ -39,61 +35,13 @@
4.15 lui $gp, %hi(_GLOBAL_OFFSET_TABLE_)
4.16 ori $gp, $gp, %lo(_GLOBAL_OFFSET_TABLE_)
4.17
4.18 - /* Copy TLB handling instructions. */
4.19 -
4.20 - la $t0, _tlb_entry /* start */
4.21 - li $t1, 0x80000000
4.22 - la $t2, _cache_entry /* end */
4.23 -_tlb_copy:
4.24 - lw $t3, 0($t0)
4.25 - addiu $t0, $t0, 4
4.26 - sw $t3, 0($t1)
4.27 - bne $t0, $t2, _tlb_copy
4.28 - addiu $t1, $t1, 4 /* executed in delay slot before branch */
4.29 -
4.30 - /* Copy cache handling instructions. */
4.31 -
4.32 - move $t0, $t2 /* start */
4.33 - li $t1, 0x80000100
4.34 - la $t2, _exc_entry /* end */
4.35 -_cache_copy:
4.36 - lw $t3, 0($t0)
4.37 - addiu $t0, $t0, 4
4.38 - sw $t3, 0($t1)
4.39 - bne $t0, $t2, _cache_copy
4.40 - addiu $t1, $t1, 4 /* executed in delay slot before branch */
4.41 -
4.42 - /* Copy exception handling instructions. */
4.43 -
4.44 - move $t0, $t2 /* start */
4.45 - li $t1, 0x80000180
4.46 - la $t2, _irq_entry /* end */
4.47 -_exc_copy:
4.48 - lw $t3, 0($t0)
4.49 - addiu $t0, $t0, 4
4.50 - sw $t3, 0($t1)
4.51 - bne $t0, $t2, _exc_copy
4.52 - addiu $t1, $t1, 4 /* executed in delay slot before branch */
4.53 -
4.54 - /* Copy IRQ handling instructions. */
4.55 -
4.56 - move $t0, $t2 /* start */
4.57 - li $t1, 0x80000200
4.58 - la $t2, _end_entries /* end */
4.59 -_irq_copy:
4.60 - lw $t3, 0($t0)
4.61 - addiu $t0, $t0, 4
4.62 - sw $t3, 0($t1)
4.63 - bne $t0, $t2, _irq_copy
4.64 - addiu $t1, $t1, 4 /* executed in delay slot before branch */
4.65 -
4.66 /* Initialise interrupts. */
4.67
4.68 mfc0 $t3, $12 /* CP0_STATUS */
4.69 nop
4.70 - li $t4, 0xffbf00e0 /* BEV = 0 (not bootloader vectors); IM = disable all */
4.71 - and $t3, $t3, $t4 /* ... KSU = 0 (kernel mode); ERL = 0; EXL = 0; IE = 0 */
4.72 - li $t4, 0x0000ff04 /* IM = enable IM7..IM0; ERL = 1 (set by default) */
4.73 + li $t4, 0xffbf00e4 /* BEV = 0 (not bootloader vectors); IM = disable all */
4.74 + and $t3, $t3, $t4 /* ... KSU = 0 (kernel mode); EXL = 0; IE = 0 */
4.75 + li $t4, 0x0000ff00 /* IM = enable IM7..IM0 */
4.76 or $t3, $t3, $t4
4.77 mtc0 $t3, $12
4.78 nop