1.1 --- a/include/jz4730_compat.h Tue Jun 30 16:10:40 2015 +0200
1.2 +++ b/include/jz4730_compat.h Tue Jun 30 19:38:56 2015 +0200
1.3 @@ -23,6 +23,7 @@
1.4 #define REG_CPM_CPCCR REG_CPM_CFCR
1.5 #define REG_CPM_CPPCR REG_CPM_PLCR1
1.6
1.7 +#define CPM_CPCCR_CE CPM_CFCR_UPE
1.8 #define CPM_CPCCR_CDIV_BIT CPM_CFCR_IFR_BIT
1.9 #define CPM_CPCCR_HDIV_BIT CPM_CFCR_SFR_BIT
1.10 #define CPM_CPCCR_PDIV_BIT CPM_CFCR_PFR_BIT
1.11 @@ -35,4 +36,6 @@
1.12 #define CPM_CPPCR_PLLST_BIT CPM_PLCR1_PLL1ST_BIT
1.13 #define CPM_CPPCR_PLLEN CPM_PLCR1_PLL1EN
1.14
1.15 +#define __cpm_set_ldiv __cpm_set_lcdclk_div
1.16 +
1.17 #endif /* __JZ4730_COMPAT_H__ */
2.1 --- a/stage2/jzlcd.c Tue Jun 30 16:10:40 2015 +0200
2.2 +++ b/stage2/jzlcd.c Tue Jun 30 19:38:56 2015 +0200
2.3 @@ -369,8 +369,6 @@
2.4 val--;
2.5 if ( val > 0xF )
2.6 val = 0xF;
2.7 - __cpm_set_lcdclk_div(val);
2.8 - REG_CPM_CFCR |= CPM_CFCR_UPE;
2.9 #else
2.10 pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
2.11 pll_div = pll_div ? 1 : 2 ;
2.12 @@ -390,9 +388,10 @@
2.13 if ( val > 0x1f ) {
2.14 val = 0x1f;
2.15 }
2.16 +#endif
2.17 __cpm_set_ldiv( val );
2.18 REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
2.19 -#endif
2.20 +
2.21 __cpm_start_lcd();
2.22 udelay(1000);
2.23