1.1 --- a/include/minipc.h Wed Jun 28 16:31:54 2017 +0200
1.2 +++ b/include/minipc.h Thu Jun 29 23:26:39 2017 +0200
1.3 @@ -3,7 +3,7 @@
1.4 *
1.5 * Copyright (C) 2009 Qi Hardware Inc.
1.6 * Authors: Xiangfu Liu <xiangfu@openmobilefree.net>
1.7 - * Copyright (C) 2015, 2016 Paul Boddie <paul@boddie.org.uk>
1.8 + * Copyright (C) 2015, 2016, 2017 Paul Boddie <paul@boddie.org.uk>
1.9 *
1.10 * This program is free software: you can redistribute it and/or modify
1.11 * it under the terms of the GNU General Public License as published by
1.12 @@ -30,8 +30,6 @@
1.13 #define GPIO_PWM0 94
1.14 #define GPIO_POWER 97
1.15
1.16 -#define GPIO_KEYIN_BASE 0 /* if jz_keypad.c is understood correctly */
1.17 -#define GPIO_KEYOUT_BASE (3 * 32 + 0)
1.18 #define GPIO_KEYIN_COUNT 8
1.19 #define GPIO_KEYOUT_COUNT 17
1.20
2.1 --- a/include/nanonote.h Wed Jun 28 16:31:54 2017 +0200
2.2 +++ b/include/nanonote.h Thu Jun 29 23:26:39 2017 +0200
2.3 @@ -3,7 +3,7 @@
2.4 *
2.5 * Copyright (C) 2009 Qi Hardware Inc.
2.6 * Authors: Xiangfu Liu <xiangfu@openmobilefree.net>
2.7 - * Copyright (C) 2015, 2016 Paul Boddie <paul@boddie.org.uk>
2.8 + * Copyright (C) 2015, 2016, 2017 Paul Boddie <paul@boddie.org.uk>
2.9 *
2.10 * This program is free software: you can redistribute it and/or modify
2.11 * it under the terms of the GNU General Public License as published by
2.12 @@ -38,11 +38,7 @@
2.13 #define GPIO_AUDIO_POP (1 * 32 + 29)
2.14 #define GPIO_COB_TEST (1 * 32 + 30)
2.15
2.16 -#define GPIO_KEYOUT_BASE (2 * 32 + 10)
2.17 -#define GPIO_KEYIN_BASE (3 * 32 + 18)
2.18 -#define GPIO_KEYIN_8 (3 * 32 + 26)
2.19 -
2.20 -#define GPIO_KEYIN_COUNT 7
2.21 +#define GPIO_KEYIN_COUNT 8
2.22 #define GPIO_KEYOUT_COUNT 8
2.23
2.24 #define GPIO_POWER (3 * 32 + 29)
3.1 --- a/stage2/Makefile Wed Jun 28 16:31:54 2017 +0200
3.2 +++ b/stage2/Makefile Thu Jun 29 23:26:39 2017 +0200
3.3 @@ -43,9 +43,9 @@
3.4
3.5 # Configure target-specific objects.
3.6
3.7 -NANONOTE_SRC = board-nanonote.c nanonote_gpm940b0.c
3.8 +NANONOTE_SRC = board-nanonote.c nanonote_gpm940b0.c nanonote_gpio.c
3.9 NANONOTE_OBJ = $(NANONOTE_SRC:.c=.o)
3.10 -MINIPC_SRC = board-minipc.c minipc_claa070vc01.c
3.11 +MINIPC_SRC = board-minipc.c minipc_claa070vc01.c minipc_gpio.c
3.12 MINIPC_OBJ = $(MINIPC_SRC:.c=.o)
3.13
3.14 ifdef MINIPC
4.1 --- a/stage2/board-nanonote.c Wed Jun 28 16:31:54 2017 +0200
4.2 +++ b/stage2/board-nanonote.c Thu Jun 29 23:26:39 2017 +0200
4.3 @@ -37,25 +37,10 @@
4.4
4.5 /* Initialise other pins. */
4.6
4.7 - unsigned int i;
4.8 -
4.9 - for (i = 0; i < GPIO_KEYIN_COUNT; i++){
4.10 - __gpio_as_input(GPIO_KEYIN_BASE + i);
4.11 - __gpio_enable_pull(GPIO_KEYIN_BASE + i);
4.12 - }
4.13 -
4.14 - for (i = 0; i < GPIO_KEYOUT_COUNT; i++) {
4.15 - __gpio_as_output(GPIO_KEYOUT_BASE + i);
4.16 - __gpio_clear_pin(GPIO_KEYOUT_BASE + i);
4.17 - }
4.18 -
4.19 /* Enable TP4, TP5 as UART0. */
4.20
4.21 __gpio_jtag_to_uart0();
4.22
4.23 - __gpio_as_input(GPIO_KEYIN_8);
4.24 - __gpio_enable_pull(GPIO_KEYIN_8);
4.25 -
4.26 __gpio_as_input(GPIO_POWER);
4.27 __gpio_enable_pull(GPIO_POWER);
4.28
5.1 --- a/stage2/board.h Wed Jun 28 16:31:54 2017 +0200
5.2 +++ b/stage2/board.h Thu Jun 29 23:26:39 2017 +0200
5.3 @@ -40,10 +40,12 @@
5.4 #ifdef CONFIG_CPU_JZ4730_MINIPC
5.5
5.6 #include "minipc.h"
5.7 +#include "minipc_gpio.h"
5.8
5.9 #else /* assume NanoNote */
5.10
5.11 #include "nanonote.h"
5.12 +#include "nanonote_gpio.h"
5.13
5.14 #endif /* CONFIG_CPU_JZ4730_MINIPC */
5.15
6.1 --- a/stage2/irq.c Wed Jun 28 16:31:54 2017 +0200
6.2 +++ b/stage2/irq.c Thu Jun 29 23:26:39 2017 +0200
6.3 @@ -32,7 +32,7 @@
6.4 {
6.5 handle_error_level();
6.6 timer_init_irq();
6.7 - gpio_init_irq();
6.8 + /* gpio_init_irq(); */
6.9 init_interrupts();
6.10 }
6.11
7.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
7.2 +++ b/stage2/minipc_gpio.c Thu Jun 29 23:26:39 2017 +0200
7.3 @@ -0,0 +1,37 @@
7.4 +/*
7.5 + * MiniPC GPIO details.
7.6 + *
7.7 + * Copyright (C) 2017 Paul Boddie <paul@boddie.org.uk>
7.8 + *
7.9 + * This program is free software; you can redistribute it and/or
7.10 + * modify it under the terms of the GNU General Public License as
7.11 + * published by the Free Software Foundation; either version 2 of
7.12 + * the License, or (at your option) any later version.
7.13 + *
7.14 + * This program is distributed in the hope that it will be useful,
7.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7.17 + * GNU General Public License for more details.
7.18 + *
7.19 + * You should have received a copy of the GNU General Public License
7.20 + * along with this program; if not, write to the Free Software
7.21 + * Foundation, Inc., 51 Franklin Street, Fifth Floor,
7.22 + * Boston, MA 02110-1301, USA
7.23 + */
7.24 +
7.25 +#include "minipc.h"
7.26 +#include <stdint.h>
7.27 +
7.28 +#define PIN(x) (3 * 32 + x)
7.29 +
7.30 +const uint8_t GPIO_KEYIN_ROW[GPIO_KEYIN_COUNT] = {
7.31 + 0, 1, 2, 3, 4, 5, 6, 7 /* if jz_keypad.c is understood correctly */
7.32 + };
7.33 +
7.34 +const uint8_t GPIO_KEYOUT_COL[GPIO_KEYOUT_COUNT] = {
7.35 + PIN(0), PIN(1), PIN(2), PIN(3), PIN(4), PIN(5), PIN(6), PIN(7),
7.36 + PIN(8), PIN(9), PIN(10), PIN(11), PIN(12), PIN(13), PIN(14), PIN(15),
7.37 + PIN(16)
7.38 + };
7.39 +
7.40 +#undef PIN
8.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
8.2 +++ b/stage2/minipc_gpio.h Thu Jun 29 23:26:39 2017 +0200
8.3 @@ -0,0 +1,34 @@
8.4 +/*
8.5 + * MiniPC GPIO declarations.
8.6 + *
8.7 + * Copyright (C) 2017 Paul Boddie <paul@boddie.org.uk>
8.8 + *
8.9 + * This program is free software: you can redistribute it and/or modify
8.10 + * it under the terms of the GNU General Public License as published by
8.11 + * the Free Software Foundation, either version 3 of the License, or
8.12 + * (at your option) any later version.
8.13 + *
8.14 + * This program is distributed in the hope that it will be useful,
8.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8.17 + * GNU General Public License for more details.
8.18 + *
8.19 + * You should have received a copy of the GNU General Public License
8.20 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
8.21 + */
8.22 +
8.23 +#ifndef __MINIPC_GPIO_H__
8.24 +#define __MINIPC_GPIO_H__
8.25 +
8.26 +#include "minipc.h"
8.27 +
8.28 +#ifndef __ASSEMBLER__
8.29 +
8.30 +#include <stdint.h>
8.31 +
8.32 +extern const uint8_t GPIO_KEYIN_ROW[GPIO_KEYIN_COUNT];
8.33 +extern const uint8_t GPIO_KEYOUT_COL[GPIO_KEYOUT_COUNT];
8.34 +
8.35 +#endif /* __ASSEMBLER__ */
8.36 +
8.37 +#endif /* __MINIPC_GPIO_H__ */
9.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
9.2 +++ b/stage2/nanonote_gpio.c Thu Jun 29 23:26:39 2017 +0200
9.3 @@ -0,0 +1,38 @@
9.4 +/*
9.5 + * Ben NanoNote GPIO details.
9.6 + *
9.7 + * Copyright (C) 2017 Paul Boddie <paul@boddie.org.uk>
9.8 + *
9.9 + * This program is free software; you can redistribute it and/or
9.10 + * modify it under the terms of the GNU General Public License as
9.11 + * published by the Free Software Foundation; either version 2 of
9.12 + * the License, or (at your option) any later version.
9.13 + *
9.14 + * This program is distributed in the hope that it will be useful,
9.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
9.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9.17 + * GNU General Public License for more details.
9.18 + *
9.19 + * You should have received a copy of the GNU General Public License
9.20 + * along with this program; if not, write to the Free Software
9.21 + * Foundation, Inc., 51 Franklin Street, Fifth Floor,
9.22 + * Boston, MA 02110-1301, USA
9.23 + */
9.24 +
9.25 +#include "nanonote.h"
9.26 +#include <stdint.h>
9.27 +
9.28 +#define PIN(x) (3 * 32 + 18 + x)
9.29 +
9.30 +const uint8_t GPIO_KEYIN_ROW[GPIO_KEYIN_COUNT] = {
9.31 + 0, 1, 2, 3, 4, 5, 6, 7
9.32 + };
9.33 +
9.34 +#undef PIN
9.35 +#define PIN(x) (2 * 32 + 10 + x)
9.36 +
9.37 +const uint8_t GPIO_KEYOUT_COL[GPIO_KEYOUT_COUNT] = {
9.38 + PIN(0), PIN(1), PIN(2), PIN(3), PIN(4), PIN(5), PIN(6), PIN(8),
9.39 + };
9.40 +
9.41 +#undef PIN
10.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
10.2 +++ b/stage2/nanonote_gpio.h Thu Jun 29 23:26:39 2017 +0200
10.3 @@ -0,0 +1,34 @@
10.4 +/*
10.5 + * Ben NanoNote GPIO declarations.
10.6 + *
10.7 + * Copyright (C) 2017 Paul Boddie <paul@boddie.org.uk>
10.8 + *
10.9 + * This program is free software: you can redistribute it and/or modify
10.10 + * it under the terms of the GNU General Public License as published by
10.11 + * the Free Software Foundation, either version 3 of the License, or
10.12 + * (at your option) any later version.
10.13 + *
10.14 + * This program is distributed in the hope that it will be useful,
10.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
10.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10.17 + * GNU General Public License for more details.
10.18 + *
10.19 + * You should have received a copy of the GNU General Public License
10.20 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
10.21 + */
10.22 +
10.23 +#ifndef __NANONOTE_GPIO_H__
10.24 +#define __NANONOTE_GPIO_H__
10.25 +
10.26 +#include "nanonote.h"
10.27 +
10.28 +#ifndef __ASSEMBLER__
10.29 +
10.30 +#include <stdint.h>
10.31 +
10.32 +extern const uint8_t GPIO_KEYIN_ROW[GPIO_KEYIN_COUNT];
10.33 +extern const uint8_t GPIO_KEYOUT_COL[GPIO_KEYOUT_COUNT];
10.34 +
10.35 +#endif /* __ASSEMBLER__ */
10.36 +
10.37 +#endif /* __NANONOTE_GPIO_H__ */
11.1 --- a/stage2/task_gpio.c Wed Jun 28 16:31:54 2017 +0200
11.2 +++ b/stage2/task_gpio.c Thu Jun 29 23:26:39 2017 +0200
11.3 @@ -41,14 +41,33 @@
11.4
11.5 void task_gpio_as_input(uint8_t pin)
11.6 {
11.7 + TASK_REG_GPIO_PXFUNC(pin / 32) = (1 << (pin % 32));
11.8 + TASK_REG_GPIO_PXSELC(pin / 32) = (1 << (pin % 32));
11.9 TASK_REG_GPIO_PXDIRC(pin / 32) = (1 << (pin % 32));
11.10 }
11.11
11.12 void task_gpio_as_output(uint8_t pin)
11.13 {
11.14 + TASK_REG_GPIO_PXFUNC(pin / 32) = (1 << (pin % 32));
11.15 + TASK_REG_GPIO_PXSELC(pin / 32) = (1 << (pin % 32));
11.16 TASK_REG_GPIO_PXDIRS(pin / 32) = (1 << (pin % 32));
11.17 }
11.18
11.19 +void task_gpio_enable_pull(uint8_t pin)
11.20 +{
11.21 + TASK_REG_GPIO_PXPEC(pin / 32) = (1 << (pin % 32));
11.22 +}
11.23 +
11.24 +void task_gpio_disable_pull(uint8_t pin)
11.25 +{
11.26 + TASK_REG_GPIO_PXPES(pin / 32) = (1 << (pin % 32));
11.27 +}
11.28 +
11.29 +inline int task_gpio_get_pin(uint8_t pin)
11.30 +{
11.31 + return TASK_REG_GPIO_PXPIN(pin / 32) & (1 << (pin % 32));
11.32 +}
11.33 +
11.34 inline void task_gpio_set_pin(uint8_t pin)
11.35 {
11.36 TASK_REG_GPIO_PXDATS(pin / 32) = (1 << (pin % 32));
11.37 @@ -59,7 +78,12 @@
11.38 TASK_REG_GPIO_PXDATC(pin / 32) = (1 << (pin % 32));
11.39 }
11.40
11.41 -inline int task_gpio_get_pin(uint8_t pin)
11.42 +inline void task_gpio_mask_irq(uint8_t pin)
11.43 {
11.44 - return TASK_REG_GPIO_PXPIN(pin / 32) & (1 << (pin % 32));
11.45 + TASK_REG_GPIO_PXIMS(pin / 32) = (1 << (pin % 32));
11.46 }
11.47 +
11.48 +inline void task_gpio_unmask_irq(uint8_t pin)
11.49 +{
11.50 + TASK_REG_GPIO_PXIMC(pin / 32) = (1 << (pin % 32));
11.51 +}
12.1 --- a/stage2/task_gpio.h Wed Jun 28 16:31:54 2017 +0200
12.2 +++ b/stage2/task_gpio.h Thu Jun 29 23:26:39 2017 +0200
12.3 @@ -9,19 +9,53 @@
12.4 #define GPIO_BASE_PHYSICAL (GPIO_BASE - KSEG1_BASE)
12.5
12.6 #define TASK_GPIO_PXPIN(n) (TASK_GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
12.7 +
12.8 #define TASK_GPIO_PXDAT(n) (TASK_GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
12.9 #define TASK_GPIO_PXDATS(n) (TASK_GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
12.10 #define TASK_GPIO_PXDATC(n) (TASK_GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
12.11
12.12 +#define TASK_GPIO_PXIM(n) (TASK_GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
12.13 +#define TASK_GPIO_PXIMS(n) (TASK_GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
12.14 +#define TASK_GPIO_PXIMC(n) (TASK_GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
12.15 +
12.16 +#define TASK_GPIO_PXPE(n) (TASK_GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */
12.17 +#define TASK_GPIO_PXPES(n) (TASK_GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */
12.18 +#define TASK_GPIO_PXPEC(n) (TASK_GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */
12.19 +
12.20 +#define TASK_GPIO_PXFUN(n) (TASK_GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
12.21 +#define TASK_GPIO_PXFUNS(n) (TASK_GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
12.22 +#define TASK_GPIO_PXFUNC(n) (TASK_GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
12.23 +
12.24 +#define TASK_GPIO_PXSEL(n) (TASK_GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
12.25 +#define TASK_GPIO_PXSELS(n) (TASK_GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
12.26 +#define TASK_GPIO_PXSELC(n) (TASK_GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
12.27 +
12.28 #define TASK_GPIO_PXDIR(n) (TASK_GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
12.29 #define TASK_GPIO_PXDIRS(n) (TASK_GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
12.30 #define TASK_GPIO_PXDIRC(n) (TASK_GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
12.31
12.32 #define TASK_REG_GPIO_PXPIN(n) REG32(TASK_GPIO_PXPIN((n)))
12.33 +
12.34 #define TASK_REG_GPIO_PXDAT(n) REG32(TASK_GPIO_PXDAT((n)))
12.35 #define TASK_REG_GPIO_PXDATS(n) REG32(TASK_GPIO_PXDATS((n)))
12.36 #define TASK_REG_GPIO_PXDATC(n) REG32(TASK_GPIO_PXDATC((n)))
12.37
12.38 +#define TASK_REG_GPIO_PXIM(n) REG32(TASK_GPIO_PXIM((n)))
12.39 +#define TASK_REG_GPIO_PXIMS(n) REG32(TASK_GPIO_PXIMS((n)))
12.40 +#define TASK_REG_GPIO_PXIMC(n) REG32(TASK_GPIO_PXIMC((n)))
12.41 +
12.42 +#define TASK_REG_GPIO_PXPE(n) REG32(TASK_GPIO_PXPE((n)))
12.43 +#define TASK_REG_GPIO_PXPES(n) REG32(TASK_GPIO_PXPES((n)))
12.44 +#define TASK_REG_GPIO_PXPEC(n) REG32(TASK_GPIO_PXPEC((n)))
12.45 +
12.46 +#define TASK_REG_GPIO_PXFUN(n) REG32(TASK_GPIO_PXFUN((n)))
12.47 +#define TASK_REG_GPIO_PXFUNS(n) REG32(TASK_GPIO_PXFUNS((n)))
12.48 +#define TASK_REG_GPIO_PXFUNC(n) REG32(TASK_GPIO_PXFUNC((n)))
12.49 +
12.50 +#define TASK_REG_GPIO_PXSEL(n) REG32(TASK_GPIO_PXSEL((n)))
12.51 +#define TASK_REG_GPIO_PXSELS(n) REG32(TASK_GPIO_PXSELS((n)))
12.52 +#define TASK_REG_GPIO_PXSELC(n) REG32(TASK_GPIO_PXSELC((n)))
12.53 +
12.54 #define TASK_REG_GPIO_PXDIR(n) REG32(TASK_GPIO_PXDIR((n)))
12.55 #define TASK_REG_GPIO_PXDIRS(n) REG32(TASK_GPIO_PXDIRS((n)))
12.56 #define TASK_REG_GPIO_PXDIRC(n) REG32(TASK_GPIO_PXDIRC((n)))
12.57 @@ -29,8 +63,15 @@
12.58 void task_gpio_init(uint8_t task);
12.59 void task_gpio_as_input(uint8_t pin);
12.60 void task_gpio_as_output(uint8_t pin);
12.61 +
12.62 +void task_gpio_enable_pull(uint8_t pin);
12.63 +void task_gpio_disable_pull(uint8_t pin);
12.64 +
12.65 +int task_gpio_get_pin(uint8_t pin);
12.66 void task_gpio_set_pin(uint8_t pin);
12.67 void task_gpio_clear_pin(uint8_t pin);
12.68 -int task_gpio_get_pin(uint8_t pin);
12.69 +
12.70 +void task_gpio_mask_irq(uint8_t pin);
12.71 +void task_gpio_unmask_irq(uint8_t pin);
12.72
12.73 #endif /* __TASK_GPIO_H__ */
13.1 --- a/stage2/tasks/keyscan.c Wed Jun 28 16:31:54 2017 +0200
13.2 +++ b/stage2/tasks/keyscan.c Thu Jun 29 23:26:39 2017 +0200
13.3 @@ -43,20 +43,27 @@
13.4
13.5 void init_keyscan()
13.6 {
13.7 - int column;
13.8 + uint8_t pin;
13.9
13.10 - for (column = 0; column < GPIO_KEYOUT_COUNT; column++)
13.11 + for (pin = 0; pin < GPIO_KEYIN_COUNT; pin++)
13.12 {
13.13 - task_gpio_set_pin(GPIO_KEYOUT_BASE + column);
13.14 + task_gpio_as_input(GPIO_KEYIN_ROW[pin]);
13.15 + task_gpio_enable_pull(GPIO_KEYIN_ROW[pin]);
13.16 }
13.17 +
13.18 + for (pin = 0; pin < GPIO_KEYOUT_COUNT; pin++)
13.19 + {
13.20 + task_gpio_as_input(GPIO_KEYOUT_COL[pin]);
13.21 + }
13.22 +
13.23 + task_gpio_as_input(GPIO_POWER);
13.24 }
13.25
13.26 /* Tasks. */
13.27
13.28 void keyscan(uint8_t task)
13.29 {
13.30 - int column, row;
13.31 - uint8_t value;
13.32 + uint8_t column, row, value;
13.33
13.34 init_keyscan();
13.35
13.36 @@ -66,21 +73,26 @@
13.37
13.38 for (column = 0; column < GPIO_KEYOUT_COUNT; column++)
13.39 {
13.40 - task_gpio_clear_pin(GPIO_KEYOUT_BASE + column);
13.41 + task_gpio_as_output(GPIO_KEYOUT_COL[column]);
13.42 +
13.43 + for (unsigned int delay = 0; delay < 1000; delay++)
13.44 + task_gpio_clear_pin(GPIO_KEYOUT_COL[column]);
13.45
13.46 value = 0;
13.47
13.48 for (row = 0; row < GPIO_KEYIN_COUNT; row++)
13.49 {
13.50 - value = (value << 1) | !task_gpio_get_pin(GPIO_KEYIN_BASE + row);
13.51 + value = (value << 1) | (task_gpio_get_pin(GPIO_KEYIN_ROW[row]) ? 0 : 1);
13.52 }
13.53
13.54 /* Perform an operation indicating the status. */
13.55
13.56 plot_value(column * 10, column * 10 + 10, 0, 10 * GPIO_KEYIN_COUNT, value);
13.57
13.58 - task_gpio_set_pin(GPIO_KEYOUT_BASE + column);
13.59 + task_gpio_as_input(GPIO_KEYOUT_COL[column]);
13.60 }
13.61 +
13.62 + plot_value(100, 110, 0, 80, task_gpio_get_pin(GPIO_POWER) ? 0xff : 0);
13.63 }
13.64 }
13.65