1.1 --- a/include/mips.h Wed Jun 28 01:04:22 2017 +0200
1.2 +++ b/include/mips.h Wed Jun 28 16:31:54 2017 +0200
1.3 @@ -1,20 +1,29 @@
1.4 #ifndef __MIPS_H__
1.5 #define __MIPS_H__
1.6
1.7 +#define KSEG0_BASE 0x80000000
1.8 +#define KSEG1_BASE 0xA0000000
1.9 +
1.10 #define CP0_INDEX $0
1.11 #define CP0_ENTRYLO0 $2
1.12 #define CP0_ENTRYLO1 $3
1.13 #define CP0_CONTEXT $4
1.14 #define CP0_PAGEMASK $5
1.15 #define CP0_WIRED $6
1.16 +#define CP0_COUNT $9
1.17 #define CP0_ENTRYHI $10
1.18 +#define CP0_COMPARE $11
1.19 #define CP0_STATUS $12
1.20 +#define CP0_INTCTL $12, 1
1.21 #define CP0_CAUSE $13
1.22 #define CP0_EPC $14
1.23 +#define CP0_EBASE $15, 1
1.24 #define CP0_CONFIG $16
1.25 #define CP0_WATCHLO $18
1.26 +#define CP0_DEBUG $23
1.27 #define CP0_TAGLO $28
1.28 #define CP0_TAGHI $29
1.29 +#define CP0_ERROREPC $30, 0
1.30
1.31 #define STATUS_CP0 0x10000000
1.32 #define STATUS_BEV 0x00400000
1.33 @@ -26,6 +35,12 @@
1.34
1.35 #define CAUSE_IV 0x00800000
1.36
1.37 +#define EBASE_MASK 0x3ffff000
1.38 +
1.39 +#define INTCTL_MASK 0x000003e0
1.40 +
1.41 +#define DEBUG_DM 0x40000000
1.42 +
1.43 #define TLB_CACHED 0x00000018
1.44 #define TLB_UNCACHED 0x00000010
1.45 #define TLB_DIRTY 0x00000004
1.46 @@ -37,4 +52,8 @@
1.47 #define TLB_ALL_READ (TLB_CACHED | TLB_VALID | TLB_GLOBAL)
1.48 #define TLB_ALL_WRITE (TLB_CACHED | TLB_DIRTY | TLB_VALID | TLB_GLOBAL)
1.49
1.50 +#define CONFIG_K0 0x00000007
1.51 +#define CONFIG_K0_UNCACHED 2
1.52 +#define CONFIG_K0_CACHABLE_NONCOHERENT 3
1.53 +
1.54 #endif /* __MIPS_H__ */
2.1 --- a/stage2/task_gpio.c Wed Jun 28 01:04:22 2017 +0200
2.2 +++ b/stage2/task_gpio.c Wed Jun 28 16:31:54 2017 +0200
2.3 @@ -30,7 +30,7 @@
2.4
2.5 /* Map the I/O region to the task. */
2.6
2.7 - for (virtual = TASK_GPIO_BASE, physical = GPIO_BASE;
2.8 + for (virtual = TASK_GPIO_BASE, physical = GPIO_BASE_PHYSICAL;
2.9 virtual < (uint32_t) TASK_GPIO_BASE + (uint32_t) GPIO_REGION_SIZE;
2.10 virtual += page_size(STAGE2_PAGESIZE), physical += page_size(STAGE2_PAGESIZE))
2.11 {
3.1 --- a/stage2/task_gpio.h Wed Jun 28 01:04:22 2017 +0200
3.2 +++ b/stage2/task_gpio.h Wed Jun 28 16:31:54 2017 +0200
3.3 @@ -6,6 +6,8 @@
3.4
3.5 /* Special task versions of GPIO operations. */
3.6
3.7 +#define GPIO_BASE_PHYSICAL (GPIO_BASE - KSEG1_BASE)
3.8 +
3.9 #define TASK_GPIO_PXPIN(n) (TASK_GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
3.10 #define TASK_GPIO_PXDAT(n) (TASK_GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
3.11 #define TASK_GPIO_PXDATS(n) (TASK_GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */