1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/include/jz4730.h Tue Jun 09 23:55:00 2015 +0200
1.3 @@ -0,0 +1,5186 @@
1.4 +/*
1.5 + * Include file for Ingenic Semiconductor's JZ4730 CPU.
1.6 + *
1.7 + * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
1.8 + * Copyright (C) 2009 Qi Hardware Inc.,
1.9 + * Author: Xiangfu Liu <xiangfu@sharism.cc>
1.10 + * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk>
1.11 + *
1.12 + * This program is free software; you can redistribute it and/or
1.13 + * modify it under the terms of the GNU General Public License as
1.14 + * published by the Free Software Foundation; either version 2 of
1.15 + * the License, or (at your option) any later version.
1.16 + *
1.17 + * This program is distributed in the hope that it will be useful,
1.18 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1.19 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1.20 + * GNU General Public License for more details.
1.21 + *
1.22 + * You should have received a copy of the GNU General Public License
1.23 + * along with this program; if not, write to the Free Software
1.24 + * Foundation, Inc., 51 Franklin Street, Fifth Floor,
1.25 + * Boston, MA 02110-1301, USA
1.26 + */
1.27 +
1.28 +#ifndef __JZ4730_H__
1.29 +#define __JZ4730_H__
1.30 +
1.31 +#include "xburst_types.h"
1.32 +
1.33 +/* NOTE: Independent of usbboot parameters. */
1.34 +
1.35 +#define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */
1.36 +#define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
1.37 +#define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */
1.38 +
1.39 +#define HARB_BASE 0xB3000000
1.40 +#define EMC_BASE 0xB3010000
1.41 +#define DMAC_BASE 0xB3020000
1.42 +#define UHC_BASE 0xB3030000
1.43 +#define UDC_BASE 0xB3040000
1.44 +#define LCD_BASE 0xB3050000
1.45 +#define CIM_BASE 0xB3060000
1.46 +#define ETH_BASE 0xB3100000
1.47 +#define NBM_BASE 0xB3F00000
1.48 +
1.49 +#define CPM_BASE 0xB0000000
1.50 +#define INTC_BASE 0xB0001000
1.51 +#define OST_BASE 0xB0002000
1.52 +#define RTC_BASE 0xB0003000
1.53 +#define WDT_BASE 0xB0004000
1.54 +#define GPIO_BASE 0xB0010000
1.55 +#define AIC_BASE 0xB0020000
1.56 +#define MSC_BASE 0xB0021000
1.57 +#define UART0_BASE 0xB0030000
1.58 +#define UART1_BASE 0xB0031000
1.59 +#define UART2_BASE 0xB0032000
1.60 +#define UART3_BASE 0xB0033000
1.61 +#define FIR_BASE 0xB0040000
1.62 +#define SCC_BASE 0xB0041000
1.63 +#define SCC0_BASE 0xB0041000
1.64 +#define I2C_BASE 0xB0042000
1.65 +#define SSI_BASE 0xB0043000
1.66 +#define SCC1_BASE 0xB0044000
1.67 +#define PWM0_BASE 0xB0050000
1.68 +#define PWM1_BASE 0xB0051000
1.69 +#define DES_BASE 0xB0060000
1.70 +#define UPRT_BASE 0xB0061000
1.71 +#define KBC_BASE 0xB0062000
1.72 +
1.73 +
1.74 +
1.75 +
1.76 +/*************************************************************************
1.77 + * MSC
1.78 + *************************************************************************/
1.79 +#define MSC_STRPCL (MSC_BASE + 0x000)
1.80 +#define MSC_STAT (MSC_BASE + 0x004)
1.81 +#define MSC_CLKRT (MSC_BASE + 0x008)
1.82 +#define MSC_CMDAT (MSC_BASE + 0x00C)
1.83 +#define MSC_RESTO (MSC_BASE + 0x010)
1.84 +#define MSC_RDTO (MSC_BASE + 0x014)
1.85 +#define MSC_BLKLEN (MSC_BASE + 0x018)
1.86 +#define MSC_NOB (MSC_BASE + 0x01C)
1.87 +#define MSC_SNOB (MSC_BASE + 0x020)
1.88 +#define MSC_IMASK (MSC_BASE + 0x024)
1.89 +#define MSC_IREG (MSC_BASE + 0x028)
1.90 +#define MSC_CMD (MSC_BASE + 0x02C)
1.91 +#define MSC_ARG (MSC_BASE + 0x030)
1.92 +#define MSC_RES (MSC_BASE + 0x034)
1.93 +#define MSC_RXFIFO (MSC_BASE + 0x038)
1.94 +#define MSC_TXFIFO (MSC_BASE + 0x03C)
1.95 +
1.96 +#define REG_MSC_STRPCL REG16(MSC_STRPCL)
1.97 +#define REG_MSC_STAT REG32(MSC_STAT)
1.98 +#define REG_MSC_CLKRT REG16(MSC_CLKRT)
1.99 +#define REG_MSC_CMDAT REG32(MSC_CMDAT)
1.100 +#define REG_MSC_RESTO REG16(MSC_RESTO)
1.101 +#define REG_MSC_RDTO REG16(MSC_RDTO)
1.102 +#define REG_MSC_BLKLEN REG16(MSC_BLKLEN)
1.103 +#define REG_MSC_NOB REG16(MSC_NOB)
1.104 +#define REG_MSC_SNOB REG16(MSC_SNOB)
1.105 +#define REG_MSC_IMASK REG16(MSC_IMASK)
1.106 +#define REG_MSC_IREG REG16(MSC_IREG)
1.107 +#define REG_MSC_CMD REG8(MSC_CMD)
1.108 +#define REG_MSC_ARG REG32(MSC_ARG)
1.109 +#define REG_MSC_RES REG16(MSC_RES)
1.110 +#define REG_MSC_RXFIFO REG32(MSC_RXFIFO)
1.111 +#define REG_MSC_TXFIFO REG32(MSC_TXFIFO)
1.112 +
1.113 +/* MSC Clock and Control Register (MSC_STRPCL) */
1.114 +
1.115 +#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7)
1.116 +#define MSC_STRPCL_EXIT_TRANSFER (1 << 6)
1.117 +#define MSC_STRPCL_START_READWAIT (1 << 5)
1.118 +#define MSC_STRPCL_STOP_READWAIT (1 << 4)
1.119 +#define MSC_STRPCL_RESET (1 << 3)
1.120 +#define MSC_STRPCL_START_OP (1 << 2)
1.121 +#define MSC_STRPCL_CLOCK_CONTROL_BIT 0
1.122 +#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
1.123 + #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */
1.124 + #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */
1.125 +
1.126 +/* MSC Status Register (MSC_STAT) */
1.127 +
1.128 +#define MSC_STAT_IS_RESETTING (1 << 15)
1.129 +#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14)
1.130 +#define MSC_STAT_PRG_DONE (1 << 13)
1.131 +#define MSC_STAT_DATA_TRAN_DONE (1 << 12)
1.132 +#define MSC_STAT_END_CMD_RES (1 << 11)
1.133 +#define MSC_STAT_DATA_FIFO_AFULL (1 << 10)
1.134 +#define MSC_STAT_IS_READWAIT (1 << 9)
1.135 +#define MSC_STAT_CLK_EN (1 << 8)
1.136 +#define MSC_STAT_DATA_FIFO_FULL (1 << 7)
1.137 +#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6)
1.138 +#define MSC_STAT_CRC_RES_ERR (1 << 5)
1.139 +#define MSC_STAT_CRC_READ_ERROR (1 << 4)
1.140 +#define MSC_STAT_CRC_WRITE_ERROR_BIT 2
1.141 +#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
1.142 + #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */
1.143 + #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */
1.144 + #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */
1.145 +#define MSC_STAT_TIME_OUT_RES (1 << 1)
1.146 +#define MSC_STAT_TIME_OUT_READ (1 << 0)
1.147 +
1.148 +/* MSC Bus Clock Control Register (MSC_CLKRT) */
1.149 +
1.150 +#define MSC_CLKRT_CLK_RATE_BIT 0
1.151 +#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT)
1.152 + #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */
1.153 + #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */
1.154 + #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */
1.155 + #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */
1.156 + #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */
1.157 + #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */
1.158 + #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */
1.159 + #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */
1.160 +
1.161 +/* MSC Command Sequence Control Register (MSC_CMDAT) */
1.162 +
1.163 +#define MSC_CMDAT_IO_ABORT (1 << 11)
1.164 +#define MSC_CMDAT_BUS_WIDTH_BIT 9
1.165 +#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
1.166 + #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */
1.167 + #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */
1.168 + #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
1.169 + #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
1.170 +#define MSC_CMDAT_DMA_EN (1 << 8)
1.171 +#define MSC_CMDAT_INIT (1 << 7)
1.172 +#define MSC_CMDAT_BUSY (1 << 6)
1.173 +#define MSC_CMDAT_STREAM_BLOCK (1 << 5)
1.174 +#define MSC_CMDAT_WRITE (1 << 4)
1.175 +#define MSC_CMDAT_READ (0 << 4)
1.176 +#define MSC_CMDAT_DATA_EN (1 << 3)
1.177 +#define MSC_CMDAT_RESPONSE_BIT 0
1.178 +#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
1.179 + #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */
1.180 + #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */
1.181 + #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */
1.182 + #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */
1.183 + #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */
1.184 + #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */
1.185 + #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */
1.186 +
1.187 +#define CMDAT_DMA_EN (1 << 8)
1.188 +#define CMDAT_INIT (1 << 7)
1.189 +#define CMDAT_BUSY (1 << 6)
1.190 +#define CMDAT_STREAM (1 << 5)
1.191 +#define CMDAT_WRITE (1 << 4)
1.192 +#define CMDAT_DATA_EN (1 << 3)
1.193 +
1.194 +/* MSC Interrupts Mask Register (MSC_IMASK) */
1.195 +
1.196 +#define MSC_IMASK_SDIO (1 << 7)
1.197 +#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6)
1.198 +#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5)
1.199 +#define MSC_IMASK_END_CMD_RES (1 << 2)
1.200 +#define MSC_IMASK_PRG_DONE (1 << 1)
1.201 +#define MSC_IMASK_DATA_TRAN_DONE (1 << 0)
1.202 +
1.203 +
1.204 +/* MSC Interrupts Status Register (MSC_IREG) */
1.205 +
1.206 +#define MSC_IREG_SDIO (1 << 7)
1.207 +#define MSC_IREG_TXFIFO_WR_REQ (1 << 6)
1.208 +#define MSC_IREG_RXFIFO_RD_REQ (1 << 5)
1.209 +#define MSC_IREG_END_CMD_RES (1 << 2)
1.210 +#define MSC_IREG_PRG_DONE (1 << 1)
1.211 +#define MSC_IREG_DATA_TRAN_DONE (1 << 0)
1.212 +
1.213 +/*************************************************************************
1.214 + * RTC
1.215 + *************************************************************************/
1.216 +#define RTC_RCR (RTC_BASE + 0x00)
1.217 +#define RTC_RSR (RTC_BASE + 0x04)
1.218 +#define RTC_RSAR (RTC_BASE + 0x08)
1.219 +#define RTC_RGR (RTC_BASE + 0x0c)
1.220 +
1.221 +#define REG_RTC_RCR REG32(RTC_RCR)
1.222 +#define REG_RTC_RSR REG32(RTC_RSR)
1.223 +#define REG_RTC_RSAR REG32(RTC_RSAR)
1.224 +#define REG_RTC_RGR REG32(RTC_RGR)
1.225 +
1.226 +#define RTC_RCR_HZ (1 << 6)
1.227 +#define RTC_RCR_HZIE (1 << 5)
1.228 +#define RTC_RCR_AF (1 << 4)
1.229 +#define RTC_RCR_AIE (1 << 3)
1.230 +#define RTC_RCR_AE (1 << 2)
1.231 +#define RTC_RCR_START (1 << 0)
1.232 +
1.233 +#define RTC_RGR_LOCK (1 << 31)
1.234 +#define RTC_RGR_ADJ_BIT 16
1.235 +#define RTC_RGR_ADJ_MASK (0x3ff << RTC_RGR_ADJ_BIT)
1.236 +#define RTC_RGR_DIV_BIT 0
1.237 +#define RTC_REG_DIV_MASK (0xff << RTC_RGR_DIV_BIT)
1.238 +
1.239 +
1.240 +
1.241 +
1.242 +/*************************************************************************
1.243 + * FIR
1.244 + *************************************************************************/
1.245 +#define FIR_TDR (FIR_BASE + 0x000)
1.246 +#define FIR_RDR (FIR_BASE + 0x004)
1.247 +#define FIR_TFLR (FIR_BASE + 0x008)
1.248 +#define FIR_AR (FIR_BASE + 0x00C)
1.249 +#define FIR_CR1 (FIR_BASE + 0x010)
1.250 +#define FIR_CR2 (FIR_BASE + 0x014)
1.251 +#define FIR_SR (FIR_BASE + 0x018)
1.252 +
1.253 +#define REG_FIR_TDR REG8(FIR_TDR)
1.254 +#define REG_FIR_RDR REG8(FIR_RDR)
1.255 +#define REG_FIR_TFLR REG16(FIR_TFLR)
1.256 +#define REG_FIR_AR REG8(FIR_AR)
1.257 +#define REG_FIR_CR1 REG8(FIR_CR1)
1.258 +#define REG_FIR_CR2 REG16(FIR_CR2)
1.259 +#define REG_FIR_SR REG16(FIR_SR)
1.260 +
1.261 +/* FIR Control Register 1 (FIR_CR1) */
1.262 +
1.263 +#define FIR_CR1_FIRUE (1 << 7)
1.264 +#define FIR_CR1_ACE (1 << 6)
1.265 +#define FIR_CR1_EOUS (1 << 5)
1.266 +#define FIR_CR1_TIIE (1 << 4)
1.267 +#define FIR_CR1_TFIE (1 << 3)
1.268 +#define FIR_CR1_RFIE (1 << 2)
1.269 +#define FIR_CR1_TXE (1 << 1)
1.270 +#define FIR_CR1_RXE (1 << 0)
1.271 +
1.272 +/* FIR Control Register 2 (FIR_CR2) */
1.273 +
1.274 +#define FIR_CR2_SIPE (1 << 10)
1.275 +#define FIR_CR2_BCRC (1 << 9)
1.276 +#define FIR_CR2_TFLRS (1 << 8)
1.277 +#define FIR_CR2_ISS (1 << 7)
1.278 +#define FIR_CR2_LMS (1 << 6)
1.279 +#define FIR_CR2_TPPS (1 << 5)
1.280 +#define FIR_CR2_RPPS (1 << 4)
1.281 +#define FIR_CR2_TTRG_BIT 2
1.282 +#define FIR_CR2_TTRG_MASK (0x3 << FIR_CR2_TTRG_BIT)
1.283 + #define FIR_CR2_TTRG_16 (0 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 16 */
1.284 + #define FIR_CR2_TTRG_32 (1 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 32 */
1.285 + #define FIR_CR2_TTRG_64 (2 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 64 */
1.286 + #define FIR_CR2_TTRG_128 (3 << FIR_CR2_TTRG_BIT) /* Transmit Trigger Level is 128 */
1.287 +#define FIR_CR2_RTRG_BIT 0
1.288 +#define FIR_CR2_RTRG_MASK (0x3 << FIR_CR2_RTRG_BIT)
1.289 + #define FIR_CR2_RTRG_16 (0 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 16 */
1.290 + #define FIR_CR2_RTRG_32 (1 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 32 */
1.291 + #define FIR_CR2_RTRG_64 (2 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 64 */
1.292 + #define FIR_CR2_RTRG_128 (3 << FIR_CR2_RTRG_BIT) /* Receive Trigger Level is 128 */
1.293 +
1.294 +/* FIR Status Register (FIR_SR) */
1.295 +
1.296 +#define FIR_SR_RFW (1 << 12)
1.297 +#define FIR_SR_RFA (1 << 11)
1.298 +#define FIR_SR_TFRTL (1 << 10)
1.299 +#define FIR_SR_RFRTL (1 << 9)
1.300 +#define FIR_SR_URUN (1 << 8)
1.301 +#define FIR_SR_RFTE (1 << 7)
1.302 +#define FIR_SR_ORUN (1 << 6)
1.303 +#define FIR_SR_CRCE (1 << 5)
1.304 +#define FIR_SR_FEND (1 << 4)
1.305 +#define FIR_SR_TFF (1 << 3)
1.306 +#define FIR_SR_RFE (1 << 2)
1.307 +#define FIR_SR_TIDLE (1 << 1)
1.308 +#define FIR_SR_RB (1 << 0)
1.309 +
1.310 +
1.311 +
1.312 +
1.313 +/*************************************************************************
1.314 + * SCC
1.315 + *************************************************************************/
1.316 +#define SCC_DR(base) ((base) + 0x000)
1.317 +#define SCC_FDR(base) ((base) + 0x004)
1.318 +#define SCC_CR(base) ((base) + 0x008)
1.319 +#define SCC_SR(base) ((base) + 0x00C)
1.320 +#define SCC_TFR(base) ((base) + 0x010)
1.321 +#define SCC_EGTR(base) ((base) + 0x014)
1.322 +#define SCC_ECR(base) ((base) + 0x018)
1.323 +#define SCC_RTOR(base) ((base) + 0x01C)
1.324 +
1.325 +#define REG_SCC_DR(base) REG8(SCC_DR(base))
1.326 +#define REG_SCC_FDR(base) REG8(SCC_FDR(base))
1.327 +#define REG_SCC_CR(base) REG32(SCC_CR(base))
1.328 +#define REG_SCC_SR(base) REG16(SCC_SR(base))
1.329 +#define REG_SCC_TFR(base) REG16(SCC_TFR(base))
1.330 +#define REG_SCC_EGTR(base) REG8(SCC_EGTR(base))
1.331 +#define REG_SCC_ECR(base) REG32(SCC_ECR(base))
1.332 +#define REG_SCC_RTOR(base) REG8(SCC_RTOR(base))
1.333 +
1.334 +/* SCC FIFO Data Count Register (SCC_FDR) */
1.335 +
1.336 +#define SCC_FDR_EMPTY 0x00
1.337 +#define SCC_FDR_FULL 0x10
1.338 +
1.339 +/* SCC Control Register (SCC_CR) */
1.340 +
1.341 +#define SCC_CR_SCCE (1 << 31)
1.342 +#define SCC_CR_TRS (1 << 30)
1.343 +#define SCC_CR_T2R (1 << 29)
1.344 +#define SCC_CR_FDIV_BIT 24
1.345 +#define SCC_CR_FDIV_MASK (0x3 << SCC_CR_FDIV_BIT)
1.346 + #define SCC_CR_FDIV_1 (0 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is the same as device clock */
1.347 + #define SCC_CR_FDIV_2 (1 << SCC_CR_FDIV_BIT) /* SCC_CLK frequency is half of device clock */
1.348 +#define SCC_CR_FLUSH (1 << 23)
1.349 +#define SCC_CR_TRIG_BIT 16
1.350 +#define SCC_CR_TRIG_MASK (0x3 << SCC_CR_TRIG_BIT)
1.351 + #define SCC_CR_TRIG_1 (0 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 1 */
1.352 + #define SCC_CR_TRIG_4 (1 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 4 */
1.353 + #define SCC_CR_TRIG_8 (2 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 8 */
1.354 + #define SCC_CR_TRIG_14 (3 << SCC_CR_TRIG_BIT) /* Receive/Transmit-FIFO Trigger is 14 */
1.355 +#define SCC_CR_TP (1 << 15)
1.356 +#define SCC_CR_CONV (1 << 14)
1.357 +#define SCC_CR_TXIE (1 << 13)
1.358 +#define SCC_CR_RXIE (1 << 12)
1.359 +#define SCC_CR_TENDIE (1 << 11)
1.360 +#define SCC_CR_RTOIE (1 << 10)
1.361 +#define SCC_CR_ECIE (1 << 9)
1.362 +#define SCC_CR_EPIE (1 << 8)
1.363 +#define SCC_CR_RETIE (1 << 7)
1.364 +#define SCC_CR_EOIE (1 << 6)
1.365 +#define SCC_CR_TSEND (1 << 3)
1.366 +#define SCC_CR_PX_BIT 1
1.367 +#define SCC_CR_PX_MASK (0x3 << SCC_CR_PX_BIT)
1.368 + #define SCC_CR_PX_NOT_SUPPORT (0 << SCC_CR_PX_BIT) /* SCC does not support clock stop */
1.369 + #define SCC_CR_PX_STOP_LOW (1 << SCC_CR_PX_BIT) /* SCC_CLK stops at state low */
1.370 + #define SCC_CR_PX_STOP_HIGH (2 << SCC_CR_PX_BIT) /* SCC_CLK stops at state high */
1.371 +#define SCC_CR_CLKSTP (1 << 0)
1.372 +
1.373 +/* SCC Status Register (SCC_SR) */
1.374 +
1.375 +#define SCC_SR_TRANS (1 << 15)
1.376 +#define SCC_SR_ORER (1 << 12)
1.377 +#define SCC_SR_RTO (1 << 11)
1.378 +#define SCC_SR_PER (1 << 10)
1.379 +#define SCC_SR_TFTG (1 << 9)
1.380 +#define SCC_SR_RFTG (1 << 8)
1.381 +#define SCC_SR_TEND (1 << 7)
1.382 +#define SCC_SR_RETR_3 (1 << 4)
1.383 +#define SCC_SR_ECNTO (1 << 0)
1.384 +
1.385 +
1.386 +
1.387 +
1.388 +/*************************************************************************
1.389 + * ETH
1.390 + *************************************************************************/
1.391 +#define ETH_BMR (ETH_BASE + 0x1000)
1.392 +#define ETH_TPDR (ETH_BASE + 0x1004)
1.393 +#define ETH_RPDR (ETH_BASE + 0x1008)
1.394 +#define ETH_RAR (ETH_BASE + 0x100C)
1.395 +#define ETH_TAR (ETH_BASE + 0x1010)
1.396 +#define ETH_SR (ETH_BASE + 0x1014)
1.397 +#define ETH_CR (ETH_BASE + 0x1018)
1.398 +#define ETH_IER (ETH_BASE + 0x101C)
1.399 +#define ETH_MFCR (ETH_BASE + 0x1020)
1.400 +#define ETH_CTAR (ETH_BASE + 0x1050)
1.401 +#define ETH_CRAR (ETH_BASE + 0x1054)
1.402 +#define ETH_MCR (ETH_BASE + 0x0000)
1.403 +#define ETH_MAHR (ETH_BASE + 0x0004)
1.404 +#define ETH_MALR (ETH_BASE + 0x0008)
1.405 +#define ETH_HTHR (ETH_BASE + 0x000C)
1.406 +#define ETH_HTLR (ETH_BASE + 0x0010)
1.407 +#define ETH_MIAR (ETH_BASE + 0x0014)
1.408 +#define ETH_MIDR (ETH_BASE + 0x0018)
1.409 +#define ETH_FCR (ETH_BASE + 0x001C)
1.410 +#define ETH_VTR1 (ETH_BASE + 0x0020)
1.411 +#define ETH_VTR2 (ETH_BASE + 0x0024)
1.412 +#define ETH_WKFR (ETH_BASE + 0x0028)
1.413 +#define ETH_PMTR (ETH_BASE + 0x002C)
1.414 +
1.415 +#define REG_ETH_BMR REG32(ETH_BMR)
1.416 +#define REG_ETH_TPDR REG32(ETH_TPDR)
1.417 +#define REG_ETH_RPDR REG32(ETH_RPDR)
1.418 +#define REG_ETH_RAR REG32(ETH_RAR)
1.419 +#define REG_ETH_TAR REG32(ETH_TAR)
1.420 +#define REG_ETH_SR REG32(ETH_SR)
1.421 +#define REG_ETH_CR REG32(ETH_CR)
1.422 +#define REG_ETH_IER REG32(ETH_IER)
1.423 +#define REG_ETH_MFCR REG32(ETH_MFCR)
1.424 +#define REG_ETH_CTAR REG32(ETH_CTAR)
1.425 +#define REG_ETH_CRAR REG32(ETH_CRAR)
1.426 +#define REG_ETH_MCR REG32(ETH_MCR)
1.427 +#define REG_ETH_MAHR REG32(ETH_MAHR)
1.428 +#define REG_ETH_MALR REG32(ETH_MALR)
1.429 +#define REG_ETH_HTHR REG32(ETH_HTHR)
1.430 +#define REG_ETH_HTLR REG32(ETH_HTLR)
1.431 +#define REG_ETH_MIAR REG32(ETH_MIAR)
1.432 +#define REG_ETH_MIDR REG32(ETH_MIDR)
1.433 +#define REG_ETH_FCR REG32(ETH_FCR)
1.434 +#define REG_ETH_VTR1 REG32(ETH_VTR1)
1.435 +#define REG_ETH_VTR2 REG32(ETH_VTR2)
1.436 +#define REG_ETH_WKFR REG32(ETH_WKFR)
1.437 +#define REG_ETH_PMTR REG32(ETH_PMTR)
1.438 +
1.439 +/* Bus Mode Register (ETH_BMR) */
1.440 +
1.441 +#define ETH_BMR_DBO (1 << 20)
1.442 +#define ETH_BMR_PBL_BIT 8
1.443 +#define ETH_BMR_PBL_MASK (0x3f << ETH_BMR_PBL_BIT)
1.444 + #define ETH_BMR_PBL_1 (0x1 << ETH_BMR_PBL_BIT)
1.445 + #define ETH_BMR_PBL_4 (0x4 << ETH_BMR_PBL_BIT)
1.446 +#define ETH_BMR_BLE (1 << 7)
1.447 +#define ETH_BMR_DSL_BIT 2
1.448 +#define ETH_BMR_DSL_MASK (0x1f << ETH_BMR_DSL_BIT)
1.449 + #define ETH_BMR_DSL_0 (0x0 << ETH_BMR_DSL_BIT)
1.450 + #define ETH_BMR_DSL_1 (0x1 << ETH_BMR_DSL_BIT)
1.451 + #define ETH_BMR_DSL_2 (0x2 << ETH_BMR_DSL_BIT)
1.452 + #define ETH_BMR_DSL_4 (0x4 << ETH_BMR_DSL_BIT)
1.453 + #define ETH_BMR_DSL_8 (0x8 << ETH_BMR_DSL_BIT)
1.454 +#define ETH_BMR_SWR (1 << 0)
1.455 +
1.456 +/* DMA Status Register (ETH_SR) */
1.457 +
1.458 +#define ETH_SR_EB_BIT 23
1.459 +#define ETH_SR_EB_MASK (0x7 << ETH_SR_EB_BIT)
1.460 + #define ETH_SR_EB_TX_ABORT (0x1 << ETH_SR_EB_BIT)
1.461 + #define ETH_SR_EB_RX_ABORT (0x2 << ETH_SR_EB_BIT)
1.462 +#define ETH_SR_TS_BIT 20
1.463 +#define ETH_SR_TS_MASK (0x7 << ETH_SR_TS_BIT)
1.464 + #define ETH_SR_TS_STOP (0x0 << ETH_SR_TS_BIT)
1.465 + #define ETH_SR_TS_FTD (0x1 << ETH_SR_TS_BIT)
1.466 + #define ETH_SR_TS_WEOT (0x2 << ETH_SR_TS_BIT)
1.467 + #define ETH_SR_TS_QDAT (0x3 << ETH_SR_TS_BIT)
1.468 + #define ETH_SR_TS_SUSPEND (0x6 << ETH_SR_TS_BIT)
1.469 + #define ETH_SR_TS_CTD (0x7 << ETH_SR_TS_BIT)
1.470 +#define ETH_SR_RS_BIT 17
1.471 +#define ETH_SR_RS_MASK (0x7 << ETH_SR_RS_BIT)
1.472 + #define ETH_SR_RS_STOP (0x0 << ETH_SR_RS_BIT)
1.473 + #define ETH_SR_RS_FRD (0x1 << ETH_SR_RS_BIT)
1.474 + #define ETH_SR_RS_CEOR (0x2 << ETH_SR_RS_BIT)
1.475 + #define ETH_SR_RS_WRP (0x3 << ETH_SR_RS_BIT)
1.476 + #define ETH_SR_RS_SUSPEND (0x4 << ETH_SR_RS_BIT)
1.477 + #define ETH_SR_RS_CRD (0x5 << ETH_SR_RS_BIT)
1.478 + #define ETH_SR_RS_FCF (0x6 << ETH_SR_RS_BIT)
1.479 + #define ETH_SR_RS_QRF (0x7 << ETH_SR_RS_BIT)
1.480 +#define ETH_SR_NIS (1 << 16)
1.481 +#define ETH_SR_AIS (1 << 15)
1.482 +#define ETH_SR_ERI (1 << 14)
1.483 +#define ETH_SR_FBE (1 << 13)
1.484 +#define ETH_SR_ETI (1 << 10)
1.485 +#define ETH_SR_RWT (1 << 9)
1.486 +#define ETH_SR_RPS (1 << 8)
1.487 +#define ETH_SR_RU (1 << 7)
1.488 +#define ETH_SR_RI (1 << 6)
1.489 +#define ETH_SR_UNF (1 << 5)
1.490 +#define ETH_SR_TJT (1 << 3)
1.491 +#define ETH_SR_TU (1 << 2)
1.492 +#define ETH_SR_TPS (1 << 1)
1.493 +#define ETH_SR_TI (1 << 0)
1.494 +
1.495 +/* Control (Operation Mode) Register (ETH_CR) */
1.496 +
1.497 +#define ETH_CR_TTM (1 << 22)
1.498 +#define ETH_CR_SF (1 << 21)
1.499 +#define ETH_CR_TR_BIT 14
1.500 +#define ETH_CR_TR_MASK (0x3 << ETH_CR_TR_BIT)
1.501 +#define ETH_CR_ST (1 << 13)
1.502 +#define ETH_CR_OSF (1 << 2)
1.503 +#define ETH_CR_SR (1 << 1)
1.504 +
1.505 +/* Interrupt Enable Register (ETH_IER) */
1.506 +
1.507 +#define ETH_IER_NI (1 << 16)
1.508 +#define ETH_IER_AI (1 << 15)
1.509 +#define ETH_IER_ERE (1 << 14)
1.510 +#define ETH_IER_FBE (1 << 13)
1.511 +#define ETH_IER_ET (1 << 10)
1.512 +#define ETH_IER_RWE (1 << 9)
1.513 +#define ETH_IER_RS (1 << 8)
1.514 +#define ETH_IER_RU (1 << 7)
1.515 +#define ETH_IER_RI (1 << 6)
1.516 +#define ETH_IER_UN (1 << 5)
1.517 +#define ETH_IER_TJ (1 << 3)
1.518 +#define ETH_IER_TU (1 << 2)
1.519 +#define ETH_IER_TS (1 << 1)
1.520 +#define ETH_IER_TI (1 << 0)
1.521 +
1.522 +/* Missed Frame and Buffer Overflow Counter Register (ETH_MFCR) */
1.523 +
1.524 +#define ETH_MFCR_OVERFLOW_BIT 17
1.525 +#define ETH_MFCR_OVERFLOW_MASK (0x7ff << ETH_MFCR_OVERFLOW_BIT)
1.526 +#define ETH_MFCR_MFC_BIT 0
1.527 +#define ETH_MFCR_MFC_MASK (0xffff << ETH_MFCR_MFC_BIT)
1.528 +
1.529 +/* MAC Control Register (ETH_MCR) */
1.530 +
1.531 +#define ETH_MCR_RA (1 << 31)
1.532 +#define ETH_MCR_HBD (1 << 28)
1.533 +#define ETH_MCR_PS (1 << 27)
1.534 +#define ETH_MCR_DRO (1 << 23)
1.535 +#define ETH_MCR_OM_BIT 21
1.536 +#define ETH_MCR_OM_MASK (0x3 << ETH_MCR_OM_BIT)
1.537 + #define ETH_MCR_OM_NORMAL (0x0 << ETH_MCR_OM_BIT)
1.538 + #define ETH_MCR_OM_INTERNAL (0x1 << ETH_MCR_OM_BIT)
1.539 + #define ETH_MCR_OM_EXTERNAL (0x2 << ETH_MCR_OM_BIT)
1.540 +#define ETH_MCR_F (1 << 20)
1.541 +#define ETH_MCR_PM (1 << 19)
1.542 +#define ETH_MCR_PR (1 << 18)
1.543 +#define ETH_MCR_IF (1 << 17)
1.544 +#define ETH_MCR_PB (1 << 16)
1.545 +#define ETH_MCR_HO (1 << 15)
1.546 +#define ETH_MCR_HP (1 << 13)
1.547 +#define ETH_MCR_LCC (1 << 12)
1.548 +#define ETH_MCR_DBF (1 << 11)
1.549 +#define ETH_MCR_DTRY (1 << 10)
1.550 +#define ETH_MCR_ASTP (1 << 8)
1.551 +#define ETH_MCR_BOLMT_BIT 6
1.552 +#define ETH_MCR_BOLMT_MASK (0x3 << ETH_MCR_BOLMT_BIT)
1.553 + #define ETH_MCR_BOLMT_10 (0 << ETH_MCR_BOLMT_BIT)
1.554 + #define ETH_MCR_BOLMT_8 (1 << ETH_MCR_BOLMT_BIT)
1.555 + #define ETH_MCR_BOLMT_4 (2 << ETH_MCR_BOLMT_BIT)
1.556 + #define ETH_MCR_BOLMT_1 (3 << ETH_MCR_BOLMT_BIT)
1.557 +#define ETH_MCR_DC (1 << 5)
1.558 +#define ETH_MCR_TE (1 << 3)
1.559 +#define ETH_MCR_RE (1 << 2)
1.560 +
1.561 +/* MII Address Register (ETH_MIAR) */
1.562 +
1.563 +#define ETH_MIAR_PHY_ADDR_BIT 11
1.564 +#define ETH_MIAR_PHY_ADDR_MASK (0x1f << ETH_MIAR_PHY_ADDR_BIT)
1.565 +#define ETH_MIAR_MII_REG_BIT 6
1.566 +#define ETH_MIAR_MII_REG_MASK (0x1f << ETH_MIAR_MII_REG_BIT)
1.567 +#define ETH_MIAR_MII_WRITE (1 << 1)
1.568 +#define ETH_MIAR_MII_BUSY (1 << 0)
1.569 +
1.570 +/* Flow Control Register (ETH_FCR) */
1.571 +
1.572 +#define ETH_FCR_PAUSE_TIME_BIT 16
1.573 +#define ETH_FCR_PAUSE_TIME_MASK (0xffff << ETH_FCR_PAUSE_TIME_BIT)
1.574 +#define ETH_FCR_PCF (1 << 2)
1.575 +#define ETH_FCR_FCE (1 << 1)
1.576 +#define ETH_FCR_BUSY (1 << 0)
1.577 +
1.578 +/* PMT Control and Status Register (ETH_PMTR) */
1.579 +
1.580 +#define ETH_PMTR_GU (1 << 9)
1.581 +#define ETH_PMTR_RF (1 << 6)
1.582 +#define ETH_PMTR_MF (1 << 5)
1.583 +#define ETH_PMTR_RWK (1 << 2)
1.584 +#define ETH_PMTR_MPK (1 << 1)
1.585 +
1.586 +/* Receive Descriptor 0 (ETH_RD0) Bits */
1.587 +
1.588 +#define ETH_RD0_OWN (1 << 31)
1.589 +#define ETH_RD0_FF (1 << 30)
1.590 +#define ETH_RD0_FL_BIT 16
1.591 +#define ETH_RD0_FL_MASK (0x3fff << ETH_RD0_FL_BIT)
1.592 +#define ETH_RD0_ES (1 << 15)
1.593 +#define ETH_RD0_DE (1 << 14)
1.594 +#define ETH_RD0_LE (1 << 12)
1.595 +#define ETH_RD0_RF (1 << 11)
1.596 +#define ETH_RD0_MF (1 << 10)
1.597 +#define ETH_RD0_FD (1 << 9)
1.598 +#define ETH_RD0_LD (1 << 8)
1.599 +#define ETH_RD0_TL (1 << 7)
1.600 +#define ETH_RD0_CS (1 << 6)
1.601 +#define ETH_RD0_FT (1 << 5)
1.602 +#define ETH_RD0_WT (1 << 4)
1.603 +#define ETH_RD0_ME (1 << 3)
1.604 +#define ETH_RD0_DB (1 << 2)
1.605 +#define ETH_RD0_CE (1 << 1)
1.606 +
1.607 +/* Receive Descriptor 1 (ETH_RD1) Bits */
1.608 +
1.609 +#define ETH_RD1_RER (1 << 25)
1.610 +#define ETH_RD1_RCH (1 << 24)
1.611 +#define ETH_RD1_RBS2_BIT 11
1.612 +#define ETH_RD1_RBS2_MASK (0x7ff << ETH_RD1_RBS2_BIT)
1.613 +#define ETH_RD1_RBS1_BIT 0
1.614 +#define ETH_RD1_RBS1_MASK (0x7ff << ETH_RD1_RBS1_BIT)
1.615 +
1.616 +/* Transmit Descriptor 0 (ETH_TD0) Bits */
1.617 +
1.618 +#define ETH_TD0_OWN (1 << 31)
1.619 +#define ETH_TD0_FA (1 << 15)
1.620 +#define ETH_TD0_LOC (1 << 11)
1.621 +#define ETH_TD0_NC (1 << 10)
1.622 +#define ETH_TD0_LC (1 << 9)
1.623 +#define ETH_TD0_EC (1 << 8)
1.624 +#define ETH_TD0_HBF (1 << 7)
1.625 +#define ETH_TD0_CC_BIT 3
1.626 +#define ETH_TD0_CC_MASK (0xf << ETH_TD0_CC_BIT)
1.627 +#define ETH_TD0_ED (1 << 2)
1.628 +#define ETH_TD0_UF (1 << 1)
1.629 +#define ETH_TD0_DF (1 << 0)
1.630 +
1.631 +/* Transmit Descriptor 1 (ETH_TD1) Bits */
1.632 +
1.633 +#define ETH_TD1_IC (1 << 31)
1.634 +#define ETH_TD1_LS (1 << 30)
1.635 +#define ETH_TD1_FS (1 << 29)
1.636 +#define ETH_TD1_AC (1 << 26)
1.637 +#define ETH_TD1_TER (1 << 25)
1.638 +#define ETH_TD1_TCH (1 << 24)
1.639 +#define ETH_TD1_DPD (1 << 23)
1.640 +#define ETH_TD1_TBS2_BIT 11
1.641 +#define ETH_TD1_TBS2_MASK (0x7ff << ETH_TD1_TBS2_BIT)
1.642 +#define ETH_TD1_TBS1_BIT 0
1.643 +#define ETH_TD1_TBS1_MASK (0x7ff << ETH_TD1_TBS1_BIT)
1.644 +
1.645 +
1.646 +
1.647 +
1.648 +/*************************************************************************
1.649 + * WDT
1.650 + *************************************************************************/
1.651 +#define WDT_WTCSR (WDT_BASE + 0x00)
1.652 +#define WDT_WTCNT (WDT_BASE + 0x04)
1.653 +
1.654 +#define REG_WDT_WTCSR REG8(WDT_WTCSR)
1.655 +#define REG_WDT_WTCNT REG32(WDT_WTCNT)
1.656 +
1.657 +#define WDT_WTCSR_START (1 << 4)
1.658 +
1.659 +
1.660 +
1.661 +
1.662 +/*************************************************************************
1.663 + * OST
1.664 + *************************************************************************/
1.665 +#define OST_TER (OST_BASE + 0x00)
1.666 +#define OST_TRDR(n) (OST_BASE + 0x10 + ((n) * 0x20))
1.667 +#define OST_TCNT(n) (OST_BASE + 0x14 + ((n) * 0x20))
1.668 +#define OST_TCSR(n) (OST_BASE + 0x18 + ((n) * 0x20))
1.669 +#define OST_TCRB(n) (OST_BASE + 0x1c + ((n) * 0x20))
1.670 +
1.671 +#define REG_OST_TER REG8(OST_TER)
1.672 +#define REG_OST_TRDR(n) REG32(OST_TRDR((n)))
1.673 +#define REG_OST_TCNT(n) REG32(OST_TCNT((n)))
1.674 +#define REG_OST_TCSR(n) REG16(OST_TCSR((n)))
1.675 +#define REG_OST_TCRB(n) REG32(OST_TCRB((n)))
1.676 +
1.677 +#define OST_TCSR_BUSY (1 << 7)
1.678 +#define OST_TCSR_UF (1 << 6)
1.679 +#define OST_TCSR_UIE (1 << 5)
1.680 +#define OST_TCSR_CKS_BIT 0
1.681 +#define OST_TCSR_CKS_MASK (0x07 << OST_TCSR_CKS_BIT)
1.682 + #define OST_TCSR_CKS_PCLK_4 (0 << OST_TCSR_CKS_BIT)
1.683 + #define OST_TCSR_CKS_PCLK_16 (1 << OST_TCSR_CKS_BIT)
1.684 + #define OST_TCSR_CKS_PCLK_64 (2 << OST_TCSR_CKS_BIT)
1.685 + #define OST_TCSR_CKS_PCLK_256 (3 << OST_TCSR_CKS_BIT)
1.686 + #define OST_TCSR_CKS_RTCCLK (4 << OST_TCSR_CKS_BIT)
1.687 + #define OST_TCSR_CKS_EXTAL (5 << OST_TCSR_CKS_BIT)
1.688 +
1.689 +#define OST_TCSR0 OST_TCSR(0)
1.690 +#define OST_TCSR1 OST_TCSR(1)
1.691 +#define OST_TCSR2 OST_TCSR(2)
1.692 +#define OST_TRDR0 OST_TRDR(0)
1.693 +#define OST_TRDR1 OST_TRDR(1)
1.694 +#define OST_TRDR2 OST_TRDR(2)
1.695 +#define OST_TCNT0 OST_TCNT(0)
1.696 +#define OST_TCNT1 OST_TCNT(1)
1.697 +#define OST_TCNT2 OST_TCNT(2)
1.698 +#define OST_TCRB0 OST_TCRB(0)
1.699 +#define OST_TCRB1 OST_TCRB(1)
1.700 +#define OST_TCRB2 OST_TCRB(2)
1.701 +
1.702 +/*************************************************************************
1.703 + * UART
1.704 + *************************************************************************/
1.705 +
1.706 +#define IRDA_BASE UART0_BASE
1.707 +#define UART_BASE UART0_BASE
1.708 +#define UART_OFF 0x1000
1.709 +
1.710 +/* register offset */
1.711 +#define OFF_RDR (0x00) /* R 8b H'xx */
1.712 +#define OFF_TDR (0x00) /* W 8b H'xx */
1.713 +#define OFF_DLLR (0x00) /* RW 8b H'00 */
1.714 +#define OFF_DLHR (0x04) /* RW 8b H'00 */
1.715 +#define OFF_IER (0x04) /* RW 8b H'00 */
1.716 +#define OFF_ISR (0x08) /* R 8b H'01 */
1.717 +#define OFF_FCR (0x08) /* W 8b H'00 */
1.718 +#define OFF_LCR (0x0C) /* RW 8b H'00 */
1.719 +#define OFF_MCR (0x10) /* RW 8b H'00 */
1.720 +#define OFF_LSR (0x14) /* R 8b H'00 */
1.721 +#define OFF_MSR (0x18) /* R 8b H'00 */
1.722 +#define OFF_SPR (0x1C) /* RW 8b H'00 */
1.723 +#define OFF_MCR (0x10) /* RW 8b H'00 */
1.724 +#define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */
1.725 +
1.726 +/* register address */
1.727 +#define UART0_RDR (UART0_BASE + OFF_RDR)
1.728 +#define UART0_TDR (UART0_BASE + OFF_TDR)
1.729 +#define UART0_DLLR (UART0_BASE + OFF_DLLR)
1.730 +#define UART0_DLHR (UART0_BASE + OFF_DLHR)
1.731 +#define UART0_IER (UART0_BASE + OFF_IER)
1.732 +#define UART0_ISR (UART0_BASE + OFF_ISR)
1.733 +#define UART0_FCR (UART0_BASE + OFF_FCR)
1.734 +#define UART0_LCR (UART0_BASE + OFF_LCR)
1.735 +#define UART0_MCR (UART0_BASE + OFF_MCR)
1.736 +#define UART0_LSR (UART0_BASE + OFF_LSR)
1.737 +#define UART0_MSR (UART0_BASE + OFF_MSR)
1.738 +#define UART0_SPR (UART0_BASE + OFF_SPR)
1.739 +#define UART0_SIRCR (UART0_BASE + OFF_SIRCR)
1.740 +
1.741 +#define UART1_RDR (UART1_BASE + OFF_RDR)
1.742 +#define UART1_TDR (UART1_BASE + OFF_TDR)
1.743 +#define UART1_DLLR (UART1_BASE + OFF_DLLR)
1.744 +#define UART1_DLHR (UART1_BASE + OFF_DLHR)
1.745 +#define UART1_IER (UART1_BASE + OFF_IER)
1.746 +#define UART1_ISR (UART1_BASE + OFF_ISR)
1.747 +#define UART1_FCR (UART1_BASE + OFF_FCR)
1.748 +#define UART1_LCR (UART1_BASE + OFF_LCR)
1.749 +#define UART1_MCR (UART1_BASE + OFF_MCR)
1.750 +#define UART1_LSR (UART1_BASE + OFF_LSR)
1.751 +#define UART1_MSR (UART1_BASE + OFF_MSR)
1.752 +#define UART1_SPR (UART1_BASE + OFF_SPR)
1.753 +#define UART1_SIRCR (UART1_BASE + OFF_SIRCR)
1.754 +
1.755 +#define UART2_RDR (UART2_BASE + OFF_RDR)
1.756 +#define UART2_TDR (UART2_BASE + OFF_TDR)
1.757 +#define UART2_DLLR (UART2_BASE + OFF_DLLR)
1.758 +#define UART2_DLHR (UART2_BASE + OFF_DLHR)
1.759 +#define UART2_IER (UART2_BASE + OFF_IER)
1.760 +#define UART2_ISR (UART2_BASE + OFF_ISR)
1.761 +#define UART2_FCR (UART2_BASE + OFF_FCR)
1.762 +#define UART2_LCR (UART2_BASE + OFF_LCR)
1.763 +#define UART2_MCR (UART2_BASE + OFF_MCR)
1.764 +#define UART2_LSR (UART2_BASE + OFF_LSR)
1.765 +#define UART2_MSR (UART2_BASE + OFF_MSR)
1.766 +#define UART2_SPR (UART2_BASE + OFF_SPR)
1.767 +#define UART2_SIRCR (UART2_BASE + OFF_SIRCR)
1.768 +
1.769 +#define UART3_RDR (UART3_BASE + OFF_RDR)
1.770 +#define UART3_TDR (UART3_BASE + OFF_TDR)
1.771 +#define UART3_DLLR (UART3_BASE + OFF_DLLR)
1.772 +#define UART3_DLHR (UART3_BASE + OFF_DLHR)
1.773 +#define UART3_IER (UART3_BASE + OFF_IER)
1.774 +#define UART3_ISR (UART3_BASE + OFF_ISR)
1.775 +#define UART3_FCR (UART3_BASE + OFF_FCR)
1.776 +#define UART3_LCR (UART3_BASE + OFF_LCR)
1.777 +#define UART3_MCR (UART3_BASE + OFF_MCR)
1.778 +#define UART3_LSR (UART3_BASE + OFF_LSR)
1.779 +#define UART3_MSR (UART3_BASE + OFF_MSR)
1.780 +#define UART3_SPR (UART3_BASE + OFF_SPR)
1.781 +#define UART3_SIRCR (UART3_BASE + OFF_SIRCR)
1.782 +
1.783 +/*
1.784 + * Define macros for UART_IER
1.785 + * UART Interrupt Enable Register
1.786 + */
1.787 +#define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */
1.788 +#define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */
1.789 +#define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
1.790 +#define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */
1.791 +#define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
1.792 +
1.793 +/*
1.794 + * Define macros for UART_ISR
1.795 + * UART Interrupt Status Register
1.796 + */
1.797 +#define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
1.798 +#define UART_ISR_IID (7 << 1) /* Source of Interrupt */
1.799 +#define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */
1.800 +#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
1.801 +#define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */
1.802 +#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
1.803 +#define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */
1.804 +#define UART_ISR_FFMS_NO_FIFO (0 << 6)
1.805 +#define UART_ISR_FFMS_FIFO_MODE (3 << 6)
1.806 +
1.807 +/*
1.808 + * Define macros for UART_FCR
1.809 + * UART FIFO Control Register
1.810 + */
1.811 +#define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
1.812 +#define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
1.813 +#define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
1.814 +#define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */
1.815 +#define UART_FCR_UUE (1 << 4) /* 0: disable UART */
1.816 +#define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
1.817 +#define UART_FCR_RTRG_1 (0 << 6)
1.818 +#define UART_FCR_RTRG_4 (1 << 6)
1.819 +#define UART_FCR_RTRG_8 (2 << 6)
1.820 +#define UART_FCR_RTRG_15 (3 << 6)
1.821 +
1.822 +/*
1.823 + * Define macros for UART_LCR
1.824 + * UART Line Control Register
1.825 + */
1.826 +#define UART_LCR_WLEN (3 << 0) /* word length */
1.827 +#define UART_LCR_WLEN_5 (0 << 0)
1.828 +#define UART_LCR_WLEN_6 (1 << 0)
1.829 +#define UART_LCR_WLEN_7 (2 << 0)
1.830 +#define UART_LCR_WLEN_8 (3 << 0)
1.831 +#define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
1.832 + 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
1.833 +#define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
1.834 + 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
1.835 +#define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
1.836 + 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
1.837 +
1.838 +#define UART_LCR_PE (1 << 3) /* 0: parity disable */
1.839 +#define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
1.840 +#define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */
1.841 +#define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
1.842 +#define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */
1.843 +
1.844 +/*
1.845 + * Define macros for UART_LSR
1.846 + * UART Line Status Register
1.847 + */
1.848 +#define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */
1.849 +#define UART_LSR_ORER (1 << 1) /* 0: no overrun error */
1.850 +#define UART_LSR_PER (1 << 2) /* 0: no parity error */
1.851 +#define UART_LSR_FER (1 << 3) /* 0; no framing error */
1.852 +#define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */
1.853 +#define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */
1.854 +#define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */
1.855 +#define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */
1.856 +
1.857 +/*
1.858 + * Define macros for UART_MCR
1.859 + * UART Modem Control Register
1.860 + */
1.861 +#define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */
1.862 +#define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */
1.863 +#define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */
1.864 +#define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */
1.865 +#define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
1.866 +#define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */
1.867 +
1.868 +/*
1.869 + * Define macros for UART_MSR
1.870 + * UART Modem Status Register
1.871 + */
1.872 +#define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */
1.873 +#define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */
1.874 +#define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */
1.875 +#define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */
1.876 +#define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */
1.877 +#define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */
1.878 +#define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */
1.879 +#define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */
1.880 +
1.881 +/*
1.882 + * Define macros for SIRCR
1.883 + * Slow IrDA Control Register
1.884 + */
1.885 +#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */
1.886 +#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */
1.887 +#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
1.888 + 1: 0 pulse width is 1.6us for 115.2Kbps */
1.889 +#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
1.890 +#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
1.891 +
1.892 +
1.893 +
1.894 +/*************************************************************************
1.895 + * INTC
1.896 + *************************************************************************/
1.897 +#define INTC_ISR (INTC_BASE + 0x00)
1.898 +#define INTC_IMR (INTC_BASE + 0x04)
1.899 +#define INTC_IMSR (INTC_BASE + 0x08)
1.900 +#define INTC_IMCR (INTC_BASE + 0x0c)
1.901 +#define INTC_IPR (INTC_BASE + 0x10)
1.902 +
1.903 +#define REG_INTC_ISR REG32(INTC_ISR)
1.904 +#define REG_INTC_IMR REG32(INTC_IMR)
1.905 +#define REG_INTC_IMSR REG32(INTC_IMSR)
1.906 +#define REG_INTC_IMCR REG32(INTC_IMCR)
1.907 +#define REG_INTC_IPR REG32(INTC_IPR)
1.908 +
1.909 +#define IRQ_I2C 1
1.910 +#define IRQ_PS2 2
1.911 +#define IRQ_UPRT 3
1.912 +#define IRQ_CORE 4
1.913 +#define IRQ_UART3 6
1.914 +#define IRQ_UART2 7
1.915 +#define IRQ_UART1 8
1.916 +#define IRQ_UART0 9
1.917 +#define IRQ_SCC1 10
1.918 +#define IRQ_SCC0 11
1.919 +#define IRQ_UDC 12
1.920 +#define IRQ_UHC 13
1.921 +#define IRQ_MSC 14
1.922 +#define IRQ_RTC 15
1.923 +#define IRQ_FIR 16
1.924 +#define IRQ_SSI 17
1.925 +#define IRQ_CIM 18
1.926 +#define IRQ_ETH 19
1.927 +#define IRQ_AIC 20
1.928 +#define IRQ_DMAC 21
1.929 +#define IRQ_OST2 22
1.930 +#define IRQ_OST1 23
1.931 +#define IRQ_OST0 24
1.932 +#define IRQ_GPIO3 25
1.933 +#define IRQ_GPIO2 26
1.934 +#define IRQ_GPIO1 27
1.935 +#define IRQ_GPIO0 28
1.936 +#define IRQ_LCD 30
1.937 +
1.938 +
1.939 +
1.940 +
1.941 +/*************************************************************************
1.942 + * CIM
1.943 + *************************************************************************/
1.944 +#define CIM_CFG (CIM_BASE + 0x0000)
1.945 +#define CIM_CTRL (CIM_BASE + 0x0004)
1.946 +#define CIM_STATE (CIM_BASE + 0x0008)
1.947 +#define CIM_IID (CIM_BASE + 0x000C)
1.948 +#define CIM_RXFIFO (CIM_BASE + 0x0010)
1.949 +#define CIM_DA (CIM_BASE + 0x0020)
1.950 +#define CIM_FA (CIM_BASE + 0x0024)
1.951 +#define CIM_FID (CIM_BASE + 0x0028)
1.952 +#define CIM_CMD (CIM_BASE + 0x002C)
1.953 +
1.954 +#define REG_CIM_CFG REG32(CIM_CFG)
1.955 +#define REG_CIM_CTRL REG32(CIM_CTRL)
1.956 +#define REG_CIM_STATE REG32(CIM_STATE)
1.957 +#define REG_CIM_IID REG32(CIM_IID)
1.958 +#define REG_CIM_RXFIFO REG32(CIM_RXFIFO)
1.959 +#define REG_CIM_DA REG32(CIM_DA)
1.960 +#define REG_CIM_FA REG32(CIM_FA)
1.961 +#define REG_CIM_FID REG32(CIM_FID)
1.962 +#define REG_CIM_CMD REG32(CIM_CMD)
1.963 +
1.964 +/* CIM Configuration Register (CIM_CFG) */
1.965 +
1.966 +#define CIM_CFG_INV_DAT (1 << 15)
1.967 +#define CIM_CFG_VSP (1 << 14)
1.968 +#define CIM_CFG_HSP (1 << 13)
1.969 +#define CIM_CFG_PCP (1 << 12)
1.970 +#define CIM_CFG_DUMMY_ZERO (1 << 9)
1.971 +#define CIM_CFG_EXT_VSYNC (1 << 8)
1.972 +#define CIM_CFG_PACK_BIT 4
1.973 +#define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT)
1.974 + #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT)
1.975 + #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT)
1.976 + #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT)
1.977 + #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT)
1.978 + #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT)
1.979 + #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT)
1.980 + #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT)
1.981 + #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT)
1.982 +#define CIM_CFG_DSM_BIT 0
1.983 +#define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT)
1.984 + #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */
1.985 + #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */
1.986 + #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */
1.987 + #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */
1.988 +
1.989 +/* CIM Control Register (CIM_CTRL) */
1.990 +
1.991 +#define CIM_CTRL_MCLKDIV_BIT 24
1.992 +#define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT)
1.993 +#define CIM_CTRL_FRC_BIT 16
1.994 +#define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT)
1.995 + #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */
1.996 + #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */
1.997 + #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */
1.998 + #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */
1.999 + #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */
1.1000 + #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */
1.1001 + #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */
1.1002 + #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */
1.1003 + #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */
1.1004 + #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */
1.1005 + #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */
1.1006 + #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */
1.1007 + #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */
1.1008 + #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */
1.1009 + #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */
1.1010 + #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */
1.1011 +#define CIM_CTRL_VDDM (1 << 13)
1.1012 +#define CIM_CTRL_DMA_SOFM (1 << 12)
1.1013 +#define CIM_CTRL_DMA_EOFM (1 << 11)
1.1014 +#define CIM_CTRL_DMA_STOPM (1 << 10)
1.1015 +#define CIM_CTRL_RXF_TRIGM (1 << 9)
1.1016 +#define CIM_CTRL_RXF_OFM (1 << 8)
1.1017 +#define CIM_CTRL_RXF_TRIG_BIT 4
1.1018 +#define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT)
1.1019 + #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */
1.1020 + #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */
1.1021 + #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */
1.1022 + #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */
1.1023 + #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */
1.1024 + #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */
1.1025 + #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */
1.1026 + #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */
1.1027 +#define CIM_CTRL_DMA_EN (1 << 2)
1.1028 +#define CIM_CTRL_RXF_RST (1 << 1)
1.1029 +#define CIM_CTRL_ENA (1 << 0)
1.1030 +
1.1031 +/* CIM State Register (CIM_STATE) */
1.1032 +
1.1033 +#define CIM_STATE_DMA_SOF (1 << 6)
1.1034 +#define CIM_STATE_DMA_EOF (1 << 5)
1.1035 +#define CIM_STATE_DMA_STOP (1 << 4)
1.1036 +#define CIM_STATE_RXF_OF (1 << 3)
1.1037 +#define CIM_STATE_RXF_TRIG (1 << 2)
1.1038 +#define CIM_STATE_RXF_EMPTY (1 << 1)
1.1039 +#define CIM_STATE_VDD (1 << 0)
1.1040 +
1.1041 +/* CIM DMA Command Register (CIM_CMD) */
1.1042 +
1.1043 +#define CIM_CMD_SOFINT (1 << 31)
1.1044 +#define CIM_CMD_EOFINT (1 << 30)
1.1045 +#define CIM_CMD_STOP (1 << 28)
1.1046 +#define CIM_CMD_LEN_BIT 0
1.1047 +#define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT)
1.1048 +
1.1049 +
1.1050 +
1.1051 +
1.1052 +/*************************************************************************
1.1053 + * PWM
1.1054 + *************************************************************************/
1.1055 +#define PWM_CTR(n) (PWM##n##_BASE + 0x000)
1.1056 +#define PWM_PER(n) (PWM##n##_BASE + 0x004)
1.1057 +#define PWM_DUT(n) (PWM##n##_BASE + 0x008)
1.1058 +
1.1059 +#define REG_PWM_CTR(n) REG8(PWM_CTR(n))
1.1060 +#define REG_PWM_PER(n) REG16(PWM_PER(n))
1.1061 +#define REG_PWM_DUT(n) REG16(PWM_DUT(n))
1.1062 +
1.1063 +/* PWM Control Register (PWM_CTR) */
1.1064 +
1.1065 +#define PWM_CTR_EN (1 << 7)
1.1066 +#define PWM_CTR_SD (1 << 6)
1.1067 +#define PWM_CTR_PRESCALE_BIT 0
1.1068 +#define PWM_CTR_PRESCALE_MASK (0x3f << PWM_CTR_PRESCALE_BIT)
1.1069 +
1.1070 +/* PWM Period Register (PWM_PER) */
1.1071 +
1.1072 +#define PWM_PER_PERIOD_BIT 0
1.1073 +#define PWM_PER_PERIOD_MASK (0x3ff << PWM_PER_PERIOD_BIT)
1.1074 +
1.1075 +/* PWM Duty Register (PWM_DUT) */
1.1076 +
1.1077 +#define PWM_DUT_FDUTY (1 << 10)
1.1078 +#define PWM_DUT_DUTY_BIT 0
1.1079 +#define PWM_DUT_DUTY_MASK (0x3ff << PWM_DUT_DUTY_BIT)
1.1080 +
1.1081 +
1.1082 +
1.1083 +
1.1084 +/*************************************************************************
1.1085 + * EMC
1.1086 + *************************************************************************/
1.1087 +#define EMC_BCR (EMC_BASE + 0x00)
1.1088 +#define EMC_SMCR0 (EMC_BASE + 0x10)
1.1089 +#define EMC_SMCR1 (EMC_BASE + 0x14)
1.1090 +#define EMC_SMCR2 (EMC_BASE + 0x18)
1.1091 +#define EMC_SMCR3 (EMC_BASE + 0x1c)
1.1092 +#define EMC_SMCR4 (EMC_BASE + 0x20)
1.1093 +#define EMC_SMCR5 (EMC_BASE + 0x24)
1.1094 +#define EMC_SMCR6 (EMC_BASE + 0x28)
1.1095 +#define EMC_SMCR7 (EMC_BASE + 0x2c)
1.1096 +#define EMC_SACR0 (EMC_BASE + 0x30)
1.1097 +#define EMC_SACR1 (EMC_BASE + 0x34)
1.1098 +#define EMC_SACR2 (EMC_BASE + 0x38)
1.1099 +#define EMC_SACR3 (EMC_BASE + 0x3c)
1.1100 +#define EMC_SACR4 (EMC_BASE + 0x40)
1.1101 +#define EMC_SACR5 (EMC_BASE + 0x44)
1.1102 +#define EMC_SACR6 (EMC_BASE + 0x48)
1.1103 +#define EMC_SACR7 (EMC_BASE + 0x4c)
1.1104 +#define EMC_NFCSR (EMC_BASE + 0x50)
1.1105 +#define EMC_NFECC (EMC_BASE + 0x54)
1.1106 +#define EMC_PCCR1 (EMC_BASE + 0x60)
1.1107 +#define EMC_PCCR2 (EMC_BASE + 0x64)
1.1108 +#define EMC_PCCR3 (EMC_BASE + 0x68)
1.1109 +#define EMC_PCCR4 (EMC_BASE + 0x6c)
1.1110 +#define EMC_DMCR (EMC_BASE + 0x80)
1.1111 +#define EMC_RTCSR (EMC_BASE + 0x84)
1.1112 +#define EMC_RTCNT (EMC_BASE + 0x88)
1.1113 +#define EMC_RTCOR (EMC_BASE + 0x8c)
1.1114 +#define EMC_DMAR1 (EMC_BASE + 0x90)
1.1115 +#define EMC_DMAR2 (EMC_BASE + 0x94)
1.1116 +#define EMC_DMAR3 (EMC_BASE + 0x98)
1.1117 +#define EMC_DMAR4 (EMC_BASE + 0x9c)
1.1118 +
1.1119 +#define EMC_SDMR0 (EMC_BASE + 0xa000)
1.1120 +#define EMC_SDMR1 (EMC_BASE + 0xb000)
1.1121 +#define EMC_SDMR2 (EMC_BASE + 0xc000)
1.1122 +#define EMC_SDMR3 (EMC_BASE + 0xd000)
1.1123 +
1.1124 +/* NAND command/address/data port */
1.1125 +#define NAND_DATAPORT 0xB4000000 /* read-write area */
1.1126 +#define NAND_COMMPORT 0xB4040000 /* write only area */
1.1127 +#define NAND_ADDRPORT 0xB4080000 /* write only area */
1.1128 +
1.1129 +#define REG_EMC_BCR REG32(EMC_BCR)
1.1130 +#define REG_EMC_SMCR0 REG32(EMC_SMCR0)
1.1131 +#define REG_EMC_SMCR1 REG32(EMC_SMCR1)
1.1132 +#define REG_EMC_SMCR2 REG32(EMC_SMCR2)
1.1133 +#define REG_EMC_SMCR3 REG32(EMC_SMCR3)
1.1134 +#define REG_EMC_SMCR4 REG32(EMC_SMCR4)
1.1135 +#define REG_EMC_SMCR5 REG32(EMC_SMCR5)
1.1136 +#define REG_EMC_SMCR6 REG32(EMC_SMCR6)
1.1137 +#define REG_EMC_SMCR7 REG32(EMC_SMCR7)
1.1138 +#define REG_EMC_SACR0 REG32(EMC_SACR0)
1.1139 +#define REG_EMC_SACR1 REG32(EMC_SACR1)
1.1140 +#define REG_EMC_SACR2 REG32(EMC_SACR2)
1.1141 +#define REG_EMC_SACR3 REG32(EMC_SACR3)
1.1142 +#define REG_EMC_SACR4 REG32(EMC_SACR4)
1.1143 +#define REG_EMC_SACR5 REG32(EMC_SACR5)
1.1144 +#define REG_EMC_SACR6 REG32(EMC_SACR6)
1.1145 +#define REG_EMC_SACR7 REG32(EMC_SACR7)
1.1146 +#define REG_EMC_NFCSR REG32(EMC_NFCSR)
1.1147 +#define REG_EMC_NFECC REG32(EMC_NFECC)
1.1148 +#define REG_EMC_DMCR REG32(EMC_DMCR)
1.1149 +#define REG_EMC_RTCSR REG16(EMC_RTCSR)
1.1150 +#define REG_EMC_RTCNT REG16(EMC_RTCNT)
1.1151 +#define REG_EMC_RTCOR REG16(EMC_RTCOR)
1.1152 +#define REG_EMC_DMAR1 REG32(EMC_DMAR1)
1.1153 +#define REG_EMC_DMAR2 REG32(EMC_DMAR2)
1.1154 +#define REG_EMC_DMAR3 REG32(EMC_DMAR3)
1.1155 +#define REG_EMC_DMAR4 REG32(EMC_DMAR4)
1.1156 +#define REG_EMC_PCCR1 REG32(EMC_PCCR1)
1.1157 +#define REG_EMC_PCCR2 REG32(EMC_PCCR2)
1.1158 +#define REG_EMC_PCCR3 REG32(EMC_PCCR3)
1.1159 +#define REG_EMC_PCCR4 REG32(EMC_PCCR4)
1.1160 +
1.1161 +
1.1162 +#define EMC_BCR_BRE (1 << 1)
1.1163 +
1.1164 +#define EMC_SMCR_STRV_BIT 24
1.1165 +#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT)
1.1166 +#define EMC_SMCR_TAW_BIT 20
1.1167 +#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT)
1.1168 +#define EMC_SMCR_TBP_BIT 16
1.1169 +#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT)
1.1170 +#define EMC_SMCR_TAH_BIT 12
1.1171 +#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT)
1.1172 +#define EMC_SMCR_TAS_BIT 8
1.1173 +#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT)
1.1174 +#define EMC_SMCR_BW_BIT 6
1.1175 +#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT)
1.1176 + #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT)
1.1177 + #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT)
1.1178 + #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT)
1.1179 +#define EMC_SMCR_BCM (1 << 3)
1.1180 +#define EMC_SMCR_BL_BIT 1
1.1181 +#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT)
1.1182 + #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT)
1.1183 + #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT)
1.1184 + #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT)
1.1185 + #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT)
1.1186 +#define EMC_SMCR_SMT (1 << 0)
1.1187 +
1.1188 +#define EMC_SACR_BASE_BIT 8
1.1189 +#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT)
1.1190 +#define EMC_SACR_MASK_BIT 0
1.1191 +#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT)
1.1192 +
1.1193 +#define EMC_NFCSR_RB (1 << 7)
1.1194 +#define EMC_NFCSR_BOOT_SEL_BIT 4
1.1195 +#define EMC_NFCSR_BOOT_SEL_MASK (0x07 << EMC_NFCSR_BOOT_SEL_BIT)
1.1196 +#define EMC_NFCSR_ERST (1 << 3)
1.1197 +#define EMC_NFCSR_ECCE (1 << 2)
1.1198 +#define EMC_NFCSR_FCE (1 << 1)
1.1199 +#define EMC_NFCSR_NFE (1 << 0)
1.1200 +
1.1201 +#define EMC_NFECC_ECC2_BIT 16
1.1202 +#define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT)
1.1203 +#define EMC_NFECC_ECC1_BIT 8
1.1204 +#define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT)
1.1205 +#define EMC_NFECC_ECC0_BIT 0
1.1206 +#define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT)
1.1207 +
1.1208 +#define EMC_DMCR_BW_BIT 31
1.1209 +#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT)
1.1210 + #define EMC_DMCR_BW_32 (0 << EMC_DMCR_BW_BIT)
1.1211 + #define EMC_DMCR_BW_16 (1 << EMC_DMCR_BW_BIT)
1.1212 +#define EMC_DMCR_CA_BIT 26
1.1213 +#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT)
1.1214 + #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT)
1.1215 + #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT)
1.1216 + #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT)
1.1217 + #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT)
1.1218 + #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT)
1.1219 +#define EMC_DMCR_RMODE (1 << 25)
1.1220 +#define EMC_DMCR_RFSH (1 << 24)
1.1221 +#define EMC_DMCR_MRSET (1 << 23)
1.1222 +#define EMC_DMCR_RA_BIT 20
1.1223 +#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT)
1.1224 + #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT)
1.1225 + #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT)
1.1226 + #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT)
1.1227 +#define EMC_DMCR_BA_BIT 19
1.1228 +#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT)
1.1229 + #define EMC_DMCR_BA_2 (0 << EMC_DMCR_BA_BIT)
1.1230 + #define EMC_DMCR_BA_4 (1 << EMC_DMCR_BA_BIT)
1.1231 +#define EMC_DMCR_PDM (1 << 18)
1.1232 +#define EMC_DMCR_EPIN (1 << 17)
1.1233 +#define EMC_DMCR_TRAS_BIT 13
1.1234 +#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT)
1.1235 +#define EMC_DMCR_RCD_BIT 11
1.1236 +#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT)
1.1237 +#define EMC_DMCR_TPC_BIT 8
1.1238 +#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT)
1.1239 +#define EMC_DMCR_TRWL_BIT 5
1.1240 +#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT)
1.1241 +#define EMC_DMCR_TRC_BIT 2
1.1242 +#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT)
1.1243 +#define EMC_DMCR_TCL_BIT 0
1.1244 +#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT)
1.1245 + #define EMC_DMCR_CASL_2 (1 << EMC_DMCR_TCL_BIT)
1.1246 + #define EMC_DMCR_CASL_3 (2 << EMC_DMCR_TCL_BIT)
1.1247 +
1.1248 +#define EMC_RTCSR_CMF (1 << 7)
1.1249 +#define EMC_RTCSR_CKS_BIT 0
1.1250 +#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT)
1.1251 + #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT)
1.1252 + #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT)
1.1253 + #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT)
1.1254 + #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT)
1.1255 + #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT)
1.1256 + #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT)
1.1257 + #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT)
1.1258 + #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT)
1.1259 +
1.1260 +#define EMC_DMAR_BASE_BIT 8
1.1261 +#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
1.1262 +#define EMC_DMAR_MASK_BIT 0
1.1263 +#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
1.1264 +
1.1265 +#define EMC_SDMR_BM (1 << 9)
1.1266 +#define EMC_SDMR_OM_BIT 7
1.1267 +#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT)
1.1268 + #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT)
1.1269 +#define EMC_SDMR_CAS_BIT 4
1.1270 +#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT)
1.1271 + #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT)
1.1272 + #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT)
1.1273 + #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT)
1.1274 +#define EMC_SDMR_BT_BIT 3
1.1275 +#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT)
1.1276 + #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT)
1.1277 + #define EMC_SDMR_BT_INTR (1 << EMC_SDMR_BT_BIT)
1.1278 +#define EMC_SDMR_BL_BIT 0
1.1279 +#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT)
1.1280 + #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT)
1.1281 + #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT)
1.1282 + #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT)
1.1283 + #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT)
1.1284 +
1.1285 +#define EMC_SDMR_CAS2_16BIT \
1.1286 + (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
1.1287 +#define EMC_SDMR_CAS2_32BIT \
1.1288 + (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1.1289 +#define EMC_SDMR_CAS3_16BIT \
1.1290 + (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
1.1291 +#define EMC_SDMR_CAS3_32BIT \
1.1292 + (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1.1293 +
1.1294 +#define EMC_PCCR12_AMW (1 << 31)
1.1295 +#define EMC_PCCR12_AMAS_BIT 28
1.1296 +#define EMC_PCCR12_AMAS_MASK (0x07 << EMC_PCCR12_AMAS_BIT)
1.1297 +#define EMC_PCCR12_AMAH_BIT 24
1.1298 +#define EMC_PCCR12_AMAH_MASK (0x07 << EMC_PCCR12_AMAH_BIT)
1.1299 +#define EMC_PCCR12_AMPW_BIT 20
1.1300 +#define EMC_PCCR12_AMPW_MASK (0x0f << EMC_PCCR12_AMPW_BIT)
1.1301 +#define EMC_PCCR12_AMRT_BIT 16
1.1302 +#define EMC_PCCR12_AMRT_MASK (0x0f << EMC_PCCR12_AMRT_BIT)
1.1303 +#define EMC_PCCR12_CMW (1 << 15)
1.1304 +#define EMC_PCCR12_CMAS_BIT 12
1.1305 +#define EMC_PCCR12_CMAS_MASK (0x07 << EMC_PCCR12_CMAS_BIT)
1.1306 +#define EMC_PCCR12_CMAH_BIT 8
1.1307 +#define EMC_PCCR12_CMAH_MASK (0x07 << EMC_PCCR12_CMAH_BIT)
1.1308 +#define EMC_PCCR12_CMPW_BIT 4
1.1309 +#define EMC_PCCR12_CMPW_MASK (0x0f << EMC_PCCR12_CMPW_BIT)
1.1310 +#define EMC_PCCR12_CMRT_BIT 0
1.1311 +#define EMC_PCCR12_CMRT_MASK (0x07 << EMC_PCCR12_CMRT_BIT)
1.1312 +
1.1313 +#define EMC_PCCR34_DRS_BIT 16
1.1314 +#define EMC_PCCR34_DRS_MASK (0x03 << EMC_PCCR34_DRS_BIT)
1.1315 + #define EMC_PCCR34_DRS_SPKR (1 << EMC_PCCR34_DRS_BIT)
1.1316 + #define EMC_PCCR34_DRS_IOIS16 (2 << EMC_PCCR34_DRS_BIT)
1.1317 + #define EMC_PCCR34_DRS_INPACK (3 << EMC_PCCR34_DRS_BIT)
1.1318 +#define EMC_PCCR34_IOIS16 (1 << 15)
1.1319 +#define EMC_PCCR34_IOW (1 << 14)
1.1320 +#define EMC_PCCR34_TCB_BIT 12
1.1321 +#define EMC_PCCR34_TCB_MASK (0x03 << EMC_PCCR34_TCB_BIT)
1.1322 +#define EMC_PCCR34_IORT_BIT 8
1.1323 +#define EMC_PCCR34_IORT_MASK (0x07 << EMC_PCCR34_IORT_BIT)
1.1324 +#define EMC_PCCR34_IOAE_BIT 6
1.1325 +#define EMC_PCCR34_IOAE_MASK (0x03 << EMC_PCCR34_IOAE_BIT)
1.1326 + #define EMC_PCCR34_IOAE_NONE (0 << EMC_PCCR34_IOAE_BIT)
1.1327 + #define EMC_PCCR34_IOAE_1 (1 << EMC_PCCR34_IOAE_BIT)
1.1328 + #define EMC_PCCR34_IOAE_2 (2 << EMC_PCCR34_IOAE_BIT)
1.1329 + #define EMC_PCCR34_IOAE_5 (3 << EMC_PCCR34_IOAE_BIT)
1.1330 +#define EMC_PCCR34_IOAH_BIT 4
1.1331 +#define EMC_PCCR34_IOAH_MASK (0x03 << EMC_PCCR34_IOAH_BIT)
1.1332 + #define EMC_PCCR34_IOAH_NONE (0 << EMC_PCCR34_IOAH_BIT)
1.1333 + #define EMC_PCCR34_IOAH_1 (1 << EMC_PCCR34_IOAH_BIT)
1.1334 + #define EMC_PCCR34_IOAH_2 (2 << EMC_PCCR34_IOAH_BIT)
1.1335 + #define EMC_PCCR34_IOAH_5 (3 << EMC_PCCR34_IOAH_BIT)
1.1336 +#define EMC_PCCR34_IOPW_BIT 0
1.1337 +#define EMC_PCCR34_IOPW_MASK (0x0f << EMC_PCCR34_IOPW_BIT)
1.1338 +
1.1339 +
1.1340 +
1.1341 +
1.1342 +/*************************************************************************
1.1343 + * GPIO
1.1344 + *************************************************************************/
1.1345 +#define GPIO_GPDR(n) (GPIO_BASE + (0x00 + (n)*0x30))
1.1346 +#define GPIO_GPDIR(n) (GPIO_BASE + (0x04 + (n)*0x30))
1.1347 +#define GPIO_GPODR(n) (GPIO_BASE + (0x08 + (n)*0x30))
1.1348 +#define GPIO_GPPUR(n) (GPIO_BASE + (0x0c + (n)*0x30))
1.1349 +#define GPIO_GPALR(n) (GPIO_BASE + (0x10 + (n)*0x30))
1.1350 +#define GPIO_GPAUR(n) (GPIO_BASE + (0x14 + (n)*0x30))
1.1351 +#define GPIO_GPIDLR(n) (GPIO_BASE + (0x18 + (n)*0x30))
1.1352 +#define GPIO_GPIDUR(n) (GPIO_BASE + (0x1c + (n)*0x30))
1.1353 +#define GPIO_GPIER(n) (GPIO_BASE + (0x20 + (n)*0x30))
1.1354 +#define GPIO_GPIMR(n) (GPIO_BASE + (0x24 + (n)*0x30))
1.1355 +#define GPIO_GPFR(n) (GPIO_BASE + (0x28 + (n)*0x30))
1.1356 +
1.1357 +#define REG_GPIO_GPDR(n) REG32(GPIO_GPDR((n)))
1.1358 +#define REG_GPIO_GPDIR(n) REG32(GPIO_GPDIR((n)))
1.1359 +#define REG_GPIO_GPODR(n) REG32(GPIO_GPODR((n)))
1.1360 +#define REG_GPIO_GPPUR(n) REG32(GPIO_GPPUR((n)))
1.1361 +#define REG_GPIO_GPALR(n) REG32(GPIO_GPALR((n)))
1.1362 +#define REG_GPIO_GPAUR(n) REG32(GPIO_GPAUR((n)))
1.1363 +#define REG_GPIO_GPIDLR(n) REG32(GPIO_GPIDLR((n)))
1.1364 +#define REG_GPIO_GPIDUR(n) REG32(GPIO_GPIDUR((n)))
1.1365 +#define REG_GPIO_GPIER(n) REG32(GPIO_GPIER((n)))
1.1366 +#define REG_GPIO_GPIMR(n) REG32(GPIO_GPIMR((n)))
1.1367 +#define REG_GPIO_GPFR(n) REG32(GPIO_GPFR((n)))
1.1368 +
1.1369 +#define GPIO_IRQ_LOLEVEL 0
1.1370 +#define GPIO_IRQ_HILEVEL 1
1.1371 +#define GPIO_IRQ_FALLEDG 2
1.1372 +#define GPIO_IRQ_RAISEDG 3
1.1373 +
1.1374 +#define IRQ_GPIO_0 48
1.1375 +#define NUM_GPIO 100
1.1376 +
1.1377 +#define GPIO_GPDR0 GPIO_GPDR(0)
1.1378 +#define GPIO_GPDR1 GPIO_GPDR(1)
1.1379 +#define GPIO_GPDR2 GPIO_GPDR(2)
1.1380 +#define GPIO_GPDR3 GPIO_GPDR(3)
1.1381 +#define GPIO_GPDIR0 GPIO_GPDIR(0)
1.1382 +#define GPIO_GPDIR1 GPIO_GPDIR(1)
1.1383 +#define GPIO_GPDIR2 GPIO_GPDIR(2)
1.1384 +#define GPIO_GPDIR3 GPIO_GPDIR(3)
1.1385 +#define GPIO_GPODR0 GPIO_GPODR(0)
1.1386 +#define GPIO_GPODR1 GPIO_GPODR(1)
1.1387 +#define GPIO_GPODR2 GPIO_GPODR(2)
1.1388 +#define GPIO_GPODR3 GPIO_GPODR(3)
1.1389 +#define GPIO_GPPUR0 GPIO_GPPUR(0)
1.1390 +#define GPIO_GPPUR1 GPIO_GPPUR(1)
1.1391 +#define GPIO_GPPUR2 GPIO_GPPUR(2)
1.1392 +#define GPIO_GPPUR3 GPIO_GPPUR(3)
1.1393 +#define GPIO_GPALR0 GPIO_GPALR(0)
1.1394 +#define GPIO_GPALR1 GPIO_GPALR(1)
1.1395 +#define GPIO_GPALR2 GPIO_GPALR(2)
1.1396 +#define GPIO_GPALR3 GPIO_GPALR(3)
1.1397 +#define GPIO_GPAUR0 GPIO_GPAUR(0)
1.1398 +#define GPIO_GPAUR1 GPIO_GPAUR(1)
1.1399 +#define GPIO_GPAUR2 GPIO_GPAUR(2)
1.1400 +#define GPIO_GPAUR3 GPIO_GPAUR(3)
1.1401 +#define GPIO_GPIDLR0 GPIO_GPIDLR(0)
1.1402 +#define GPIO_GPIDLR1 GPIO_GPIDLR(1)
1.1403 +#define GPIO_GPIDLR2 GPIO_GPIDLR(2)
1.1404 +#define GPIO_GPIDLR3 GPIO_GPIDLR(3)
1.1405 +#define GPIO_GPIDUR0 GPIO_GPIDUR(0)
1.1406 +#define GPIO_GPIDUR1 GPIO_GPIDUR(1)
1.1407 +#define GPIO_GPIDUR2 GPIO_GPIDUR(2)
1.1408 +#define GPIO_GPIDUR3 GPIO_GPIDUR(3)
1.1409 +#define GPIO_GPIER0 GPIO_GPIER(0)
1.1410 +#define GPIO_GPIER1 GPIO_GPIER(1)
1.1411 +#define GPIO_GPIER2 GPIO_GPIER(2)
1.1412 +#define GPIO_GPIER3 GPIO_GPIER(3)
1.1413 +#define GPIO_GPIMR0 GPIO_GPIMR(0)
1.1414 +#define GPIO_GPIMR1 GPIO_GPIMR(1)
1.1415 +#define GPIO_GPIMR2 GPIO_GPIMR(2)
1.1416 +#define GPIO_GPIMR3 GPIO_GPIMR(3)
1.1417 +#define GPIO_GPFR0 GPIO_GPFR(0)
1.1418 +#define GPIO_GPFR1 GPIO_GPFR(1)
1.1419 +#define GPIO_GPFR2 GPIO_GPFR(2)
1.1420 +#define GPIO_GPFR3 GPIO_GPFR(3)
1.1421 +
1.1422 +
1.1423 +/*************************************************************************
1.1424 + * HARB
1.1425 + *************************************************************************/
1.1426 +#define HARB_HAPOR (HARB_BASE + 0x000)
1.1427 +#define HARB_HMCTR (HARB_BASE + 0x010)
1.1428 +#define HARB_HME8H (HARB_BASE + 0x014)
1.1429 +#define HARB_HMCR1 (HARB_BASE + 0x018)
1.1430 +#define HARB_HMER2 (HARB_BASE + 0x01C)
1.1431 +#define HARB_HMER3 (HARB_BASE + 0x020)
1.1432 +#define HARB_HMLTR (HARB_BASE + 0x024)
1.1433 +
1.1434 +#define REG_HARB_HAPOR REG32(HARB_HAPOR)
1.1435 +#define REG_HARB_HMCTR REG32(HARB_HMCTR)
1.1436 +#define REG_HARB_HME8H REG32(HARB_HME8H)
1.1437 +#define REG_HARB_HMCR1 REG32(HARB_HMCR1)
1.1438 +#define REG_HARB_HMER2 REG32(HARB_HMER2)
1.1439 +#define REG_HARB_HMER3 REG32(HARB_HMER3)
1.1440 +#define REG_HARB_HMLTR REG32(HARB_HMLTR)
1.1441 +
1.1442 +/* HARB Priority Order Register (HARB_HAPOR) */
1.1443 +
1.1444 +#define HARB_HAPOR_UCHSEL (1 << 7)
1.1445 +#define HARB_HAPOR_PRIO_BIT 0
1.1446 +#define HARB_HAPOR_PRIO_MASK (0xf << HARB_HAPOR_PRIO_BIT)
1.1447 +
1.1448 +/* AHB Monitor Control Register (HARB_HMCTR) */
1.1449 +
1.1450 +#define HARB_HMCTR_HET3_BIT 20
1.1451 +#define HARB_HMCTR_HET3_MASK (0xf << HARB_HMCTR_HET3_BIT)
1.1452 +#define HARB_HMCTR_HMS3_BIT 16
1.1453 +#define HARB_HMCTR_HMS3_MASK (0xf << HARB_HMCTR_HMS3_BIT)
1.1454 +#define HARB_HMCTR_HET2_BIT 12
1.1455 +#define HARB_HMCTR_HET2_MASK (0xf << HARB_HMCTR_HET2_BIT)
1.1456 +#define HARB_HMCTR_HMS2_BIT 8
1.1457 +#define HARB_HMCTR_HMS2_MASK (0xf << HARB_HMCTR_HMS2_BIT)
1.1458 +#define HARB_HMCTR_HOVF3 (1 << 7)
1.1459 +#define HARB_HMCTR_HOVF2 (1 << 6)
1.1460 +#define HARB_HMCTR_HOVF1 (1 << 5)
1.1461 +#define HARB_HMCTR_HRST (1 << 4)
1.1462 +#define HARB_HMCTR_HEE3 (1 << 2)
1.1463 +#define HARB_HMCTR_HEE2 (1 << 1)
1.1464 +#define HARB_HMCTR_HEE1 (1 << 0)
1.1465 +
1.1466 +/* AHB Monitor Event 8bits High Register (HARB_HME8H) */
1.1467 +
1.1468 +#define HARB_HME8H_HC8H1_BIT 16
1.1469 +#define HARB_HME8H_HC8H1_MASK (0xff << HARB_HME8H_HC8H1_BIT)
1.1470 +#define HARB_HME8H_HC8H2_BIT 8
1.1471 +#define HARB_HME8H_HC8H2_MASK (0xff << HARB_HME8H_HC8H2_BIT)
1.1472 +#define HARB_HME8H_HC8H3_BIT 0
1.1473 +#define HARB_HME8H_HC8H3_MASK (0xff << HARB_HME8H_HC8H3_BIT)
1.1474 +
1.1475 +/* AHB Monitor Latency Register (HARB_HMLTR) */
1.1476 +
1.1477 +#define HARB_HMLTR_HLT2_BIT 16
1.1478 +#define HARB_HMLTR_HLT2_MASK (0xffff << HARB_HMLTR_HLT2_BIT)
1.1479 +#define HARB_HMLTR_HLT3_BIT 0
1.1480 +#define HARB_HMLTR_HLT3_MASK (0xffff << HARB_HMLTR_HLT3_BIT)
1.1481 +
1.1482 +
1.1483 +
1.1484 +
1.1485 +/*************************************************************************
1.1486 + * I2C
1.1487 + *************************************************************************/
1.1488 +#define I2C_DR (I2C_BASE + 0x000)
1.1489 +#define I2C_CR (I2C_BASE + 0x004)
1.1490 +#define I2C_SR (I2C_BASE + 0x008)
1.1491 +#define I2C_GR (I2C_BASE + 0x00C)
1.1492 +
1.1493 +#define REG_I2C_DR REG8(I2C_DR)
1.1494 +#define REG_I2C_CR REG8(I2C_CR)
1.1495 +#define REG_I2C_SR REG8(I2C_SR)
1.1496 +#define REG_I2C_GR REG16(I2C_GR)
1.1497 +
1.1498 +/* I2C Control Register (I2C_CR) */
1.1499 +
1.1500 +#define I2C_CR_IEN (1 << 4)
1.1501 +#define I2C_CR_STA (1 << 3)
1.1502 +#define I2C_CR_STO (1 << 2)
1.1503 +#define I2C_CR_AC (1 << 1)
1.1504 +#define I2C_CR_I2CE (1 << 0)
1.1505 +
1.1506 +/* I2C Status Register (I2C_SR) */
1.1507 +
1.1508 +#define I2C_SR_STX (1 << 4)
1.1509 +#define I2C_SR_BUSY (1 << 3)
1.1510 +#define I2C_SR_TEND (1 << 2)
1.1511 +#define I2C_SR_DRF (1 << 1)
1.1512 +#define I2C_SR_ACKF (1 << 0)
1.1513 +
1.1514 +
1.1515 +
1.1516 +
1.1517 +/*************************************************************************
1.1518 + * UDC
1.1519 + *************************************************************************/
1.1520 +#define UDC_EP0InCR (UDC_BASE + 0x00)
1.1521 +#define UDC_EP0InSR (UDC_BASE + 0x04)
1.1522 +#define UDC_EP0InBSR (UDC_BASE + 0x08)
1.1523 +#define UDC_EP0InMPSR (UDC_BASE + 0x0c)
1.1524 +#define UDC_EP0InDesR (UDC_BASE + 0x14)
1.1525 +#define UDC_EP1InCR (UDC_BASE + 0x20)
1.1526 +#define UDC_EP1InSR (UDC_BASE + 0x24)
1.1527 +#define UDC_EP1InBSR (UDC_BASE + 0x28)
1.1528 +#define UDC_EP1InMPSR (UDC_BASE + 0x2c)
1.1529 +#define UDC_EP1InDesR (UDC_BASE + 0x34)
1.1530 +#define UDC_EP2InCR (UDC_BASE + 0x40)
1.1531 +#define UDC_EP2InSR (UDC_BASE + 0x44)
1.1532 +#define UDC_EP2InBSR (UDC_BASE + 0x48)
1.1533 +#define UDC_EP2InMPSR (UDC_BASE + 0x4c)
1.1534 +#define UDC_EP2InDesR (UDC_BASE + 0x54)
1.1535 +#define UDC_EP3InCR (UDC_BASE + 0x60)
1.1536 +#define UDC_EP3InSR (UDC_BASE + 0x64)
1.1537 +#define UDC_EP3InBSR (UDC_BASE + 0x68)
1.1538 +#define UDC_EP3InMPSR (UDC_BASE + 0x6c)
1.1539 +#define UDC_EP3InDesR (UDC_BASE + 0x74)
1.1540 +#define UDC_EP4InCR (UDC_BASE + 0x80)
1.1541 +#define UDC_EP4InSR (UDC_BASE + 0x84)
1.1542 +#define UDC_EP4InBSR (UDC_BASE + 0x88)
1.1543 +#define UDC_EP4InMPSR (UDC_BASE + 0x8c)
1.1544 +#define UDC_EP4InDesR (UDC_BASE + 0x94)
1.1545 +
1.1546 +#define UDC_EP0OutCR (UDC_BASE + 0x200)
1.1547 +#define UDC_EP0OutSR (UDC_BASE + 0x204)
1.1548 +#define UDC_EP0OutPFNR (UDC_BASE + 0x208)
1.1549 +#define UDC_EP0OutMPSR (UDC_BASE + 0x20c)
1.1550 +#define UDC_EP0OutSBPR (UDC_BASE + 0x210)
1.1551 +#define UDC_EP0OutDesR (UDC_BASE + 0x214)
1.1552 +#define UDC_EP5OutCR (UDC_BASE + 0x2a0)
1.1553 +#define UDC_EP5OutSR (UDC_BASE + 0x2a4)
1.1554 +#define UDC_EP5OutPFNR (UDC_BASE + 0x2a8)
1.1555 +#define UDC_EP5OutMPSR (UDC_BASE + 0x2ac)
1.1556 +#define UDC_EP5OutDesR (UDC_BASE + 0x2b4)
1.1557 +#define UDC_EP6OutCR (UDC_BASE + 0x2c0)
1.1558 +#define UDC_EP6OutSR (UDC_BASE + 0x2c4)
1.1559 +#define UDC_EP6OutPFNR (UDC_BASE + 0x2c8)
1.1560 +#define UDC_EP6OutMPSR (UDC_BASE + 0x2cc)
1.1561 +#define UDC_EP6OutDesR (UDC_BASE + 0x2d4)
1.1562 +#define UDC_EP7OutCR (UDC_BASE + 0x2e0)
1.1563 +#define UDC_EP7OutSR (UDC_BASE + 0x2e4)
1.1564 +#define UDC_EP7OutPFNR (UDC_BASE + 0x2e8)
1.1565 +#define UDC_EP7OutMPSR (UDC_BASE + 0x2ec)
1.1566 +#define UDC_EP7OutDesR (UDC_BASE + 0x2f4)
1.1567 +
1.1568 +#define UDC_DevCFGR (UDC_BASE + 0x400)
1.1569 +#define UDC_DevCR (UDC_BASE + 0x404)
1.1570 +#define UDC_DevSR (UDC_BASE + 0x408)
1.1571 +#define UDC_DevIntR (UDC_BASE + 0x40c)
1.1572 +#define UDC_DevIntMR (UDC_BASE + 0x410)
1.1573 +#define UDC_EPIntR (UDC_BASE + 0x414)
1.1574 +#define UDC_EPIntMR (UDC_BASE + 0x418)
1.1575 +
1.1576 +#define UDC_STCMAR (UDC_BASE + 0x500)
1.1577 +#define UDC_EP0InfR (UDC_BASE + 0x504)
1.1578 +#define UDC_EP1InfR (UDC_BASE + 0x508)
1.1579 +#define UDC_EP2InfR (UDC_BASE + 0x50c)
1.1580 +#define UDC_EP3InfR (UDC_BASE + 0x510)
1.1581 +#define UDC_EP4InfR (UDC_BASE + 0x514)
1.1582 +#define UDC_EP5InfR (UDC_BASE + 0x518)
1.1583 +#define UDC_EP6InfR (UDC_BASE + 0x51c)
1.1584 +#define UDC_EP7InfR (UDC_BASE + 0x520)
1.1585 +
1.1586 +#define UDC_TXCONFIRM (UDC_BASE + 0x41C)
1.1587 +#define UDC_TXZLP (UDC_BASE + 0x420)
1.1588 +#define UDC_RXCONFIRM (UDC_BASE + 0x41C)
1.1589 +
1.1590 +#define UDC_RXFIFO (UDC_BASE + 0x800)
1.1591 +#define UDC_TXFIFOEP0 (UDC_BASE + 0x840)
1.1592 +
1.1593 +#define REG_UDC_EP0InCR REG32(UDC_EP0InCR)
1.1594 +#define REG_UDC_EP0InSR REG32(UDC_EP0InSR)
1.1595 +#define REG_UDC_EP0InBSR REG32(UDC_EP0InBSR)
1.1596 +#define REG_UDC_EP0InMPSR REG32(UDC_EP0InMPSR)
1.1597 +#define REG_UDC_EP0InDesR REG32(UDC_EP0InDesR)
1.1598 +#define REG_UDC_EP1InCR REG32(UDC_EP1InCR)
1.1599 +#define REG_UDC_EP1InSR REG32(UDC_EP1InSR)
1.1600 +#define REG_UDC_EP1InBSR REG32(UDC_EP1InBSR)
1.1601 +#define REG_UDC_EP1InMPSR REG32(UDC_EP1InMPSR)
1.1602 +#define REG_UDC_EP1InDesR REG32(UDC_EP1InDesR)
1.1603 +#define REG_UDC_EP2InCR REG32(UDC_EP2InCR)
1.1604 +#define REG_UDC_EP2InSR REG32(UDC_EP2InSR)
1.1605 +#define REG_UDC_EP2InBSR REG32(UDC_EP2InBSR)
1.1606 +#define REG_UDC_EP2InMPSR REG32(UDC_EP2InMPSR)
1.1607 +#define REG_UDC_EP2InDesR REG32(UDC_EP2InDesR)
1.1608 +#define REG_UDC_EP3InCR REG32(UDC_EP3InCR)
1.1609 +#define REG_UDC_EP3InSR REG32(UDC_EP3InSR)
1.1610 +#define REG_UDC_EP3InBSR REG32(UDC_EP3InBSR)
1.1611 +#define REG_UDC_EP3InMPSR REG32(UDC_EP3InMPSR)
1.1612 +#define REG_UDC_EP3InDesR REG32(UDC_EP3InDesR)
1.1613 +#define REG_UDC_EP4InCR REG32(UDC_EP4InCR)
1.1614 +#define REG_UDC_EP4InSR REG32(UDC_EP4InSR)
1.1615 +#define REG_UDC_EP4InBSR REG32(UDC_EP4InBSR)
1.1616 +#define REG_UDC_EP4InMPSR REG32(UDC_EP4InMPSR)
1.1617 +#define REG_UDC_EP4InDesR REG32(UDC_EP4InDesR)
1.1618 +
1.1619 +#define REG_UDC_EP0OutCR REG32(UDC_EP0OutCR)
1.1620 +#define REG_UDC_EP0OutSR REG32(UDC_EP0OutSR)
1.1621 +#define REG_UDC_EP0OutPFNR REG32(UDC_EP0OutPFNR)
1.1622 +#define REG_UDC_EP0OutMPSR REG32(UDC_EP0OutMPSR)
1.1623 +#define REG_UDC_EP0OutSBPR REG32(UDC_EP0OutSBPR)
1.1624 +#define REG_UDC_EP0OutDesR REG32(UDC_EP0OutDesR)
1.1625 +#define REG_UDC_EP5OutCR REG32(UDC_EP5OutCR)
1.1626 +#define REG_UDC_EP5OutSR REG32(UDC_EP5OutSR)
1.1627 +#define REG_UDC_EP5OutPFNR REG32(UDC_EP5OutPFNR)
1.1628 +#define REG_UDC_EP5OutMPSR REG32(UDC_EP5OutMPSR)
1.1629 +#define REG_UDC_EP5OutDesR REG32(UDC_EP5OutDesR)
1.1630 +#define REG_UDC_EP6OutCR REG32(UDC_EP6OutCR)
1.1631 +#define REG_UDC_EP6OutSR REG32(UDC_EP6OutSR)
1.1632 +#define REG_UDC_EP6OutPFNR REG32(UDC_EP6OutPFNR)
1.1633 +#define REG_UDC_EP6OutMPSR REG32(UDC_EP6OutMPSR)
1.1634 +#define REG_UDC_EP6OutDesR REG32(UDC_EP6OutDesR)
1.1635 +#define REG_UDC_EP7OutCR REG32(UDC_EP7OutCR)
1.1636 +#define REG_UDC_EP7OutSR REG32(UDC_EP7OutSR)
1.1637 +#define REG_UDC_EP7OutPFNR REG32(UDC_EP7OutPFNR)
1.1638 +#define REG_UDC_EP7OutMPSR REG32(UDC_EP7OutMPSR)
1.1639 +#define REG_UDC_EP7OutDesR REG32(UDC_EP7OutDesR)
1.1640 +
1.1641 +#define REG_UDC_DevCFGR REG32(UDC_DevCFGR)
1.1642 +#define REG_UDC_DevCR REG32(UDC_DevCR)
1.1643 +#define REG_UDC_DevSR REG32(UDC_DevSR)
1.1644 +#define REG_UDC_DevIntR REG32(UDC_DevIntR)
1.1645 +#define REG_UDC_DevIntMR REG32(UDC_DevIntMR)
1.1646 +#define REG_UDC_EPIntR REG32(UDC_EPIntR)
1.1647 +#define REG_UDC_EPIntMR REG32(UDC_EPIntMR)
1.1648 +
1.1649 +#define REG_UDC_STCMAR REG32(UDC_STCMAR)
1.1650 +#define REG_UDC_EP0InfR REG32(UDC_EP0InfR)
1.1651 +#define REG_UDC_EP1InfR REG32(UDC_EP1InfR)
1.1652 +#define REG_UDC_EP2InfR REG32(UDC_EP2InfR)
1.1653 +#define REG_UDC_EP3InfR REG32(UDC_EP3InfR)
1.1654 +#define REG_UDC_EP4InfR REG32(UDC_EP4InfR)
1.1655 +#define REG_UDC_EP5InfR REG32(UDC_EP5InfR)
1.1656 +#define REG_UDC_EP6InfR REG32(UDC_EP6InfR)
1.1657 +#define REG_UDC_EP7InfR REG32(UDC_EP7InfR)
1.1658 +
1.1659 +#define UDC_DevCFGR_PI (1 << 5)
1.1660 +#define UDC_DevCFGR_SS (1 << 4)
1.1661 +#define UDC_DevCFGR_SP (1 << 3)
1.1662 +#define UDC_DevCFGR_RW (1 << 2)
1.1663 +#define UDC_DevCFGR_SPD_BIT 0
1.1664 +#define UDC_DevCFGR_SPD_MASK (0x03 << UDC_DevCFGR_SPD_BIT)
1.1665 + #define UDC_DevCFGR_SPD_HS (0 << UDC_DevCFGR_SPD_BIT)
1.1666 + #define UDC_DevCFGR_SPD_LS (2 << UDC_DevCFGR_SPD_BIT)
1.1667 + #define UDC_DevCFGR_SPD_FS (3 << UDC_DevCFGR_SPD_BIT)
1.1668 +
1.1669 +#define UDC_DevCR_DM (1 << 9)
1.1670 +#define UDC_DevCR_BE (1 << 5)
1.1671 +#define UDC_DevCR_RES (1 << 0)
1.1672 +
1.1673 +#define UDC_DevSR_ENUMSPD_BIT 13
1.1674 +#define UDC_DevSR_ENUMSPD_MASK (0x03 << UDC_DevSR_ENUMSPD_BIT)
1.1675 + #define UDC_DevSR_ENUMSPD_HS (0 << UDC_DevSR_ENUMSPD_BIT)
1.1676 + #define UDC_DevSR_ENUMSPD_LS (2 << UDC_DevSR_ENUMSPD_BIT)
1.1677 + #define UDC_DevSR_ENUMSPD_FS (3 << UDC_DevSR_ENUMSPD_BIT)
1.1678 +#define UDC_DevSR_SUSP (1 << 12)
1.1679 +#define UDC_DevSR_ALT_BIT 8
1.1680 +#define UDC_DevSR_ALT_MASK (0x0f << UDC_DevSR_ALT_BIT)
1.1681 +#define UDC_DevSR_INTF_BIT 4
1.1682 +#define UDC_DevSR_INTF_MASK (0x0f << UDC_DevSR_INTF_BIT)
1.1683 +#define UDC_DevSR_CFG_BIT 0
1.1684 +#define UDC_DevSR_CFG_MASK (0x0f << UDC_DevSR_CFG_BIT)
1.1685 +
1.1686 +#define UDC_DevIntR_ENUM (1 << 6)
1.1687 +#define UDC_DevIntR_SOF (1 << 5)
1.1688 +#define UDC_DevIntR_US (1 << 4)
1.1689 +#define UDC_DevIntR_UR (1 << 3)
1.1690 +#define UDC_DevIntR_SI (1 << 1)
1.1691 +#define UDC_DevIntR_SC (1 << 0)
1.1692 +
1.1693 +#define UDC_EPIntR_OUTEP_BIT 16
1.1694 +#define UDC_EPIntR_OUTEP_MASK (0xffff << UDC_EPIntR_OUTEP_BIT)
1.1695 +#define UDC_EPIntR_OUTEP0 0x00010000
1.1696 +#define UDC_EPIntR_OUTEP5 0x00200000
1.1697 +#define UDC_EPIntR_OUTEP6 0x00400000
1.1698 +#define UDC_EPIntR_OUTEP7 0x00800000
1.1699 +#define UDC_EPIntR_INEP_BIT 0
1.1700 +#define UDC_EPIntR_INEP_MASK (0xffff << UDC_EPIntR_INEP_BIT)
1.1701 +#define UDC_EPIntR_INEP0 0x00000001
1.1702 +#define UDC_EPIntR_INEP1 0x00000002
1.1703 +#define UDC_EPIntR_INEP2 0x00000004
1.1704 +#define UDC_EPIntR_INEP3 0x00000008
1.1705 +#define UDC_EPIntR_INEP4 0x00000010
1.1706 +
1.1707 +
1.1708 +#define UDC_EPIntMR_OUTEP_BIT 16
1.1709 +#define UDC_EPIntMR_OUTEP_MASK (0xffff << UDC_EPIntMR_OUTEP_BIT)
1.1710 +#define UDC_EPIntMR_INEP_BIT 0
1.1711 +#define UDC_EPIntMR_INEP_MASK (0xffff << UDC_EPIntMR_INEP_BIT)
1.1712 +
1.1713 +#define UDC_EPCR_ET_BIT 4
1.1714 +#define UDC_EPCR_ET_MASK (0x03 << UDC_EPCR_ET_BIT)
1.1715 + #define UDC_EPCR_ET_CTRL (0 << UDC_EPCR_ET_BIT)
1.1716 + #define UDC_EPCR_ET_ISO (1 << UDC_EPCR_ET_BIT)
1.1717 + #define UDC_EPCR_ET_BULK (2 << UDC_EPCR_ET_BIT)
1.1718 + #define UDC_EPCR_ET_INTR (3 << UDC_EPCR_ET_BIT)
1.1719 +#define UDC_EPCR_SN (1 << 2)
1.1720 +#define UDC_EPCR_F (1 << 1)
1.1721 +#define UDC_EPCR_S (1 << 0)
1.1722 +
1.1723 +#define UDC_EPSR_RXPKTSIZE_BIT 11
1.1724 +#define UDC_EPSR_RXPKTSIZE_MASK (0x7ff << UDC_EPSR_RXPKTSIZE_BIT)
1.1725 +#define UDC_EPSR_IN (1 << 6)
1.1726 +#define UDC_EPSR_OUT_BIT 4
1.1727 +#define UDC_EPSR_OUT_MASK (0x03 << UDC_EPSR_OUT_BIT)
1.1728 + #define UDC_EPSR_OUT_NONE (0 << UDC_EPSR_OUT_BIT)
1.1729 + #define UDC_EPSR_OUT_RCVDATA (1 << UDC_EPSR_OUT_BIT)
1.1730 + #define UDC_EPSR_OUT_RCVSETUP (2 << UDC_EPSR_OUT_BIT)
1.1731 +#define UDC_EPSR_PID_BIT 0
1.1732 +#define UDC_EPSR_PID_MASK (0x0f << UDC_EPSR_PID_BIT)
1.1733 +
1.1734 +#define UDC_EPInfR_MPS_BIT 19
1.1735 +#define UDC_EPInfR_MPS_MASK (0x3ff << UDC_EPInfR_MPS_BIT)
1.1736 +#define UDC_EPInfR_ALTS_BIT 15
1.1737 +#define UDC_EPInfR_ALTS_MASK (0x0f << UDC_EPInfR_ALTS_BIT)
1.1738 +#define UDC_EPInfR_IFN_BIT 11
1.1739 +#define UDC_EPInfR_IFN_MASK (0x0f << UDC_EPInfR_IFN_BIT)
1.1740 +#define UDC_EPInfR_CGN_BIT 7
1.1741 +#define UDC_EPInfR_CGN_MASK (0x0f << UDC_EPInfR_CGN_BIT)
1.1742 +#define UDC_EPInfR_EPT_BIT 5
1.1743 +#define UDC_EPInfR_EPT_MASK (0x03 << UDC_EPInfR_EPT_BIT)
1.1744 + #define UDC_EPInfR_EPT_CTRL (0 << UDC_EPInfR_EPT_BIT)
1.1745 + #define UDC_EPInfR_EPT_ISO (1 << UDC_EPInfR_EPT_BIT)
1.1746 + #define UDC_EPInfR_EPT_BULK (2 << UDC_EPInfR_EPT_BIT)
1.1747 + #define UDC_EPInfR_EPT_INTR (3 << UDC_EPInfR_EPT_BIT)
1.1748 +#define UDC_EPInfR_EPD (1 << 4)
1.1749 + #define UDC_EPInfR_EPD_OUT (0 << 4)
1.1750 + #define UDC_EPInfR_EPD_IN (1 << 4)
1.1751 +
1.1752 +#define UDC_EPInfR_EPN_BIT 0
1.1753 +#define UDC_EPInfR_EPN_MASK (0xf << UDC_EPInfR_EPN_BIT)
1.1754 +
1.1755 +
1.1756 +
1.1757 +
1.1758 +/*************************************************************************
1.1759 + * DMAC
1.1760 + *************************************************************************/
1.1761 +#define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20))
1.1762 +#define DMAC_DDAR(n) (DMAC_BASE + (0x04 + (n) * 0x20))
1.1763 +#define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20))
1.1764 +#define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20))
1.1765 +#define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20))
1.1766 +#define DMAC_DMAIPR (DMAC_BASE + 0xf8)
1.1767 +#define DMAC_DMACR (DMAC_BASE + 0xfc)
1.1768 +
1.1769 +#define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n)))
1.1770 +#define REG_DMAC_DDAR(n) REG32(DMAC_DDAR((n)))
1.1771 +#define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n)))
1.1772 +#define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n)))
1.1773 +#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n)))
1.1774 +#define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR)
1.1775 +#define REG_DMAC_DMACR REG32(DMAC_DMACR)
1.1776 +
1.1777 +#define DMAC_DRSR_RS_BIT 0
1.1778 +#define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT)
1.1779 + #define DMAC_DRSR_RS_EXTREXTR (0 << DMAC_DRSR_RS_BIT)
1.1780 + #define DMAC_DRSR_RS_PCMCIAOUT (4 << DMAC_DRSR_RS_BIT)
1.1781 + #define DMAC_DRSR_RS_PCMCIAIN (5 << DMAC_DRSR_RS_BIT)
1.1782 + #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT)
1.1783 + #define DMAC_DRSR_RS_DESOUT (10 << DMAC_DRSR_RS_BIT)
1.1784 + #define DMAC_DRSR_RS_DESIN (11 << DMAC_DRSR_RS_BIT)
1.1785 + #define DMAC_DRSR_RS_UART3OUT (14 << DMAC_DRSR_RS_BIT)
1.1786 + #define DMAC_DRSR_RS_UART3IN (15 << DMAC_DRSR_RS_BIT)
1.1787 + #define DMAC_DRSR_RS_UART2OUT (16 << DMAC_DRSR_RS_BIT)
1.1788 + #define DMAC_DRSR_RS_UART2IN (17 << DMAC_DRSR_RS_BIT)
1.1789 + #define DMAC_DRSR_RS_UART1OUT (18 << DMAC_DRSR_RS_BIT)
1.1790 + #define DMAC_DRSR_RS_UART1IN (19 << DMAC_DRSR_RS_BIT)
1.1791 + #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT)
1.1792 + #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT)
1.1793 + #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT)
1.1794 + #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT)
1.1795 + #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT)
1.1796 + #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT)
1.1797 + #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT)
1.1798 + #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT)
1.1799 + #define DMAC_DRSR_RS_OST2 (28 << DMAC_DRSR_RS_BIT)
1.1800 +
1.1801 +#define DMAC_DCCSR_EACKS (1 << 31)
1.1802 +#define DMAC_DCCSR_EACKM (1 << 30)
1.1803 +#define DMAC_DCCSR_ERDM_BIT 28
1.1804 +#define DMAC_DCCSR_ERDM_MASK (0x03 << DMAC_DCCSR_ERDM_BIT)
1.1805 + #define DMAC_DCCSR_ERDM_LLEVEL (0 << DMAC_DCCSR_ERDM_BIT)
1.1806 + #define DMAC_DCCSR_ERDM_FEDGE (1 << DMAC_DCCSR_ERDM_BIT)
1.1807 + #define DMAC_DCCSR_ERDM_HLEVEL (2 << DMAC_DCCSR_ERDM_BIT)
1.1808 + #define DMAC_DCCSR_ERDM_REDGE (3 << DMAC_DCCSR_ERDM_BIT)
1.1809 +#define DMAC_DCCSR_EOPM (1 << 27)
1.1810 +#define DMAC_DCCSR_SAM (1 << 23)
1.1811 +#define DMAC_DCCSR_DAM (1 << 22)
1.1812 +#define DMAC_DCCSR_RDIL_BIT 16
1.1813 +#define DMAC_DCCSR_RDIL_MASK (0x0f << DMAC_DCCSR_RDIL_BIT)
1.1814 + #define DMAC_DCCSR_RDIL_IGN (0 << DMAC_DCCSR_RDIL_BIT)
1.1815 + #define DMAC_DCCSR_RDIL_2 (1 << DMAC_DCCSR_RDIL_BIT)
1.1816 + #define DMAC_DCCSR_RDIL_4 (2 << DMAC_DCCSR_RDIL_BIT)
1.1817 + #define DMAC_DCCSR_RDIL_8 (3 << DMAC_DCCSR_RDIL_BIT)
1.1818 + #define DMAC_DCCSR_RDIL_12 (4 << DMAC_DCCSR_RDIL_BIT)
1.1819 + #define DMAC_DCCSR_RDIL_16 (5 << DMAC_DCCSR_RDIL_BIT)
1.1820 + #define DMAC_DCCSR_RDIL_20 (6 << DMAC_DCCSR_RDIL_BIT)
1.1821 + #define DMAC_DCCSR_RDIL_24 (7 << DMAC_DCCSR_RDIL_BIT)
1.1822 + #define DMAC_DCCSR_RDIL_28 (8 << DMAC_DCCSR_RDIL_BIT)
1.1823 + #define DMAC_DCCSR_RDIL_32 (9 << DMAC_DCCSR_RDIL_BIT)
1.1824 + #define DMAC_DCCSR_RDIL_48 (10 << DMAC_DCCSR_RDIL_BIT)
1.1825 + #define DMAC_DCCSR_RDIL_60 (11 << DMAC_DCCSR_RDIL_BIT)
1.1826 + #define DMAC_DCCSR_RDIL_64 (12 << DMAC_DCCSR_RDIL_BIT)
1.1827 + #define DMAC_DCCSR_RDIL_124 (13 << DMAC_DCCSR_RDIL_BIT)
1.1828 + #define DMAC_DCCSR_RDIL_128 (14 << DMAC_DCCSR_RDIL_BIT)
1.1829 + #define DMAC_DCCSR_RDIL_200 (15 << DMAC_DCCSR_RDIL_BIT)
1.1830 +#define DMAC_DCCSR_SWDH_BIT 14
1.1831 +#define DMAC_DCCSR_SWDH_MASK (0x03 << DMAC_DCCSR_SWDH_BIT)
1.1832 + #define DMAC_DCCSR_SWDH_32 (0 << DMAC_DCCSR_SWDH_BIT)
1.1833 + #define DMAC_DCCSR_SWDH_8 (1 << DMAC_DCCSR_SWDH_BIT)
1.1834 + #define DMAC_DCCSR_SWDH_16 (2 << DMAC_DCCSR_SWDH_BIT)
1.1835 +#define DMAC_DCCSR_DWDH_BIT 12
1.1836 +#define DMAC_DCCSR_DWDH_MASK (0x03 << DMAC_DCCSR_DWDH_BIT)
1.1837 + #define DMAC_DCCSR_DWDH_32 (0 << DMAC_DCCSR_DWDH_BIT)
1.1838 + #define DMAC_DCCSR_DWDH_8 (1 << DMAC_DCCSR_DWDH_BIT)
1.1839 + #define DMAC_DCCSR_DWDH_16 (2 << DMAC_DCCSR_DWDH_BIT)
1.1840 +#define DMAC_DCCSR_DS_BIT 8
1.1841 +#define DMAC_DCCSR_DS_MASK (0x07 << DMAC_DCCSR_DS_BIT)
1.1842 + #define DMAC_DCCSR_DS_32b (0 << DMAC_DCCSR_DS_BIT)
1.1843 + #define DMAC_DCCSR_DS_8b (1 << DMAC_DCCSR_DS_BIT)
1.1844 + #define DMAC_DCCSR_DS_16b (2 << DMAC_DCCSR_DS_BIT)
1.1845 + #define DMAC_DCCSR_DS_16B (3 << DMAC_DCCSR_DS_BIT)
1.1846 + #define DMAC_DCCSR_DS_32B (4 << DMAC_DCCSR_DS_BIT)
1.1847 +#define DMAC_DCCSR_TM (1 << 7)
1.1848 +#define DMAC_DCCSR_AR (1 << 4)
1.1849 +#define DMAC_DCCSR_TC (1 << 3)
1.1850 +#define DMAC_DCCSR_HLT (1 << 2)
1.1851 +#define DMAC_DCCSR_TCIE (1 << 1)
1.1852 +#define DMAC_DCCSR_CHDE (1 << 0)
1.1853 +
1.1854 +#define DMAC_DMAIPR_CINT_BIT 8
1.1855 +#define DMAC_DMAIPR_CINT_MASK (0xff << DMAC_DMAIPR_CINT_BIT)
1.1856 +
1.1857 +#define DMAC_DMACR_PR_BIT 8
1.1858 +#define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT)
1.1859 + #define DMAC_DMACR_PR_01234567 (0 << DMAC_DMACR_PR_BIT)
1.1860 + #define DMAC_DMACR_PR_02314675 (1 << DMAC_DMACR_PR_BIT)
1.1861 + #define DMAC_DMACR_PR_20136457 (2 << DMAC_DMACR_PR_BIT)
1.1862 + #define DMAC_DMACR_PR_ROUNDROBIN (3 << DMAC_DMACR_PR_BIT)
1.1863 +#define DMAC_DMACR_HTR (1 << 3)
1.1864 +#define DMAC_DMACR_AER (1 << 2)
1.1865 +#define DMAC_DMACR_DME (1 << 0)
1.1866 +
1.1867 +#define IRQ_DMA_0 32
1.1868 +#define NUM_DMA 6
1.1869 +
1.1870 +
1.1871 +/*************************************************************************
1.1872 + * AIC
1.1873 + *************************************************************************/
1.1874 +#define AIC_FR (AIC_BASE + 0x000)
1.1875 +#define AIC_CR (AIC_BASE + 0x004)
1.1876 +#define AIC_ACCR1 (AIC_BASE + 0x008)
1.1877 +#define AIC_ACCR2 (AIC_BASE + 0x00C)
1.1878 +#define AIC_I2SCR (AIC_BASE + 0x010)
1.1879 +#define AIC_SR (AIC_BASE + 0x014)
1.1880 +#define AIC_ACSR (AIC_BASE + 0x018)
1.1881 +#define AIC_I2SSR (AIC_BASE + 0x01C)
1.1882 +#define AIC_ACCAR (AIC_BASE + 0x020)
1.1883 +#define AIC_ACCDR (AIC_BASE + 0x024)
1.1884 +#define AIC_ACSAR (AIC_BASE + 0x028)
1.1885 +#define AIC_ACSDR (AIC_BASE + 0x02C)
1.1886 +#define AIC_I2SDIV (AIC_BASE + 0x030)
1.1887 +#define AIC_DR (AIC_BASE + 0x034)
1.1888 +
1.1889 +#define REG_AIC_FR REG32(AIC_FR)
1.1890 +#define REG_AIC_CR REG32(AIC_CR)
1.1891 +#define REG_AIC_ACCR1 REG32(AIC_ACCR1)
1.1892 +#define REG_AIC_ACCR2 REG32(AIC_ACCR2)
1.1893 +#define REG_AIC_I2SCR REG32(AIC_I2SCR)
1.1894 +#define REG_AIC_SR REG32(AIC_SR)
1.1895 +#define REG_AIC_ACSR REG32(AIC_ACSR)
1.1896 +#define REG_AIC_I2SSR REG32(AIC_I2SSR)
1.1897 +#define REG_AIC_ACCAR REG32(AIC_ACCAR)
1.1898 +#define REG_AIC_ACCDR REG32(AIC_ACCDR)
1.1899 +#define REG_AIC_ACSAR REG32(AIC_ACSAR)
1.1900 +#define REG_AIC_ACSDR REG32(AIC_ACSDR)
1.1901 +#define REG_AIC_I2SDIV REG32(AIC_I2SDIV)
1.1902 +#define REG_AIC_DR REG32(AIC_DR)
1.1903 +
1.1904 +/* AIC Controller Configuration Register (AIC_FR) */
1.1905 +
1.1906 +#define AIC_FR_RFTH_BIT 12
1.1907 +#define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT)
1.1908 +#define AIC_FR_TFTH_BIT 8
1.1909 +#define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT)
1.1910 +#define AIC_FR_AUSEL (1 << 4)
1.1911 +#define AIC_FR_RST (1 << 3)
1.1912 +#define AIC_FR_BCKD (1 << 2)
1.1913 +#define AIC_FR_SYNCD (1 << 1)
1.1914 +#define AIC_FR_ENB (1 << 0)
1.1915 +
1.1916 +/* AIC Controller Common Control Register (AIC_CR) */
1.1917 +
1.1918 +#define AIC_CR_RDMS (1 << 15)
1.1919 +#define AIC_CR_TDMS (1 << 14)
1.1920 +#define AIC_CR_FLUSH (1 << 8)
1.1921 +#define AIC_CR_EROR (1 << 6)
1.1922 +#define AIC_CR_ETUR (1 << 5)
1.1923 +#define AIC_CR_ERFS (1 << 4)
1.1924 +#define AIC_CR_ETFS (1 << 3)
1.1925 +#define AIC_CR_ENLBF (1 << 2)
1.1926 +#define AIC_CR_ERPL (1 << 1)
1.1927 +#define AIC_CR_EREC (1 << 0)
1.1928 +
1.1929 +/* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */
1.1930 +
1.1931 +#define AIC_ACCR1_RS_BIT 16
1.1932 +#define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT)
1.1933 + #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */
1.1934 + #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */
1.1935 + #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */
1.1936 + #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit */
1.1937 + #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit */
1.1938 + #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit */
1.1939 + #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit */
1.1940 + #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */
1.1941 + #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit */
1.1942 + #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit */
1.1943 +#define AIC_ACCR1_XS_BIT 0
1.1944 +#define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT)
1.1945 + #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */
1.1946 + #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */
1.1947 + #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */
1.1948 + #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit */
1.1949 + #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit */
1.1950 + #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit */
1.1951 + #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit */
1.1952 + #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */
1.1953 + #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit */
1.1954 + #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit */
1.1955 +
1.1956 +/* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */
1.1957 +
1.1958 +#define AIC_ACCR2_ERSTO (1 << 18)
1.1959 +#define AIC_ACCR2_ESADR (1 << 17)
1.1960 +#define AIC_ACCR2_ECADT (1 << 16)
1.1961 +#define AIC_ACCR2_OASS_BIT 8
1.1962 +#define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT)
1.1963 + #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */
1.1964 + #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */
1.1965 + #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */
1.1966 + #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */
1.1967 +#define AIC_ACCR2_IASS_BIT 6
1.1968 +#define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT)
1.1969 + #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */
1.1970 + #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */
1.1971 + #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */
1.1972 + #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */
1.1973 +#define AIC_ACCR2_SO (1 << 3)
1.1974 +#define AIC_ACCR2_SR (1 << 2)
1.1975 +#define AIC_ACCR2_SS (1 << 1)
1.1976 +#define AIC_ACCR2_SA (1 << 0)
1.1977 +
1.1978 +/* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */
1.1979 +
1.1980 +#define AIC_I2SCR_STPBK (1 << 12)
1.1981 +#define AIC_I2SCR_WL_BIT 1
1.1982 +#define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT)
1.1983 + #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */
1.1984 + #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */
1.1985 + #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */
1.1986 + #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */
1.1987 + #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */
1.1988 +#define AIC_I2SCR_AMSL (1 << 0)
1.1989 +
1.1990 +/* AIC Controller FIFO Status Register (AIC_SR) */
1.1991 +
1.1992 +#define AIC_SR_RFL_BIT 24
1.1993 +#define AIC_SR_RFL_MASK (0x1f << AIC_SR_RFL_BIT)
1.1994 +#define AIC_SR_TFL_BIT 8
1.1995 +#define AIC_SR_TFL_MASK (0x1f << AIC_SR_TFL_BIT)
1.1996 +#define AIC_SR_ROR (1 << 6)
1.1997 +#define AIC_SR_TUR (1 << 5)
1.1998 +#define AIC_SR_RFS (1 << 4)
1.1999 +#define AIC_SR_TFS (1 << 3)
1.2000 +
1.2001 +/* AIC Controller AC-link Status Register (AIC_ACSR) */
1.2002 +
1.2003 +#define AIC_ACSR_CRDY (1 << 20)
1.2004 +#define AIC_ACSR_CLPM (1 << 19)
1.2005 +#define AIC_ACSR_RSTO (1 << 18)
1.2006 +#define AIC_ACSR_SADR (1 << 17)
1.2007 +#define AIC_ACSR_CADT (1 << 16)
1.2008 +
1.2009 +/* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */
1.2010 +
1.2011 +#define AIC_I2SSR_BSY (1 << 2)
1.2012 +
1.2013 +/* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */
1.2014 +
1.2015 +#define AIC_ACCAR_CAR_BIT 0
1.2016 +#define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT)
1.2017 +
1.2018 +/* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */
1.2019 +
1.2020 +#define AIC_ACCDR_CDR_BIT 0
1.2021 +#define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT)
1.2022 +
1.2023 +/* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */
1.2024 +
1.2025 +#define AIC_ACSAR_SAR_BIT 0
1.2026 +#define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT)
1.2027 +
1.2028 +/* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */
1.2029 +
1.2030 +#define AIC_ACSDR_SDR_BIT 0
1.2031 +#define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT)
1.2032 +
1.2033 +/* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */
1.2034 +
1.2035 +#define AIC_I2SDIV_DIV_BIT 0
1.2036 +#define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT)
1.2037 + #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */
1.2038 + #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */
1.2039 + #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */
1.2040 + #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */
1.2041 + #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */
1.2042 + #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */
1.2043 +
1.2044 +
1.2045 +
1.2046 +
1.2047 +/*************************************************************************
1.2048 + * LCD
1.2049 + *************************************************************************/
1.2050 +#define LCD_CFG (LCD_BASE + 0x00)
1.2051 +#define LCD_VSYNC (LCD_BASE + 0x04)
1.2052 +#define LCD_HSYNC (LCD_BASE + 0x08)
1.2053 +#define LCD_VAT (LCD_BASE + 0x0c)
1.2054 +#define LCD_DAH (LCD_BASE + 0x10)
1.2055 +#define LCD_DAV (LCD_BASE + 0x14)
1.2056 +#define LCD_PS (LCD_BASE + 0x18)
1.2057 +#define LCD_CLS (LCD_BASE + 0x1c)
1.2058 +#define LCD_SPL (LCD_BASE + 0x20)
1.2059 +#define LCD_REV (LCD_BASE + 0x24)
1.2060 +#define LCD_CTRL (LCD_BASE + 0x30)
1.2061 +#define LCD_STATE (LCD_BASE + 0x34)
1.2062 +#define LCD_IID (LCD_BASE + 0x38)
1.2063 +#define LCD_DA0 (LCD_BASE + 0x40)
1.2064 +#define LCD_SA0 (LCD_BASE + 0x44)
1.2065 +#define LCD_FID0 (LCD_BASE + 0x48)
1.2066 +#define LCD_CMD0 (LCD_BASE + 0x4c)
1.2067 +#define LCD_DA1 (LCD_BASE + 0x50)
1.2068 +#define LCD_SA1 (LCD_BASE + 0x54)
1.2069 +#define LCD_FID1 (LCD_BASE + 0x58)
1.2070 +#define LCD_CMD1 (LCD_BASE + 0x5c)
1.2071 +
1.2072 +#define REG_LCD_CFG REG32(LCD_CFG)
1.2073 +#define REG_LCD_VSYNC REG32(LCD_VSYNC)
1.2074 +#define REG_LCD_HSYNC REG32(LCD_HSYNC)
1.2075 +#define REG_LCD_VAT REG32(LCD_VAT)
1.2076 +#define REG_LCD_DAH REG32(LCD_DAH)
1.2077 +#define REG_LCD_DAV REG32(LCD_DAV)
1.2078 +#define REG_LCD_PS REG32(LCD_PS)
1.2079 +#define REG_LCD_CLS REG32(LCD_CLS)
1.2080 +#define REG_LCD_SPL REG32(LCD_SPL)
1.2081 +#define REG_LCD_REV REG32(LCD_REV)
1.2082 +#define REG_LCD_CTRL REG32(LCD_CTRL)
1.2083 +#define REG_LCD_STATE REG32(LCD_STATE)
1.2084 +#define REG_LCD_IID REG32(LCD_IID)
1.2085 +#define REG_LCD_DA0 REG32(LCD_DA0)
1.2086 +#define REG_LCD_SA0 REG32(LCD_SA0)
1.2087 +#define REG_LCD_FID0 REG32(LCD_FID0)
1.2088 +#define REG_LCD_CMD0 REG32(LCD_CMD0)
1.2089 +#define REG_LCD_DA1 REG32(LCD_DA1)
1.2090 +#define REG_LCD_SA1 REG32(LCD_SA1)
1.2091 +#define REG_LCD_FID1 REG32(LCD_FID1)
1.2092 +#define REG_LCD_CMD1 REG32(LCD_CMD1)
1.2093 +
1.2094 +#define LCD_CFG_PDW_BIT 4
1.2095 +#define LCD_CFG_PDW_MASK (0x03 << LCD_DEV_PDW_BIT)
1.2096 + #define LCD_CFG_PDW_1 (0 << LCD_DEV_PDW_BIT)
1.2097 + #define LCD_CFG_PDW_2 (1 << LCD_DEV_PDW_BIT)
1.2098 + #define LCD_CFG_PDW_4 (2 << LCD_DEV_PDW_BIT)
1.2099 + #define LCD_CFG_PDW_8 (3 << LCD_DEV_PDW_BIT)
1.2100 +#define LCD_CFG_MODE_BIT 0
1.2101 +#define LCD_CFG_MODE_MASK (0x0f << LCD_DEV_MODE_BIT)
1.2102 + #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_DEV_MODE_BIT)
1.2103 + #define LCD_CFG_MODE_SHARP_HR (1 << LCD_DEV_MODE_BIT)
1.2104 + #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_DEV_MODE_BIT)
1.2105 + #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_DEV_MODE_BIT)
1.2106 + #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_DEV_MODE_BIT)
1.2107 + #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_DEV_MODE_BIT)
1.2108 + #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_DEV_MODE_BIT)
1.2109 + #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_DEV_MODE_BIT)
1.2110 + #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_DEV_MODE_BIT)
1.2111 + #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_DEV_MODE_BIT)
1.2112 +
1.2113 +#define LCD_VSYNC_VPS_BIT 16
1.2114 +#define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT)
1.2115 +#define LCD_VSYNC_VPE_BIT 0
1.2116 +#define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT)
1.2117 +
1.2118 +#define LCD_HSYNC_HPS_BIT 16
1.2119 +#define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT)
1.2120 +#define LCD_HSYNC_HPE_BIT 0
1.2121 +#define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT)
1.2122 +
1.2123 +#define LCD_VAT_HT_BIT 16
1.2124 +#define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT)
1.2125 +#define LCD_VAT_VT_BIT 0
1.2126 +#define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT)
1.2127 +
1.2128 +#define LCD_DAH_HDS_BIT 16
1.2129 +#define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT)
1.2130 +#define LCD_DAH_HDE_BIT 0
1.2131 +#define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT)
1.2132 +
1.2133 +#define LCD_DAV_VDS_BIT 16
1.2134 +#define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT)
1.2135 +#define LCD_DAV_VDE_BIT 0
1.2136 +#define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT)
1.2137 +
1.2138 +#define LCD_CTRL_BST_BIT 28
1.2139 +#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT)
1.2140 + #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT)
1.2141 + #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT)
1.2142 + #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT)
1.2143 +#define LCD_CTRL_RGB555 (1 << 27)
1.2144 +#define LCD_CTRL_OFUP (1 << 26)
1.2145 +#define LCD_CTRL_FRC_BIT 24
1.2146 +#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT)
1.2147 + #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT)
1.2148 + #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT)
1.2149 + #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT)
1.2150 +#define LCD_CTRL_PDD_BIT 16
1.2151 +#define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT)
1.2152 +#define LCD_CTRL_EOFM (1 << 13)
1.2153 +#define LCD_CTRL_SOFM (1 << 12)
1.2154 +#define LCD_CTRL_OFUM (1 << 11)
1.2155 +#define LCD_CTRL_IFUM0 (1 << 10)
1.2156 +#define LCD_CTRL_IFUM1 (1 << 9)
1.2157 +#define LCD_CTRL_LDDM (1 << 8)
1.2158 +#define LCD_CTRL_QDM (1 << 7)
1.2159 +#define LCD_CTRL_BEDN (1 << 6)
1.2160 +#define LCD_CTRL_PEDN (1 << 5)
1.2161 +#define LCD_CTRL_DIS (1 << 4)
1.2162 +#define LCD_CTRL_ENA (1 << 3)
1.2163 +#define LCD_CTRL_BPP_BIT 0
1.2164 +#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT)
1.2165 + #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT)
1.2166 + #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT)
1.2167 + #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT)
1.2168 + #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT)
1.2169 + #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT)
1.2170 +
1.2171 +#define LCD_STATE_QD (1 << 7)
1.2172 +#define LCD_STATE_EOF (1 << 5)
1.2173 +#define LCD_STATE_SOF (1 << 4)
1.2174 +#define LCD_STATE_OFU (1 << 3)
1.2175 +#define LCD_STATE_IFU0 (1 << 2)
1.2176 +#define LCD_STATE_IFU1 (1 << 1)
1.2177 +#define LCD_STATE_LDD (1 << 0)
1.2178 +
1.2179 +#define LCD_CMD_SOFINT (1 << 31)
1.2180 +#define LCD_CMD_EOFINT (1 << 30)
1.2181 +#define LCD_CMD_PAL (1 << 28)
1.2182 +#define LCD_CMD_LEN_BIT 0
1.2183 +#define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT)
1.2184 +
1.2185 +
1.2186 +
1.2187 +
1.2188 +/*************************************************************************
1.2189 + * DES
1.2190 + *************************************************************************/
1.2191 +#define DES_CR1 (DES_BASE + 0x000)
1.2192 +#define DES_CR2 (DES_BASE + 0x004)
1.2193 +#define DES_SR (DES_BASE + 0x008)
1.2194 +#define DES_K1L (DES_BASE + 0x010)
1.2195 +#define DES_K1R (DES_BASE + 0x014)
1.2196 +#define DES_K2L (DES_BASE + 0x018)
1.2197 +#define DES_K2R (DES_BASE + 0x01C)
1.2198 +#define DES_K3L (DES_BASE + 0x020)
1.2199 +#define DES_K3R (DES_BASE + 0x024)
1.2200 +#define DES_IVL (DES_BASE + 0x028)
1.2201 +#define DES_IVR (DES_BASE + 0x02C)
1.2202 +#define DES_DIN (DES_BASE + 0x030)
1.2203 +#define DES_DOUT (DES_BASE + 0x034)
1.2204 +
1.2205 +#define REG_DES_CR1 REG32(DES_CR1)
1.2206 +#define REG_DES_CR2 REG32(DES_CR2)
1.2207 +#define REG_DES_SR REG32(DES_SR)
1.2208 +#define REG_DES_K1L REG32(DES_K1L)
1.2209 +#define REG_DES_K1R REG32(DES_K1R)
1.2210 +#define REG_DES_K2L REG32(DES_K2L)
1.2211 +#define REG_DES_K2R REG32(DES_K2R)
1.2212 +#define REG_DES_K3L REG32(DES_K3L)
1.2213 +#define REG_DES_K3R REG32(DES_K3R)
1.2214 +#define REG_DES_IVL REG32(DES_IVL)
1.2215 +#define REG_DES_IVR REG32(DES_IVR)
1.2216 +#define REG_DES_DIN REG32(DES_DIN)
1.2217 +#define REG_DES_DOUT REG32(DES_DOUT)
1.2218 +
1.2219 +/* DES Control Register 1 (DES_CR1) */
1.2220 +
1.2221 +#define DES_CR1_EN (1 << 0)
1.2222 +
1.2223 +/* DES Control Register 2 (DES_CR2) */
1.2224 +
1.2225 +#define DES_CR2_ENDEC (1 << 3)
1.2226 +#define DES_CR2_MODE (1 << 2)
1.2227 +#define DES_CR2_ALG (1 << 1)
1.2228 +#define DES_CR2_DMAE (1 << 0)
1.2229 +
1.2230 +/* DES State Register (DES_SR) */
1.2231 +
1.2232 +#define DES_SR_IN_FULL (1 << 5)
1.2233 +#define DES_SR_IN_LHF (1 << 4)
1.2234 +#define DES_SR_IN_EMPTY (1 << 3)
1.2235 +#define DES_SR_OUT_FULL (1 << 2)
1.2236 +#define DES_SR_OUT_GHF (1 << 1)
1.2237 +#define DES_SR_OUT_EMPTY (1 << 0)
1.2238 +
1.2239 +
1.2240 +
1.2241 +
1.2242 +/*************************************************************************
1.2243 + * CPM
1.2244 + *************************************************************************/
1.2245 +#define CPM_CFCR (CPM_BASE+0x00)
1.2246 +#define CPM_PLCR1 (CPM_BASE+0x10)
1.2247 +#define CPM_OCR (CPM_BASE+0x1c)
1.2248 +#define CPM_CFCR2 (CPM_BASE+0x60)
1.2249 +#define CPM_LPCR (CPM_BASE+0x04)
1.2250 +#define CPM_RSTR (CPM_BASE+0x08)
1.2251 +#define CPM_MSCR (CPM_BASE+0x20)
1.2252 +#define CPM_SCR (CPM_BASE+0x24)
1.2253 +#define CPM_WRER (CPM_BASE+0x28)
1.2254 +#define CPM_WFER (CPM_BASE+0x2c)
1.2255 +#define CPM_WER (CPM_BASE+0x30)
1.2256 +#define CPM_WSR (CPM_BASE+0x34)
1.2257 +#define CPM_GSR0 (CPM_BASE+0x38)
1.2258 +#define CPM_GSR1 (CPM_BASE+0x3c)
1.2259 +#define CPM_GSR2 (CPM_BASE+0x40)
1.2260 +#define CPM_SPR (CPM_BASE+0x44)
1.2261 +#define CPM_GSR3 (CPM_BASE+0x48)
1.2262 +
1.2263 +#define REG_CPM_CFCR REG32(CPM_CFCR)
1.2264 +#define REG_CPM_PLCR1 REG32(CPM_PLCR1)
1.2265 +#define REG_CPM_OCR REG32(CPM_OCR)
1.2266 +#define REG_CPM_CFCR2 REG32(CPM_CFCR2)
1.2267 +#define REG_CPM_LPCR REG32(CPM_LPCR)
1.2268 +#define REG_CPM_RSTR REG32(CPM_RSTR)
1.2269 +#define REG_CPM_MSCR REG32(CPM_MSCR)
1.2270 +#define REG_CPM_SCR REG32(CPM_SCR)
1.2271 +#define REG_CPM_WRER REG32(CPM_WRER)
1.2272 +#define REG_CPM_WFER REG32(CPM_WFER)
1.2273 +#define REG_CPM_WER REG32(CPM_WER)
1.2274 +#define REG_CPM_WSR REG32(CPM_WSR)
1.2275 +#define REG_CPM_GSR0 REG32(CPM_GSR0)
1.2276 +#define REG_CPM_GSR1 REG32(CPM_GSR1)
1.2277 +#define REG_CPM_GSR2 REG32(CPM_GSR2)
1.2278 +#define REG_CPM_SPR REG32(CPM_SPR)
1.2279 +#define REG_CPM_GSR3 REG32(CPM_GSR3)
1.2280 +
1.2281 +#define CPM_CFCR_SSI (1 << 31)
1.2282 +#define CPM_CFCR_LCD (1 << 30)
1.2283 +#define CPM_CFCR_I2S (1 << 29)
1.2284 +#define CPM_CFCR_UCS (1 << 28)
1.2285 +#define CPM_CFCR_UFR_BIT 25
1.2286 +#define CPM_CFCR_UFR_MASK (0x07 << CPM_CFCR_UFR_BIT)
1.2287 +#define CPM_CFCR_MSC (1 << 24)
1.2288 +#define CPM_CFCR_CKOEN2 (1 << 23)
1.2289 +#define CPM_CFCR_CKOEN1 (1 << 22)
1.2290 +#define CPM_CFCR_UPE (1 << 20)
1.2291 +#define CPM_CFCR_MFR_BIT 16
1.2292 +#define CPM_CFCR_MFR_MASK (0x0f << CPM_CFCR_MFR_BIT)
1.2293 + #define CFCR_MDIV_1 (0 << CPM_CFCR_MFR_BIT)
1.2294 + #define CFCR_MDIV_2 (1 << CPM_CFCR_MFR_BIT)
1.2295 + #define CFCR_MDIV_3 (2 << CPM_CFCR_MFR_BIT)
1.2296 + #define CFCR_MDIV_4 (3 << CPM_CFCR_MFR_BIT)
1.2297 + #define CFCR_MDIV_6 (4 << CPM_CFCR_MFR_BIT)
1.2298 + #define CFCR_MDIV_8 (5 << CPM_CFCR_MFR_BIT)
1.2299 + #define CFCR_MDIV_12 (6 << CPM_CFCR_MFR_BIT)
1.2300 + #define CFCR_MDIV_16 (7 << CPM_CFCR_MFR_BIT)
1.2301 + #define CFCR_MDIV_24 (8 << CPM_CFCR_MFR_BIT)
1.2302 + #define CFCR_MDIV_32 (9 << CPM_CFCR_MFR_BIT)
1.2303 +#define CPM_CFCR_LFR_BIT 12
1.2304 +#define CPM_CFCR_LFR_MASK (0x0f << CPM_CFCR_LFR_BIT)
1.2305 +#define CPM_CFCR_PFR_BIT 8
1.2306 +#define CPM_CFCR_PFR_MASK (0x0f << CPM_CFCR_PFR_BIT)
1.2307 + #define CFCR_PDIV_1 (0 << CPM_CFCR_PFR_BIT)
1.2308 + #define CFCR_PDIV_2 (1 << CPM_CFCR_PFR_BIT)
1.2309 + #define CFCR_PDIV_3 (2 << CPM_CFCR_PFR_BIT)
1.2310 + #define CFCR_PDIV_4 (3 << CPM_CFCR_PFR_BIT)
1.2311 + #define CFCR_PDIV_6 (4 << CPM_CFCR_PFR_BIT)
1.2312 + #define CFCR_PDIV_8 (5 << CPM_CFCR_PFR_BIT)
1.2313 + #define CFCR_PDIV_12 (6 << CPM_CFCR_PFR_BIT)
1.2314 + #define CFCR_PDIV_16 (7 << CPM_CFCR_PFR_BIT)
1.2315 + #define CFCR_PDIV_24 (8 << CPM_CFCR_PFR_BIT)
1.2316 + #define CFCR_PDIV_32 (9 << CPM_CFCR_PFR_BIT)
1.2317 +#define CPM_CFCR_SFR_BIT 4
1.2318 +#define CPM_CFCR_SFR_MASK (0x0f << CPM_CFCR_SFR_BIT)
1.2319 + #define CFCR_SDIV_1 (0 << CPM_CFCR_SFR_BIT)
1.2320 + #define CFCR_SDIV_2 (1 << CPM_CFCR_SFR_BIT)
1.2321 + #define CFCR_SDIV_3 (2 << CPM_CFCR_SFR_BIT)
1.2322 + #define CFCR_SDIV_4 (3 << CPM_CFCR_SFR_BIT)
1.2323 + #define CFCR_SDIV_6 (4 << CPM_CFCR_SFR_BIT)
1.2324 + #define CFCR_SDIV_8 (5 << CPM_CFCR_SFR_BIT)
1.2325 + #define CFCR_SDIV_12 (6 << CPM_CFCR_SFR_BIT)
1.2326 + #define CFCR_SDIV_16 (7 << CPM_CFCR_SFR_BIT)
1.2327 + #define CFCR_SDIV_24 (8 << CPM_CFCR_SFR_BIT)
1.2328 + #define CFCR_SDIV_32 (9 << CPM_CFCR_SFR_BIT)
1.2329 +#define CPM_CFCR_IFR_BIT 0
1.2330 +#define CPM_CFCR_IFR_MASK (0x0f << CPM_CFCR_IFR_BIT)
1.2331 + #define CFCR_IDIV_1 (0 << CPM_CFCR_IFR_BIT)
1.2332 + #define CFCR_IDIV_2 (1 << CPM_CFCR_IFR_BIT)
1.2333 + #define CFCR_IDIV_3 (2 << CPM_CFCR_IFR_BIT)
1.2334 + #define CFCR_IDIV_4 (3 << CPM_CFCR_IFR_BIT)
1.2335 + #define CFCR_IDIV_6 (4 << CPM_CFCR_IFR_BIT)
1.2336 + #define CFCR_IDIV_8 (5 << CPM_CFCR_IFR_BIT)
1.2337 + #define CFCR_IDIV_12 (6 << CPM_CFCR_IFR_BIT)
1.2338 + #define CFCR_IDIV_16 (7 << CPM_CFCR_IFR_BIT)
1.2339 + #define CFCR_IDIV_24 (8 << CPM_CFCR_IFR_BIT)
1.2340 + #define CFCR_IDIV_32 (9 << CPM_CFCR_IFR_BIT)
1.2341 +
1.2342 +#define CPM_PLCR1_PLL1FD_BIT 23
1.2343 +#define CPM_PLCR1_PLL1FD_MASK (0x1ff << CPM_PLCR1_PLL1FD_BIT)
1.2344 +#define CPM_PLCR1_PLL1RD_BIT 18
1.2345 +#define CPM_PLCR1_PLL1RD_MASK (0x1f << CPM_PLCR1_PLL1RD_BIT)
1.2346 +#define CPM_PLCR1_PLL1OD_BIT 16
1.2347 +#define CPM_PLCR1_PLL1OD_MASK (0x03 << CPM_PLCR1_PLL1OD_BIT)
1.2348 +#define CPM_PLCR1_PLL1S (1 << 10)
1.2349 +#define CPM_PLCR1_PLL1BP (1 << 9)
1.2350 +#define CPM_PLCR1_PLL1EN (1 << 8)
1.2351 +#define CPM_PLCR1_PLL1ST_BIT 0
1.2352 +#define CPM_PLCR1_PLL1ST_MASK (0xff << CPM_PLCR1_PLL1ST_BIT)
1.2353 +
1.2354 +#define CPM_OCR_O1ST_BIT 16
1.2355 +#define CPM_OCR_O1ST_MASK (0xff << CPM_OCR_O1ST_BIT)
1.2356 +#define CPM_OCR_EXT_RTC_CLK (1<<8)
1.2357 +#define CPM_OCR_SUSPEND_PHY1 (1<<7)
1.2358 +#define CPM_OCR_SUSPEND_PHY0 (1<<6)
1.2359 +
1.2360 +#define CPM_CFCR2_PXFR_BIT 0
1.2361 +#define CPM_CFCR2_PXFR_MASK (0x1ff << CPM_CFCR2_PXFR_BIT)
1.2362 +
1.2363 +#define CPM_LPCR_DUTY_BIT 3
1.2364 +#define CPM_LPCR_DUTY_MASK (0x1f << CPM_LPCR_DUTY_BIT)
1.2365 +#define CPM_LPCR_DOZE (1 << 2)
1.2366 +#define CPM_LPCR_LPM_BIT 0
1.2367 +#define CPM_LPCR_LPM_MASK (0x03 << CPM_LPCR_LPM_BIT)
1.2368 + #define CPM_LPCR_LPM_IDLE (0 << CPM_LPCR_LPM_BIT)
1.2369 + #define CPM_LPCR_LPM_SLEEP (1 << CPM_LPCR_LPM_BIT)
1.2370 + #define CPM_LPCR_LPM_HIBERNATE (2 << CPM_LPCR_LPM_BIT)
1.2371 +
1.2372 +#define CPM_RSTR_SR (1 << 2)
1.2373 +#define CPM_RSTR_WR (1 << 1)
1.2374 +#define CPM_RSTR_HR (1 << 0)
1.2375 +
1.2376 +#define CPM_MSCR_MSTP_BIT 0
1.2377 +#define CPM_MSCR_MSTP_MASK (0x1ffffff << CPM_MSCR_MSTP_BIT)
1.2378 + #define CPM_MSCR_MSTP_UART0 0
1.2379 + #define CPM_MSCR_MSTP_UART1 1
1.2380 + #define CPM_MSCR_MSTP_UART2 2
1.2381 + #define CPM_MSCR_MSTP_OST 3
1.2382 + #define CPM_MSCR_MSTP_DMAC 5
1.2383 + #define CPM_MSCR_MSTP_UHC 6
1.2384 + #define CPM_MSCR_MSTP_LCD 7
1.2385 + #define CPM_MSCR_MSTP_I2C 8
1.2386 + #define CPM_MSCR_MSTP_AICPCLK 9
1.2387 + #define CPM_MSCR_MSTP_PWM0 10
1.2388 + #define CPM_MSCR_MSTP_PWM1 11
1.2389 + #define CPM_MSCR_MSTP_SSI 12
1.2390 + #define CPM_MSCR_MSTP_MSC 13
1.2391 + #define CPM_MSCR_MSTP_SCC 14
1.2392 + #define CPM_MSCR_MSTP_AICBCLK 18
1.2393 + #define CPM_MSCR_MSTP_UART3 20
1.2394 + #define CPM_MSCR_MSTP_ETH 21
1.2395 + #define CPM_MSCR_MSTP_KBC 22
1.2396 + #define CPM_MSCR_MSTP_CIM 23
1.2397 + #define CPM_MSCR_MSTP_UDC 24
1.2398 + #define CPM_MSCR_MSTP_UPRT 25
1.2399 +
1.2400 +#define CPM_SCR_O1SE (1 << 4)
1.2401 +#define CPM_SCR_HGP (1 << 3)
1.2402 +#define CPM_SCR_HZP (1 << 2)
1.2403 +#define CPM_SCR_HZM (1 << 1)
1.2404 +
1.2405 +#define CPM_WRER_RE_BIT 0
1.2406 +#define CPM_WRER_RE_MASK (0xffff << CPM_WRER_RE_BIT)
1.2407 +
1.2408 +#define CPM_WFER_FE_BIT 0
1.2409 +#define CPM_WFER_FE_MASK (0xffff << CPM_WFER_FE_BIT)
1.2410 +
1.2411 +#define CPM_WER_WERTC (1 << 31)
1.2412 +#define CPM_WER_WEETH (1 << 30)
1.2413 +#define CPM_WER_WE_BIT 0
1.2414 +#define CPM_WER_WE_MASK (0xffff << CPM_WER_WE_BIT)
1.2415 +
1.2416 +#define CPM_WSR_WSRTC (1 << 31)
1.2417 +#define CPM_WSR_WSETH (1 << 30)
1.2418 +#define CPM_WSR_WS_BIT 0
1.2419 +#define CPM_WSR_WS_MASK (0xffff << CPM_WSR_WS_BIT)
1.2420 +
1.2421 +
1.2422 +
1.2423 +
1.2424 +/*************************************************************************
1.2425 + * SSI
1.2426 + *************************************************************************/
1.2427 +#define SSI_DR (SSI_BASE + 0x000)
1.2428 +#define SSI_CR0 (SSI_BASE + 0x004)
1.2429 +#define SSI_CR1 (SSI_BASE + 0x008)
1.2430 +#define SSI_SR (SSI_BASE + 0x00C)
1.2431 +#define SSI_ITR (SSI_BASE + 0x010)
1.2432 +#define SSI_ICR (SSI_BASE + 0x014)
1.2433 +#define SSI_GR (SSI_BASE + 0x018)
1.2434 +
1.2435 +#define REG_SSI_DR REG32(SSI_DR)
1.2436 +#define REG_SSI_CR0 REG16(SSI_CR0)
1.2437 +#define REG_SSI_CR1 REG32(SSI_CR1)
1.2438 +#define REG_SSI_SR REG32(SSI_SR)
1.2439 +#define REG_SSI_ITR REG16(SSI_ITR)
1.2440 +#define REG_SSI_ICR REG8(SSI_ICR)
1.2441 +#define REG_SSI_GR REG16(SSI_GR)
1.2442 +
1.2443 +/* SSI Data Register (SSI_DR) */
1.2444 +
1.2445 +#define SSI_DR_GPC_BIT 0
1.2446 +#define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT)
1.2447 +
1.2448 +/* SSI Control Register 0 (SSI_CR0) */
1.2449 +
1.2450 +#define SSI_CR0_SSIE (1 << 15)
1.2451 +#define SSI_CR0_TIE (1 << 14)
1.2452 +#define SSI_CR0_RIE (1 << 13)
1.2453 +#define SSI_CR0_TEIE (1 << 12)
1.2454 +#define SSI_CR0_REIE (1 << 11)
1.2455 +#define SSI_CR0_LOOP (1 << 10)
1.2456 +#define SSI_CR0_RFINE (1 << 9)
1.2457 +#define SSI_CR0_RFINC (1 << 8)
1.2458 +#define SSI_CR0_FSEL (1 << 6)
1.2459 +#define SSI_CR0_TFLUSH (1 << 2)
1.2460 +#define SSI_CR0_RFLUSH (1 << 1)
1.2461 +#define SSI_CR0_DISREV (1 << 0)
1.2462 +
1.2463 +/* SSI Control Register 1 (SSI_CR1) */
1.2464 +
1.2465 +#define SSI_CR1_FRMHL_BIT 30
1.2466 +#define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT)
1.2467 + #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */
1.2468 + #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */
1.2469 + #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */
1.2470 + #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */
1.2471 +#define SSI_CR1_TFVCK_BIT 28
1.2472 +#define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT)
1.2473 + #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT)
1.2474 + #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT)
1.2475 + #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT)
1.2476 + #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT)
1.2477 +#define SSI_CR1_TCKFI_BIT 26
1.2478 +#define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT)
1.2479 + #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT)
1.2480 + #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT)
1.2481 + #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT)
1.2482 + #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT)
1.2483 +#define SSI_CR1_LFST (1 << 25)
1.2484 +#define SSI_CR1_ITFRM (1 << 24)
1.2485 +#define SSI_CR1_UNFIN (1 << 23)
1.2486 +#define SSI_CR1_MULTS (1 << 22)
1.2487 +#define SSI_CR1_FMAT_BIT 20
1.2488 +#define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT)
1.2489 + #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */
1.2490 + #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */
1.2491 + #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */
1.2492 + #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */
1.2493 +#define SSI_CR1_MCOM_BIT 12
1.2494 +#define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT)
1.2495 + #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */
1.2496 + #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */
1.2497 + #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */
1.2498 + #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */
1.2499 + #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */
1.2500 + #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */
1.2501 + #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */
1.2502 + #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */
1.2503 + #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */
1.2504 + #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */
1.2505 + #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */
1.2506 + #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */
1.2507 + #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */
1.2508 + #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */
1.2509 + #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */
1.2510 + #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */
1.2511 +#define SSI_CR1_TTRG_BIT 10
1.2512 +#define SSI_CR1_TTRG_MASK (0x3 << SSI_CR1_TTRG_BIT)
1.2513 + #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT)/* Less than or equal to 1 */
1.2514 + #define SSI_CR1_TTRG_4 (1 << SSI_CR1_TTRG_BIT) /* Less than or equal to 4 */
1.2515 + #define SSI_CR1_TTRG_8 (2 << SSI_CR1_TTRG_BIT) /* Less than or equal to 8 */
1.2516 + #define SSI_CR1_TTRG_14 (3 << SSI_CR1_TTRG_BIT) /* Less than or equal to 14 */
1.2517 +#define SSI_CR1_RTRG_BIT 8
1.2518 +#define SSI_CR1_RTRG_MASK (0x3 << SSI_CR1_RTRG_BIT)
1.2519 + #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT) /* More than or equal to 1 */
1.2520 + #define SSI_CR1_RTRG_4 (1 << SSI_CR1_RTRG_BIT) /* More than or equal to 4 */
1.2521 + #define SSI_CR1_RTRG_8 (2 << SSI_CR1_RTRG_BIT) /* More than or equal to 8 */
1.2522 + #define SSI_CR1_RTRG_14 (3 << SSI_CR1_RTRG_BIT) /* More than or equal to 14 */
1.2523 +#define SSI_CR1_FLEN_BIT 4
1.2524 +#define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT)
1.2525 + #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT)
1.2526 + #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT)
1.2527 + #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT)
1.2528 + #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT)
1.2529 + #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT)
1.2530 + #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT)
1.2531 + #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT)
1.2532 + #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT)
1.2533 + #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT)
1.2534 + #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT)
1.2535 + #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT)
1.2536 + #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT)
1.2537 + #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT)
1.2538 + #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT)
1.2539 + #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT)
1.2540 + #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT)
1.2541 +#define SSI_CR1_PHA (1 << 1)
1.2542 +#define SSI_CR1_POL (1 << 0)
1.2543 +
1.2544 +/* SSI Status Register (SSI_SR) */
1.2545 +
1.2546 +#define SSI_SR_TFIFONUM_BIT 13
1.2547 +#define SSI_SR_TFIFONUM_MASK (0x1f << SSI_SR_TFIFONUM_BIT)
1.2548 +#define SSI_SR_RFIFONUM_BIT 8
1.2549 +#define SSI_SR_RFIFONUM_MASK (0x1f << SSI_SR_RFIFONUM_BIT)
1.2550 +#define SSI_SR_END (1 << 7)
1.2551 +#define SSI_SR_BUSY (1 << 6)
1.2552 +#define SSI_SR_TFF (1 << 5)
1.2553 +#define SSI_SR_RFE (1 << 4)
1.2554 +#define SSI_SR_TFHE (1 << 3)
1.2555 +#define SSI_SR_RFHF (1 << 2)
1.2556 +#define SSI_SR_UNDR (1 << 1)
1.2557 +#define SSI_SR_OVER (1 << 0)
1.2558 +
1.2559 +/* SSI Interval Time Control Register (SSI_ITR) */
1.2560 +
1.2561 +#define SSI_ITR_CNTCLK (1 << 15)
1.2562 +#define SSI_ITR_IVLTM_BIT 0
1.2563 +#define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT)
1.2564 +
1.2565 +#ifndef __ASSEMBLY__
1.2566 +
1.2567 +/***************************************************************************
1.2568 + * MSC
1.2569 + ***************************************************************************/
1.2570 +
1.2571 +#define __msc_start_op() \
1.2572 + ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START )
1.2573 +
1.2574 +#define __msc_set_resto(to) ( REG_MSC_RESTO = to )
1.2575 +#define __msc_set_rdto(to) ( REG_MSC_RDTO = to )
1.2576 +#define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd )
1.2577 +#define __msc_set_arg(arg) ( REG_MSC_ARG = arg )
1.2578 +#define __msc_set_nob(nob) ( REG_MSC_NOB = nob )
1.2579 +#define __msc_get_nob() ( REG_MSC_NOB )
1.2580 +#define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len )
1.2581 +#define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat )
1.2582 +#define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT )
1.2583 +#define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT )
1.2584 +
1.2585 +#define __msc_set_cmdat_bus_width1() \
1.2586 +do { \
1.2587 + REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
1.2588 + REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \
1.2589 +} while(0)
1.2590 +
1.2591 +#define __msc_set_cmdat_bus_width4() \
1.2592 +do { \
1.2593 + REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
1.2594 + REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \
1.2595 +} while(0)
1.2596 +
1.2597 +#define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN )
1.2598 +#define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT )
1.2599 +#define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY )
1.2600 +#define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK )
1.2601 +#define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK )
1.2602 +#define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ )
1.2603 +#define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ )
1.2604 +#define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN )
1.2605 +
1.2606 +/* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */
1.2607 +#define __msc_set_cmdat_res_format(r) \
1.2608 +do { \
1.2609 + REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \
1.2610 + REG_MSC_CMDAT |= (r); \
1.2611 +} while(0)
1.2612 +
1.2613 +#define __msc_clear_cmdat() \
1.2614 + REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \
1.2615 + MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \
1.2616 + MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK )
1.2617 +
1.2618 +#define __msc_get_imask() ( REG_MSC_IMASK )
1.2619 +#define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff )
1.2620 +#define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 )
1.2621 +#define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ )
1.2622 +#define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ )
1.2623 +#define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ )
1.2624 +#define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ )
1.2625 +#define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES )
1.2626 +#define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES )
1.2627 +#define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE )
1.2628 +#define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE )
1.2629 +#define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE )
1.2630 +#define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE )
1.2631 +
1.2632 +/* n=1,2,4,8,16,32,64,128 */
1.2633 +#define __msc_set_clkrt_div(n) \
1.2634 +do { \
1.2635 + REG_MSC_CLKRT &= ~MSC_CLKRT_CLK_RATE_MASK; \
1.2636 + REG_MSC_CLKRT |= MSC_CLKRT_CLK_RATE_DIV_##n; \
1.2637 +} while(0)
1.2638 +
1.2639 +#define __msc_get_ireg() ( REG_MSC_IREG )
1.2640 +#define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ )
1.2641 +#define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ )
1.2642 +#define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES )
1.2643 +#define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE )
1.2644 +#define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE )
1.2645 +#define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES )
1.2646 +#define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE )
1.2647 +#define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE )
1.2648 +
1.2649 +#define __msc_get_stat() ( REG_MSC_STAT )
1.2650 +#define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0)
1.2651 +#define __msc_stat_crc_err() \
1.2652 + ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) )
1.2653 +#define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR )
1.2654 +#define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR )
1.2655 +#define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES )
1.2656 +#define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES )
1.2657 +#define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ )
1.2658 +
1.2659 +#define __msc_rd_resfifo() ( REG_MSC_RES )
1.2660 +#define __msc_rd_rxfifo() ( REG_MSC_RXFIFO )
1.2661 +#define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v )
1.2662 +
1.2663 +#define __msc_reset() \
1.2664 +do { \
1.2665 + REG_MSC_STRPCL = MSC_STRPCL_RESET; \
1.2666 + while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \
1.2667 +} while (0)
1.2668 +
1.2669 +#define __msc_start_clk() \
1.2670 +do { \
1.2671 + REG_MSC_STRPCL &= ~MSC_STRPCL_CLOCK_CONTROL_MASK; \
1.2672 + REG_MSC_STRPCL |= MSC_STRPCL_CLOCK_CONTROL_START; \
1.2673 +} while (0)
1.2674 +
1.2675 +#define __msc_stop_clk() \
1.2676 +do { \
1.2677 + REG_MSC_STRPCL &= ~MSC_STRPCL_CLOCK_CONTROL_MASK; \
1.2678 + REG_MSC_STRPCL |= MSC_STRPCL_CLOCK_CONTROL_STOP; \
1.2679 +} while (0)
1.2680 +
1.2681 +#define MMC_CLK 19169200
1.2682 +#define SD_CLK 24576000
1.2683 +
1.2684 +/* msc_clk should little than pclk and little than clk retrieve from card */
1.2685 +#define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \
1.2686 +do { \
1.2687 + unsigned int rate, pclk, i; \
1.2688 + pclk = dev_clk; \
1.2689 + rate = type?SD_CLK:MMC_CLK; \
1.2690 + if (msc_clk && msc_clk < pclk) \
1.2691 + pclk = msc_clk; \
1.2692 + i = 0; \
1.2693 + while (pclk < rate) \
1.2694 + { \
1.2695 + i ++; \
1.2696 + rate >>= 1; \
1.2697 + } \
1.2698 + lv = i; \
1.2699 +} while(0)
1.2700 +
1.2701 +/* divide rate to little than or equal to 400kHz */
1.2702 +#define __msc_calc_slow_clk_divisor(type, lv) \
1.2703 +do { \
1.2704 + unsigned int rate, i; \
1.2705 + rate = (type?SD_CLK:MMC_CLK)/1000/400; \
1.2706 + i = 0; \
1.2707 + while (rate > 0) \
1.2708 + { \
1.2709 + rate >>= 1; \
1.2710 + i ++; \
1.2711 + } \
1.2712 + lv = i; \
1.2713 +} while(0)
1.2714 +
1.2715 +/***************************************************************************
1.2716 + * RTC
1.2717 + ***************************************************************************/
1.2718 +
1.2719 +#define __rtc_start() ( REG_RTC_RCR |= RTC_RCR_START )
1.2720 +#define __rtc_stop() ( REG_RTC_RCR &= ~RTC_RCR_START )
1.2721 +
1.2722 +#define __rtc_enable_alarm() ( REG_RTC_RCR |= RTC_RCR_AE )
1.2723 +#define __rtc_disable_alarm() ( REG_RTC_RCR &= ~RTC_RCR_AE )
1.2724 +#define __rtc_enable_alarm_irq() ( REG_RTC_RCR |= RTC_RCR_AIE )
1.2725 +#define __rtc_disable_alarm_irq() ( REG_RTC_RCR &= ~RTC_RCR_AIE )
1.2726 +
1.2727 +#define __rtc_enable_1hz_irq() ( REG_RTC_RCR |= RTC_RCR_HZIE )
1.2728 +#define __rtc_disable_1hz_irq() ( REG_RTC_RCR &= ~RTC_RCR_HZIE )
1.2729 +
1.2730 +#define __rtc_is_alarm_flag() ( REG_RTC_RCR & RTC_RCR_AF )
1.2731 +#define __rtc_is_1hz_flag() ( REG_RTC_RCR & RTC_RCR_HZ )
1.2732 +#define __rtc_clear_alarm_flag() ( REG_RTC_RCR &= ~RTC_RCR_AF )
1.2733 +#define __rtc_clear_1hz_flag() ( REG_RTC_RCR &= ~RTC_RCR_HZ )
1.2734 +
1.2735 +#define __rtc_set_second(s) ( REG_RTC_RSR = (s) )
1.2736 +#define __rtc_get_second() REG_RTC_RSR
1.2737 +#define __rtc_set_alarm(s) ( REG_RTC_RSAR = (s) )
1.2738 +#define __rtc_get_alarm() REG_RTC_RSAR
1.2739 +
1.2740 +#define __rtc_adjust_1hz(f32k) \
1.2741 + ( REG_RTC_RGR = (REG_RTC_RGR & ~(RTC_REG_DIV_MASK | RTC_RGR_ADJ_MASK)) | f32k | 0 )
1.2742 +#define __rtc_lock_1hz() ( REG_RTC_RGR |= RTC_RGR_LOCK )
1.2743 +
1.2744 +
1.2745 +/***************************************************************************
1.2746 + * FIR
1.2747 + ***************************************************************************/
1.2748 +
1.2749 +/* enable/disable fir unit */
1.2750 +#define __fir_enable() ( REG_FIR_CR1 |= FIR_CR1_FIRUE )
1.2751 +#define __fir_disable() ( REG_FIR_CR1 &= ~FIR_CR1_FIRUE )
1.2752 +
1.2753 +/* enable/disable address comparison */
1.2754 +#define __fir_enable_ac() ( REG_FIR_CR1 |= FIR_CR1_ACE )
1.2755 +#define __fir_disable_ac() ( REG_FIR_CR1 &= ~FIR_CR1_ACE )
1.2756 +
1.2757 +/* select frame end mode as underrun or normal */
1.2758 +#define __fir_set_eous() ( REG_FIR_CR1 |= FIR_CR1_EOUS )
1.2759 +#define __fir_clear_eous() ( REG_FIR_CR1 &= ~FIR_CR1_EOUS )
1.2760 +
1.2761 +/* enable/disable transmitter idle interrupt */
1.2762 +#define __fir_enable_tii() ( REG_FIR_CR1 |= FIR_CR1_TIIE )
1.2763 +#define __fir_disable_tii() ( REG_FIR_CR1 &= ~FIR_CR1_TIIE )
1.2764 +
1.2765 +/* enable/disable transmit FIFO service request interrupt */
1.2766 +#define __fir_enable_tfi() ( REG_FIR_CR1 |= FIR_CR1_TFIE )
1.2767 +#define __fir_disable_tfi() ( REG_FIR_CR1 &= ~FIR_CR1_TFIE )
1.2768 +
1.2769 +/* enable/disable receive FIFO service request interrupt */
1.2770 +#define __fir_enable_rfi() ( REG_FIR_CR1 |= FIR_CR1_RFIE )
1.2771 +#define __fir_disable_rfi() ( REG_FIR_CR1 &= ~FIR_CR1_RFIE )
1.2772 +
1.2773 +/* enable/disable tx function */
1.2774 +#define __fir_tx_enable() ( REG_FIR_CR1 |= FIR_CR1_TXE )
1.2775 +#define __fir_tx_disable() ( REG_FIR_CR1 &= ~FIR_CR1_TXE )
1.2776 +
1.2777 +/* enable/disable rx function */
1.2778 +#define __fir_rx_enable() ( REG_FIR_CR1 |= FIR_CR1_RXE )
1.2779 +#define __fir_rx_disable() ( REG_FIR_CR1 &= ~FIR_CR1_RXE )
1.2780 +
1.2781 +
1.2782 +/* enable/disable serial infrared interaction pulse (SIP) */
1.2783 +#define __fir_enable_sip() ( REG_FIR_CR2 |= FIR_CR2_SIPE )
1.2784 +#define __fir_disable_sip() ( REG_FIR_CR2 &= ~FIR_CR2_SIPE )
1.2785 +
1.2786 +/* un-inverted CRC value is sent out */
1.2787 +#define __fir_enable_bcrc() ( REG_FIR_CR2 |= FIR_CR2_BCRC )
1.2788 +
1.2789 +/* inverted CRC value is sent out */
1.2790 +#define __fir_disable_bcrc() ( REG_FIR_CR2 &= ~FIR_CR2_BCRC )
1.2791 +
1.2792 +/* enable/disable Transmit Frame Length Register */
1.2793 +#define __fir_enable_tflr() ( REG_FIR_CR2 |= FIR_CR2_TFLRS )
1.2794 +#define __fir_disable_tflr() ( REG_FIR_CR2 &= ~FIR_CR2_TFLRS )
1.2795 +
1.2796 +/* Preamble is transmitted in idle state */
1.2797 +#define __fir_set_iss() ( REG_FIR_CR2 |= FIR_CR2_ISS )
1.2798 +
1.2799 +/* Abort symbol is transmitted in idle state */
1.2800 +#define __fir_clear_iss() ( REG_FIR_CR2 &= ~FIR_CR2_ISS )
1.2801 +
1.2802 +/* enable/disable loopback mode */
1.2803 +#define __fir_enable_loopback() ( REG_FIR_CR2 |= FIR_CR2_LMS )
1.2804 +#define __fir_disable_loopback() ( REG_FIR_CR2 &= ~FIR_CR2_LMS )
1.2805 +
1.2806 +/* select transmit pin polarity */
1.2807 +#define __fir_tpp_negative() ( REG_FIR_CR2 |= FIR_CR2_TPPS )
1.2808 +#define __fir_tpp_positive() ( REG_FIR_CR2 &= ~FIR_CR2_TPPS )
1.2809 +
1.2810 +/* select receive pin polarity */
1.2811 +#define __fir_rpp_negative() ( REG_FIR_CR2 |= FIR_CR2_RPPS )
1.2812 +#define __fir_rpp_positive() ( REG_FIR_CR2 &= ~FIR_CR2_RPPS )
1.2813 +
1.2814 +/* n=16,32,64,128 */
1.2815 +#define __fir_set_txfifo_trigger(n) \
1.2816 +do { \
1.2817 + REG_FIR_CR2 &= ~FIR_CR2_TTRG_MASK; \
1.2818 + REG_FIR_CR2 |= FIR_CR2_TTRG_##n; \
1.2819 +} while (0)
1.2820 +
1.2821 +/* n=16,32,64,128 */
1.2822 +#define __fir_set_rxfifo_trigger(n) \
1.2823 +do { \
1.2824 + REG_FIR_CR2 &= ~FIR_CR2_RTRG_MASK; \
1.2825 + REG_FIR_CR2 |= FIR_CR2_RTRG_##n; \
1.2826 +} while (0)
1.2827 +
1.2828 +
1.2829 +/* FIR status checking */
1.2830 +
1.2831 +#define __fir_test_rfw() ( REG_FIR_SR & FIR_SR_RFW )
1.2832 +#define __fir_test_rfa() ( REG_FIR_SR & FIR_SR_RFA )
1.2833 +#define __fir_test_tfrtl() ( REG_FIR_SR & FIR_SR_TFRTL )
1.2834 +#define __fir_test_rfrtl() ( REG_FIR_SR & FIR_SR_RFRTL )
1.2835 +#define __fir_test_urun() ( REG_FIR_SR & FIR_SR_URUN )
1.2836 +#define __fir_test_rfte() ( REG_FIR_SR & FIR_SR_RFTE )
1.2837 +#define __fir_test_orun() ( REG_FIR_SR & FIR_SR_ORUN )
1.2838 +#define __fir_test_crce() ( REG_FIR_SR & FIR_SR_CRCE )
1.2839 +#define __fir_test_fend() ( REG_FIR_SR & FIR_SR_FEND )
1.2840 +#define __fir_test_tff() ( REG_FIR_SR & FIR_SR_TFF )
1.2841 +#define __fir_test_rfe() ( REG_FIR_SR & FIR_SR_RFE )
1.2842 +#define __fir_test_tidle() ( REG_FIR_SR & FIR_SR_TIDLE )
1.2843 +#define __fir_test_rb() ( REG_FIR_SR & FIR_SR_RB )
1.2844 +
1.2845 +#define __fir_clear_status() \
1.2846 +do { \
1.2847 + REG_FIR_SR |= FIR_SR_RFW | FIR_SR_RFA | FIR_SR_URUN; \
1.2848 +} while (0)
1.2849 +
1.2850 +#define __fir_clear_rfw() ( REG_FIR_SR |= FIR_SR_RFW )
1.2851 +#define __fir_clear_rfa() ( REG_FIR_SR |= FIR_SR_RFA )
1.2852 +#define __fir_clear_urun() ( REG_FIR_SR |= FIR_SR_URUN )
1.2853 +
1.2854 +#define __fir_set_tflr(len) \
1.2855 +do { \
1.2856 + REG_FIR_TFLR = len; \
1.2857 +} while (0)
1.2858 +
1.2859 +#define __fir_set_addr(a) ( REG_FIR_AR = (a) )
1.2860 +
1.2861 +#define __fir_write_data(data) ( REG_FIR_TDR = data )
1.2862 +#define __fir_read_data(data) ( data = REG_FIR_RDR )
1.2863 +
1.2864 +/***************************************************************************
1.2865 + * SCC
1.2866 + ***************************************************************************/
1.2867 +
1.2868 +#define __scc_enable(base) ( REG_SCC_CR(base) |= SCC_CR_SCCE )
1.2869 +#define __scc_disable(base) ( REG_SCC_CR(base) &= ~SCC_CR_SCCE )
1.2870 +
1.2871 +#define __scc_set_tx_mode(base) ( REG_SCC_CR(base) |= SCC_CR_TRS )
1.2872 +#define __scc_set_rx_mode(base) ( REG_SCC_CR(base) &= ~SCC_CR_TRS )
1.2873 +
1.2874 +#define __scc_enable_t2r(base) ( REG_SCC_CR(base) |= SCC_CR_T2R )
1.2875 +#define __scc_disable_t2r(base) ( REG_SCC_CR(base) &= ~SCC_CR_T2R )
1.2876 +
1.2877 +#define __scc_clk_as_devclk(base) \
1.2878 +do { \
1.2879 + REG_SCC_CR(base) &= ~SCC_CR_FDIV_MASK; \
1.2880 + REG_SCC_CR(base) |= SCC_CR_FDIV_1; \
1.2881 +} while (0)
1.2882 +
1.2883 +#define __scc_clk_as_half_devclk(base) \
1.2884 +do { \
1.2885 + REG_SCC_CR(base) &= ~SCC_CR_FDIV_MASK; \
1.2886 + REG_SCC_CR(base) |= SCC_CR_FDIV_2; \
1.2887 +} while (0)
1.2888 +
1.2889 +/* n=1,4,8,14 */
1.2890 +#define __scc_set_fifo_trigger(base, n) \
1.2891 +do { \
1.2892 + REG_SCC_CR(base) &= ~SCC_CR_TRIG_MASK; \
1.2893 + REG_SCC_CR(base) |= SCC_CR_TRIG_##n; \
1.2894 +} while (0)
1.2895 +
1.2896 +#define __scc_set_protocol(base, p) \
1.2897 +do { \
1.2898 + if (p) \
1.2899 + REG_SCC_CR(base) |= SCC_CR_TP; \
1.2900 + else \
1.2901 + REG_SCC_CR(base) &= ~SCC_CR_TP; \
1.2902 +} while (0)
1.2903 +
1.2904 +#define __scc_flush_fifo(base) ( REG_SCC_CR(base) |= SCC_CR_FLUSH )
1.2905 +
1.2906 +#define __scc_set_invert_mode(base) ( REG_SCC_CR(base) |= SCC_CR_CONV )
1.2907 +#define __scc_set_direct_mode(base) ( REG_SCC_CR(base) &= ~SCC_CR_CONV )
1.2908 +
1.2909 +#define SCC_ERR_INTRS \
1.2910 + ( SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE )
1.2911 +#define SCC_ALL_INTRS \
1.2912 + ( SCC_CR_TXIE | SCC_CR_RXIE | SCC_CR_TENDIE | SCC_CR_RTOIE | \
1.2913 + SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE )
1.2914 +
1.2915 +#define __scc_enable_err_intrs(base) ( REG_SCC_CR(base) |= SCC_ERR_INTRS )
1.2916 +#define __scc_disable_err_intrs(base) ( REG_SCC_CR(base) &= ~SCC_ERR_INTRS )
1.2917 +
1.2918 +#define SCC_ALL_ERRORS \
1.2919 + ( SCC_SR_ORER | SCC_SR_RTO | SCC_SR_PER | SCC_SR_RETR_3 | SCC_SR_ECNTO)
1.2920 +
1.2921 +#define __scc_clear_errors(base) ( REG_SCC_SR(base) &= ~SCC_ALL_ERRORS )
1.2922 +
1.2923 +#define __scc_enable_all_intrs(base) ( REG_SCC_CR(base) |= SCC_ALL_INTRS )
1.2924 +#define __scc_disable_all_intrs(base) ( REG_SCC_CR(base) &= ~SCC_ALL_INTRS )
1.2925 +
1.2926 +#define __scc_enable_tx_intr(base) ( REG_SCC_CR(base) |= SCC_CR_TXIE | SCC_CR_TENDIE )
1.2927 +#define __scc_disable_tx_intr(base) ( REG_SCC_CR(base) &= ~(SCC_CR_TXIE | SCC_CR_TENDIE) )
1.2928 +
1.2929 +#define __scc_enable_rx_intr(base) ( REG_SCC_CR(base) |= SCC_CR_RXIE)
1.2930 +#define __scc_disable_rx_intr(base) ( REG_SCC_CR(base) &= ~SCC_CR_RXIE)
1.2931 +
1.2932 +#define __scc_set_tsend(base) ( REG_SCC_CR(base) |= SCC_CR_TSEND )
1.2933 +#define __scc_clear_tsend(base) ( REG_SCC_CR(base) &= ~SCC_CR_TSEND )
1.2934 +
1.2935 +#define __scc_set_clockstop(base) ( REG_SCC_CR(base) |= SCC_CR_CLKSTP )
1.2936 +#define __scc_clear_clockstop(base) ( REG_SCC_CR(base) &= ~SCC_CR_CLKSTP )
1.2937 +
1.2938 +#define __scc_clockstop_low(base) \
1.2939 +do { \
1.2940 + REG_SCC_CR(base) &= ~SCC_CR_PX_MASK; \
1.2941 + REG_SCC_CR(base) |= SCC_CR_PX_STOP_LOW; \
1.2942 +} while (0)
1.2943 +
1.2944 +#define __scc_clockstop_high(base) \
1.2945 +do { \
1.2946 + REG_SCC_CR(base) &= ~SCC_CR_PX_MASK; \
1.2947 + REG_SCC_CR(base) |= SCC_CR_PX_STOP_HIGH; \
1.2948 +} while (0)
1.2949 +
1.2950 +
1.2951 +/* SCC status checking */
1.2952 +#define __scc_check_transfer_status(base) ( REG_SCC_SR(base) & SCC_SR_TRANS )
1.2953 +#define __scc_check_rx_overrun_error(base) ( REG_SCC_SR(base) & SCC_SR_ORER )
1.2954 +#define __scc_check_rx_timeout(base) ( REG_SCC_SR(base) & SCC_SR_RTO )
1.2955 +#define __scc_check_parity_error(base) ( REG_SCC_SR(base) & SCC_SR_PER )
1.2956 +#define __scc_check_txfifo_trigger(base) ( REG_SCC_SR(base) & SCC_SR_TFTG )
1.2957 +#define __scc_check_rxfifo_trigger(base) ( REG_SCC_SR(base) & SCC_SR_RFTG )
1.2958 +#define __scc_check_tx_end(base) ( REG_SCC_SR(base) & SCC_SR_TEND )
1.2959 +#define __scc_check_retx_3(base) ( REG_SCC_SR(base) & SCC_SR_RETR_3 )
1.2960 +#define __scc_check_ecnt_overflow(base) ( REG_SCC_SR(base) & SCC_SR_ECNTO )
1.2961 +
1.2962 +
1.2963 +/***************************************************************************
1.2964 + * WDT
1.2965 + ***************************************************************************/
1.2966 +
1.2967 +#define __wdt_set_count(count) ( REG_WDT_WTCNT = (count) )
1.2968 +#define __wdt_start() ( REG_WDT_WTCSR |= WDT_WTCSR_START )
1.2969 +#define __wdt_stop() ( REG_WDT_WTCSR &= ~WDT_WTCSR_START )
1.2970 +
1.2971 +
1.2972 +/***************************************************************************
1.2973 + * OST
1.2974 + ***************************************************************************/
1.2975 +
1.2976 +#define __ost_enable_all() ( REG_OST_TER |= 0x07 )
1.2977 +#define __ost_disable_all() ( REG_OST_TER &= ~0x07 )
1.2978 +#define __ost_enable_channel(n) ( REG_OST_TER |= (1 << (n)) )
1.2979 +#define __ost_disable_channel(n) ( REG_OST_TER &= ~(1 << (n)) )
1.2980 +#define __ost_set_reload(n, val) ( REG_OST_TRDR(n) = (val) )
1.2981 +#define __ost_set_count(n, val) ( REG_OST_TCNT(n) = (val) )
1.2982 +#define __ost_get_count(n) ( REG_OST_TCNT(n) )
1.2983 +#define __ost_set_clock(n, cs) ( REG_OST_TCSR(n) |= (cs) )
1.2984 +#define __ost_set_mode(n, val) ( REG_OST_TCSR(n) = (val) )
1.2985 +#define __ost_enable_interrupt(n) ( REG_OST_TCSR(n) |= OST_TCSR_UIE )
1.2986 +#define __ost_disable_interrupt(n) ( REG_OST_TCSR(n) &= ~OST_TCSR_UIE )
1.2987 +#define __ost_uf_detected(n) ( REG_OST_TCSR(n) & OST_TCSR_UF )
1.2988 +#define __ost_clear_uf(n) ( REG_OST_TCSR(n) &= ~OST_TCSR_UF )
1.2989 +#define __ost_is_busy(n) ( REG_OST_TCSR(n) & OST_TCSR_BUSY )
1.2990 +#define __ost_clear_busy(n) ( REG_OST_TCSR(n) &= ~OST_TCSR_BUSY )
1.2991 +
1.2992 +
1.2993 +/***************************************************************************
1.2994 + * UART
1.2995 + ***************************************************************************/
1.2996 +
1.2997 +#define __uart_enable(n) \
1.2998 + ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) = UARTFCR_UUE | UARTFCR_FE )
1.2999 +#define __uart_disable(n) \
1.3000 + ( REG8(UART_BASE + UART_OFF*(n) + OFF_FCR) = ~UARTFCR_UUE )
1.3001 +
1.3002 +#define __uart_enable_transmit_irq(n) \
1.3003 + ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_TIE )
1.3004 +#define __uart_disable_transmit_irq(n) \
1.3005 + ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~UARTIER_TIE )
1.3006 +
1.3007 +#define __uart_enable_receive_irq(n) \
1.3008 + ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE )
1.3009 +#define __uart_disable_receive_irq(n) \
1.3010 + ( REG8(UART_BASE + UART_OFF*(n) + OFF_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) )
1.3011 +
1.3012 +#define __uart_enable_loopback(n) \
1.3013 + ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) |= UARTMCR_LOOP )
1.3014 +#define __uart_disable_loopback(n) \
1.3015 + ( REG8(UART_BASE + UART_OFF*(n) + OFF_MCR) &= ~UARTMCR_LOOP )
1.3016 +
1.3017 +#define __uart_set_8n1(n) \
1.3018 + ( REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) = UARTLCR_WLEN_8 )
1.3019 +
1.3020 +#define __uart_set_baud(n, devclk, baud) \
1.3021 + do { \
1.3022 + REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) |= UARTLCR_DLAB; \
1.3023 + REG8(UART_BASE + UART_OFF*(n) + OFF_DLLR) = (devclk / 16 / baud) & 0xff; \
1.3024 + REG8(UART_BASE + UART_OFF*(n) + OFF_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \
1.3025 + REG8(UART_BASE + UART_OFF*(n) + OFF_LCR) &= ~UARTLCR_DLAB; \
1.3026 + } while (0)
1.3027 +
1.3028 +#define __uart_parity_error(n) \
1.3029 + ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_PER) != 0 )
1.3030 +
1.3031 +#define __uart_clear_errors(n) \
1.3032 + ( REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTSR_RFER) )
1.3033 +
1.3034 +#define __uart_transmit_fifo_empty(n) \
1.3035 + ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TDRQ) != 0 )
1.3036 +
1.3037 +#define __uart_transmit_end(n) \
1.3038 + ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_TEMT) != 0 )
1.3039 +
1.3040 +#define __uart_transmit_char(n, ch) \
1.3041 + REG8(UART_BASE + UART_OFF*(n) + OFF_TDR) = (ch)
1.3042 +
1.3043 +#define __uart_receive_fifo_full(n) \
1.3044 + ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 )
1.3045 +
1.3046 +#define __uart_receive_ready(n) \
1.3047 + ( (REG8(UART_BASE + UART_OFF*(n) + OFF_LSR) & UARTLSR_DR) != 0 )
1.3048 +
1.3049 +#define __uart_receive_char(n) \
1.3050 + REG8(UART_BASE + UART_OFF*(n) + OFF_RDR)
1.3051 +
1.3052 +#define __uart_disable_irda() \
1.3053 + ( REG8(IRDA_BASE + OFF_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) )
1.3054 +#define __uart_enable_irda() \
1.3055 + /* Tx high pulse as 0, Rx low pulse as 0 */ \
1.3056 + ( REG8(IRDA_BASE + OFF_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS )
1.3057 +
1.3058 +
1.3059 +/***************************************************************************
1.3060 + * INTC
1.3061 + ***************************************************************************/
1.3062 +#define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) )
1.3063 +#define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) )
1.3064 +#define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) )
1.3065 +
1.3066 +/***************************************************************************
1.3067 + * CIM
1.3068 + ***************************************************************************/
1.3069 +
1.3070 +#define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA )
1.3071 +#define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA )
1.3072 +
1.3073 +#define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT )
1.3074 +#define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT )
1.3075 +
1.3076 +#define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP )
1.3077 +#define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP )
1.3078 +
1.3079 +#define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP )
1.3080 +#define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP )
1.3081 +
1.3082 +#define __cim_sample_data_at_pclk_falling_edge() \
1.3083 + ( REG_CIM_CFG |= CIM_CFG_PCP )
1.3084 +#define __cim_sample_data_at_pclk_rising_edge() \
1.3085 + ( REG_CIM_CFG &= ~CIM_CFG_PCP )
1.3086 +
1.3087 +#define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO )
1.3088 +#define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO )
1.3089 +
1.3090 +#define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC )
1.3091 +#define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC )
1.3092 +
1.3093 +/* n=0-7 */
1.3094 +#define __cim_set_data_packing_mode(n) \
1.3095 +do { \
1.3096 + REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \
1.3097 + REG_CIM_CFG |= (CIM_CFG_PACK_##n); \
1.3098 +} while (0)
1.3099 +
1.3100 +#define __cim_enable_ccir656_progressive_mode() \
1.3101 +do { \
1.3102 + REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
1.3103 + REG_CIM_CFG |= CIM_CFG_DSM_CPM; \
1.3104 +} while (0)
1.3105 +
1.3106 +#define __cim_enable_ccir656_interlace_mode() \
1.3107 +do { \
1.3108 + REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
1.3109 + REG_CIM_CFG |= CIM_CFG_DSM_CIM; \
1.3110 +} while (0)
1.3111 +
1.3112 +#define __cim_enable_gated_clock_mode() \
1.3113 +do { \
1.3114 + REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
1.3115 + REG_CIM_CFG |= CIM_CFG_DSM_GCM; \
1.3116 +} while (0)
1.3117 +
1.3118 +#define __cim_enable_nongated_clock_mode() \
1.3119 +do { \
1.3120 + REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
1.3121 + REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \
1.3122 +} while (0)
1.3123 +
1.3124 +/* sclk:system bus clock
1.3125 + * mclk: CIM master clock
1.3126 + */
1.3127 +#define __cim_set_master_clk(sclk, mclk) \
1.3128 +do { \
1.3129 + REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \
1.3130 + REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \
1.3131 +} while (0)
1.3132 +
1.3133 +#define __cim_enable_sof_intr() \
1.3134 + ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM )
1.3135 +#define __cim_disable_sof_intr() \
1.3136 + ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM )
1.3137 +
1.3138 +#define __cim_enable_eof_intr() \
1.3139 + ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM )
1.3140 +#define __cim_disable_eof_intr() \
1.3141 + ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM )
1.3142 +
1.3143 +#define __cim_enable_stop_intr() \
1.3144 + ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM )
1.3145 +#define __cim_disable_stop_intr() \
1.3146 + ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM )
1.3147 +
1.3148 +#define __cim_enable_trig_intr() \
1.3149 + ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM )
1.3150 +#define __cim_disable_trig_intr() \
1.3151 + ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM )
1.3152 +
1.3153 +#define __cim_enable_rxfifo_overflow_intr() \
1.3154 + ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM )
1.3155 +#define __cim_disable_rxfifo_overflow_intr() \
1.3156 + ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM )
1.3157 +
1.3158 +/* n=1-16 */
1.3159 +#define __cim_set_frame_rate(n) \
1.3160 +do { \
1.3161 + REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \
1.3162 + REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \
1.3163 +} while (0)
1.3164 +
1.3165 +#define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN )
1.3166 +#define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN )
1.3167 +
1.3168 +#define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST )
1.3169 +#define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST )
1.3170 +
1.3171 +/* n=4,8,12,16,20,24,28,32 */
1.3172 +#define __cim_set_rxfifo_trigger(n) \
1.3173 +do { \
1.3174 + REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \
1.3175 + REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \
1.3176 +} while (0)
1.3177 +
1.3178 +#define __cim_clear_state() ( REG_CIM_STATE = 0 )
1.3179 +
1.3180 +#define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD )
1.3181 +#define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY )
1.3182 +#define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG )
1.3183 +#define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF )
1.3184 +#define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF )
1.3185 +#define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP )
1.3186 +#define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF )
1.3187 +#define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF )
1.3188 +
1.3189 +#define __cim_get_iid() ( REG_CIM_IID )
1.3190 +#define __cim_get_image_data() ( REG_CIM_RXFIFO )
1.3191 +#define __cim_get_dam_cmd() ( REG_CIM_CMD )
1.3192 +
1.3193 +#define __cim_set_da(a) ( REG_CIM_DA = (a) )
1.3194 +
1.3195 +/***************************************************************************
1.3196 + * PWM
1.3197 + ***************************************************************************/
1.3198 +
1.3199 +/* n is the pwm channel (0,1,..) */
1.3200 +#define __pwm_enable_module(n) ( REG_PWM_CTR(n) |= PWM_CTR_EN )
1.3201 +#define __pwm_disable_module(n) ( REG_PWM_CTR(n) &= ~PWM_CTR_EN )
1.3202 +#define __pwm_graceful_shutdown_mode(n) ( REG_PWM_CTR(n) &= ~PWM_CTR_SD )
1.3203 +#define __pwm_abrupt_shutdown_mode(n) ( REG_PWM_CTR(n) |= PWM_CTR_SD )
1.3204 +#define __pwm_set_full_duty(n) ( REG_PWM_DUT(n) |= PWM_DUT_FDUTY )
1.3205 +
1.3206 +#define __pwm_set_prescale(n, p) \
1.3207 + ( REG_PWM_CTR(n) = ((REG_PWM_CTR(n) & ~PWM_CTR_PRESCALE_MASK) | (p) ) )
1.3208 +#define __pwm_set_period(n, p) \
1.3209 + ( REG_PWM_PER(n) = ( (REG_PWM_PER(n) & ~PWM_PER_PERIOD_MASK) | (p) ) )
1.3210 +#define __pwm_set_duty(n, d) \
1.3211 + ( REG_PWM_DUT(n) = ( (REG_PWM_DUT(n) & ~PWM_DUT_FDUTY) | (d) ) )
1.3212 +
1.3213 +/***************************************************************************
1.3214 + * EMC
1.3215 + ***************************************************************************/
1.3216 +
1.3217 +#define __emc_enable_split() ( REG_EMC_BCR = EMC_BCR_BRE )
1.3218 +#define __emc_disable_split() ( REG_EMC_BCR = 0 )
1.3219 +
1.3220 +#define __emc_smem_bus_width(n) /* 8, 16 or 32*/ \
1.3221 + ( REG_EMC_SMCR = (REG_EMC_SMCR & EMC_SMCR_BW_MASK) | \
1.3222 + EMC_SMCR_BW_##n##BIT )
1.3223 +#define __emc_smem_byte_control() \
1.3224 + ( REG_EMC_SMCR = (REG_EMC_SMCR | EMC_SMCR_BCM )
1.3225 +#define __emc_normal_smem() \
1.3226 + ( REG_EMC_SMCR = (REG_EMC_SMCR & ~EMC_SMCR_SMT )
1.3227 +#define __emc_burst_smem() \
1.3228 + ( REG_EMC_SMCR = (REG_EMC_SMCR | EMC_SMCR_SMT )
1.3229 +#define __emc_smem_burstlen(n) /* 4, 8, 16 or 32 */ \
1.3230 + ( REG_EMC_SMCR = (REG_EMC_SMCR & EMC_SMCR_BL_MASK) | (EMC_SMCR_BL_##n )
1.3231 +
1.3232 +/***************************************************************************
1.3233 + * GPIO
1.3234 + ***************************************************************************/
1.3235 +
1.3236 +/* p is the port number (0,1,2,3)
1.3237 + * o is the pin offset (0-31) inside the port
1.3238 + * n is the absolute number of a pin (0-124), regardless of the port
1.3239 + * m is the interrupt manner (low/high/falling/rising)
1.3240 + */
1.3241 +
1.3242 +#define __gpio_port_data(p) ( REG_GPIO_GPDR(p) )
1.3243 +
1.3244 +#define __gpio_port_as_output(p, o) \
1.3245 +do { \
1.3246 + unsigned int tmp; \
1.3247 + REG_GPIO_GPIER(p) &= ~(1 << (o)); \
1.3248 + REG_GPIO_GPDIR(p) |= (1 << (o)); \
1.3249 + if (o < 16) { \
1.3250 + tmp = REG_GPIO_GPALR(p); \
1.3251 + tmp &= ~(3 << ((o) << 1)); \
1.3252 + REG_GPIO_GPALR(p) = tmp; \
1.3253 + } else { \
1.3254 + tmp = REG_GPIO_GPAUR(p); \
1.3255 + tmp &= ~(3 << (((o) - 16)<< 1)); \
1.3256 + REG_GPIO_GPAUR(p) = tmp; \
1.3257 + } \
1.3258 +} while (0)
1.3259 +
1.3260 +#define __gpio_port_as_input(p, o) \
1.3261 +do { \
1.3262 + unsigned int tmp; \
1.3263 + REG_GPIO_GPIER(p) &= ~(1 << (o)); \
1.3264 + REG_GPIO_GPDIR(p) &= ~(1 << (o)); \
1.3265 + if (o < 16) { \
1.3266 + tmp = REG_GPIO_GPALR(p); \
1.3267 + tmp &= ~(3 << ((o) << 1)); \
1.3268 + REG_GPIO_GPALR(p) = tmp; \
1.3269 + } else { \
1.3270 + tmp = REG_GPIO_GPAUR(p); \
1.3271 + tmp &= ~(3 << (((o) - 16)<< 1)); \
1.3272 + REG_GPIO_GPAUR(p) = tmp; \
1.3273 + } \
1.3274 +} while (0)
1.3275 +
1.3276 +#define __gpio_as_output(n) \
1.3277 +do { \
1.3278 + unsigned int p, o; \
1.3279 + p = (n) / 32; \
1.3280 + o = (n) % 32; \
1.3281 + __gpio_port_as_output(p, o); \
1.3282 +} while (0)
1.3283 +
1.3284 +#define __gpio_as_input(n) \
1.3285 +do { \
1.3286 + unsigned int p, o; \
1.3287 + p = (n) / 32; \
1.3288 + o = (n) % 32; \
1.3289 + __gpio_port_as_input(p, o); \
1.3290 +} while (0)
1.3291 +
1.3292 +#define __gpio_set_pin(n) \
1.3293 +do { \
1.3294 + unsigned int p, o; \
1.3295 + p = (n) / 32; \
1.3296 + o = (n) % 32; \
1.3297 + __gpio_port_data(p) |= (1 << o); \
1.3298 +} while (0)
1.3299 +
1.3300 +#define __gpio_clear_pin(n) \
1.3301 +do { \
1.3302 + unsigned int p, o; \
1.3303 + p = (n) / 32; \
1.3304 + o = (n) % 32; \
1.3305 + __gpio_port_data(p) &= ~(1 << o); \
1.3306 +} while (0)
1.3307 +
1.3308 +static __inline__ unsigned int __gpio_get_pin(unsigned int n)
1.3309 +{
1.3310 + unsigned int p, o;
1.3311 + p = (n) / 32;
1.3312 + o = (n) % 32;
1.3313 + if (__gpio_port_data(p) & (1 << o))
1.3314 + return 1;
1.3315 + else
1.3316 + return 0;
1.3317 +}
1.3318 +
1.3319 +
1.3320 +#define __gpio_set_irq_detect_manner(p, o, m) \
1.3321 +do { \
1.3322 + unsigned int tmp; \
1.3323 + if (o < 16) { \
1.3324 + tmp = REG_GPIO_GPIDLR(p); \
1.3325 + tmp &= ~(3 << ((o) << 1)); \
1.3326 + tmp |= ((m) << ((o) << 1)); \
1.3327 + REG_GPIO_GPIDLR(p) = tmp; \
1.3328 + } else { \
1.3329 + o -= 16; \
1.3330 + tmp = REG_GPIO_GPIDUR(p); \
1.3331 + tmp &= ~(3 << ((o) << 1)); \
1.3332 + tmp |= ((m) << ((o) << 1)); \
1.3333 + REG_GPIO_GPIDUR(p) = tmp; \
1.3334 + } \
1.3335 +} while (0)
1.3336 +
1.3337 +#define __gpio_port_as_irq(p, o, m) \
1.3338 +do { \
1.3339 + __gpio_set_irq_detect_manner(p, o, m); \
1.3340 + __gpio_port_as_input(p, o); \
1.3341 + REG_GPIO_GPIER(p) |= (1 << o); \
1.3342 +} while (0)
1.3343 +
1.3344 +#define __gpio_as_irq(n, m) \
1.3345 +do { \
1.3346 + unsigned int p, o; \
1.3347 + p = (n) / 32; \
1.3348 + o = (n) % 32; \
1.3349 + __gpio_port_as_irq(p, o, m); \
1.3350 +} while (0)
1.3351 +
1.3352 +
1.3353 +#define __gpio_as_irq_high_level(n) __gpio_as_irq(n, GPIO_IRQ_HILEVEL)
1.3354 +#define __gpio_as_irq_low_level(n) __gpio_as_irq(n, GPIO_IRQ_LOLEVEL)
1.3355 +#define __gpio_as_irq_fall_edge(n) __gpio_as_irq(n, GPIO_IRQ_FALLEDG)
1.3356 +#define __gpio_as_irq_rise_edge(n) __gpio_as_irq(n, GPIO_IRQ_RAISEDG)
1.3357 +
1.3358 +
1.3359 +#define __gpio_mask_irq(n) \
1.3360 +do { \
1.3361 + unsigned int p, o; \
1.3362 + p = (n) / 32; \
1.3363 + o = (n) % 32; \
1.3364 + REG_GPIO_GPIER(p) &= ~(1 << o); \
1.3365 +} while (0)
1.3366 +
1.3367 +#define __gpio_unmask_irq(n) \
1.3368 +do { \
1.3369 + unsigned int p, o; \
1.3370 + p = (n) / 32; \
1.3371 + o = (n) % 32; \
1.3372 + REG_GPIO_GPIER(n) |= (1 << o); \
1.3373 +} while (0)
1.3374 +
1.3375 +#define __gpio_ack_irq(n) \
1.3376 +do { \
1.3377 + unsigned int p, o; \
1.3378 + p = (n) / 32; \
1.3379 + o = (n) % 32; \
1.3380 + REG_GPIO_GPFR(p) |= (1 << o); \
1.3381 +} while (0)
1.3382 +
1.3383 +
1.3384 +static __inline__ unsigned int __gpio_get_irq(void)
1.3385 +{
1.3386 + unsigned int tmp, i;
1.3387 +
1.3388 + tmp = REG_GPIO_GPFR(3);
1.3389 + for (i=0; i<32; i++)
1.3390 + if (tmp & (1 << i))
1.3391 + return 0x60 + i;
1.3392 + tmp = REG_GPIO_GPFR(2);
1.3393 + for (i=0; i<32; i++)
1.3394 + if (tmp & (1 << i))
1.3395 + return 0x40 + i;
1.3396 + tmp = REG_GPIO_GPFR(1);
1.3397 + for (i=0; i<32; i++)
1.3398 + if (tmp & (1 << i))
1.3399 + return 0x20 + i;
1.3400 + tmp = REG_GPIO_GPFR(0);
1.3401 + for (i=0; i<32; i++)
1.3402 + if (tmp & (1 << i))
1.3403 + return i;
1.3404 + return 0;
1.3405 +}
1.3406 +
1.3407 +#define __gpio_group_irq(n) \
1.3408 +({ \
1.3409 + register int tmp, i; \
1.3410 + tmp = REG_GPIO_GPFR((n)); \
1.3411 + for (i=31;i>=0;i--) \
1.3412 + if (tmp & (1 << i)) \
1.3413 + break; \
1.3414 + i; \
1.3415 +})
1.3416 +
1.3417 +#define __gpio_enable_pull(n) \
1.3418 +do { \
1.3419 + unsigned int p, o; \
1.3420 + p = (n) / 32; \
1.3421 + o = (n) % 32; \
1.3422 + REG_GPIO_GPPUR(p) |= (1 << o); \
1.3423 +} while (0)
1.3424 +
1.3425 +#define __gpio_disable_pull(n) \
1.3426 +do { \
1.3427 + unsigned int p, o; \
1.3428 + p = (n) / 32; \
1.3429 + o = (n) % 32; \
1.3430 + REG_GPIO_GPPUR(p) &= ~(1 << o); \
1.3431 +} while (0)
1.3432 +
1.3433 +/* Init the alternate function pins */
1.3434 +
1.3435 +
1.3436 +#define __gpio_as_ssi() \
1.3437 +do { \
1.3438 + REG_GPIO_GPALR(2) &= 0xFC00FFFF; \
1.3439 + REG_GPIO_GPALR(2) |= 0x01550000; \
1.3440 +} while (0)
1.3441 +
1.3442 +#define __gpio_as_uart3() \
1.3443 +do { \
1.3444 + REG_GPIO_GPAUR(0) &= 0xFFFF0000; \
1.3445 + REG_GPIO_GPAUR(0) |= 0x00005555; \
1.3446 +} while (0)
1.3447 +
1.3448 +#define __gpio_as_uart2() \
1.3449 +do { \
1.3450 + REG_GPIO_GPALR(3) &= 0x3FFFFFFF; \
1.3451 + REG_GPIO_GPALR(3) |= 0x40000000; \
1.3452 + REG_GPIO_GPAUR(3) &= 0xF3FFFFFF; \
1.3453 + REG_GPIO_GPAUR(3) |= 0x04000000; \
1.3454 +} while (0)
1.3455 +
1.3456 +#define __gpio_as_uart1() \
1.3457 +do { \
1.3458 + REG_GPIO_GPAUR(0) &= 0xFFF0FFFF; \
1.3459 + REG_GPIO_GPAUR(0) |= 0x00050000; \
1.3460 +} while (0)
1.3461 +
1.3462 +#define __gpio_as_uart0() \
1.3463 +do { \
1.3464 + REG_GPIO_GPAUR(3) &= 0x0FFFFFFF; \
1.3465 + REG_GPIO_GPAUR(3) |= 0x50000000; \
1.3466 +} while (0)
1.3467 +
1.3468 +
1.3469 +#define __gpio_as_scc0() \
1.3470 +do { \
1.3471 + REG_GPIO_GPALR(2) &= 0xFFFFFFCC; \
1.3472 + REG_GPIO_GPALR(2) |= 0x00000011; \
1.3473 +} while (0)
1.3474 +
1.3475 +#define __gpio_as_scc1() \
1.3476 +do { \
1.3477 + REG_GPIO_GPALR(2) &= 0xFFFFFF33; \
1.3478 + REG_GPIO_GPALR(2) |= 0x00000044; \
1.3479 +} while (0)
1.3480 +
1.3481 +#define __gpio_as_scc() \
1.3482 +do { \
1.3483 + __gpio_as_scc0(); \
1.3484 + __gpio_as_scc1(); \
1.3485 +} while (0)
1.3486 +
1.3487 +#define __gpio_as_dma() \
1.3488 +do { \
1.3489 + REG_GPIO_GPALR(0) &= 0x00FFFFFF; \
1.3490 + REG_GPIO_GPALR(0) |= 0x55000000; \
1.3491 + REG_GPIO_GPAUR(0) &= 0xFF0FFFFF; \
1.3492 + REG_GPIO_GPAUR(0) |= 0x00500000; \
1.3493 +} while (0)
1.3494 +
1.3495 +#define __gpio_as_msc() \
1.3496 +do { \
1.3497 + REG_GPIO_GPALR(1) &= 0xFFFF000F; \
1.3498 + REG_GPIO_GPALR(1) |= 0x00005550; \
1.3499 +} while (0)
1.3500 +
1.3501 +#define __gpio_as_pcmcia() \
1.3502 +do { \
1.3503 + REG_GPIO_GPAUR(2) &= 0xF000FFFF; \
1.3504 + REG_GPIO_GPAUR(2) |= 0x05550000; \
1.3505 +} while (0)
1.3506 +
1.3507 +#define __gpio_as_emc() \
1.3508 +do { \
1.3509 + REG_GPIO_GPALR(2) &= 0x3FFFFFFF; \
1.3510 + REG_GPIO_GPALR(2) |= 0x40000000; \
1.3511 + REG_GPIO_GPAUR(2) &= 0xFFFF0000; \
1.3512 + REG_GPIO_GPAUR(2) |= 0x00005555; \
1.3513 +} while (0)
1.3514 +
1.3515 +#define __gpio_as_lcd_slave() \
1.3516 +do { \
1.3517 + REG_GPIO_GPALR(1) &= 0x0000FFFF; \
1.3518 + REG_GPIO_GPALR(1) |= 0x55550000; \
1.3519 + REG_GPIO_GPAUR(1) &= 0x00000000; \
1.3520 + REG_GPIO_GPAUR(1) |= 0x55555555; \
1.3521 +} while (0)
1.3522 +
1.3523 +#define __gpio_as_lcd_master() \
1.3524 +do { \
1.3525 + REG_GPIO_GPALR(1) &= 0x0000FFFF; \
1.3526 + REG_GPIO_GPALR(1) |= 0x55550000; \
1.3527 + REG_GPIO_GPAUR(1) &= 0x00000000; \
1.3528 + REG_GPIO_GPAUR(1) |= 0x556A5555; \
1.3529 +} while (0)
1.3530 +
1.3531 +#define __gpio_as_usb() \
1.3532 +do { \
1.3533 + REG_GPIO_GPAUR(0) &= 0x00FFFFFF; \
1.3534 + REG_GPIO_GPAUR(0) |= 0x55000000; \
1.3535 +} while (0)
1.3536 +
1.3537 +#define __gpio_as_ac97() \
1.3538 +do { \
1.3539 + REG_GPIO_GPALR(2) &= 0xC3FF03FF; \
1.3540 + REG_GPIO_GPALR(2) |= 0x24005400; \
1.3541 +} while (0)
1.3542 +
1.3543 +#define __gpio_as_i2s_slave() \
1.3544 +do { \
1.3545 + REG_GPIO_GPALR(2) &= 0xC3FF0CFF; \
1.3546 + REG_GPIO_GPALR(2) |= 0x14005100; \
1.3547 +} while (0)
1.3548 +
1.3549 +#define __gpio_as_i2s_master() \
1.3550 +do { \
1.3551 + REG_GPIO_GPALR(2) &= 0xC3FF0CFF; \
1.3552 + REG_GPIO_GPALR(2) |= 0x28005100; \
1.3553 +} while (0)
1.3554 +
1.3555 +#define __gpio_as_eth() \
1.3556 +do { \
1.3557 + REG_GPIO_GPAUR(3) &= 0xFC000000; \
1.3558 + REG_GPIO_GPAUR(3) |= 0x01555555; \
1.3559 +} while (0)
1.3560 +
1.3561 +#define __gpio_as_pwm() \
1.3562 +do { \
1.3563 + REG_GPIO_GPAUR(2) &= 0x0FFFFFFF; \
1.3564 + REG_GPIO_GPAUR(2) |= 0x50000000; \
1.3565 +} while (0)
1.3566 +
1.3567 +#define __gpio_as_ps2() \
1.3568 +do { \
1.3569 + REG_GPIO_GPALR(1) &= 0xFFFFFFF0; \
1.3570 + REG_GPIO_GPALR(1) |= 0x00000005; \
1.3571 +} while (0)
1.3572 +
1.3573 +#define __gpio_as_uprt() \
1.3574 +do { \
1.3575 + REG_GPIO_GPALR(1) &= 0x0000000F; \
1.3576 + REG_GPIO_GPALR(1) |= 0x55555550; \
1.3577 + REG_GPIO_GPALR(3) &= 0xC0000000; \
1.3578 + REG_GPIO_GPALR(3) |= 0x15555555; \
1.3579 +} while (0)
1.3580 +
1.3581 +#define __gpio_as_cim() \
1.3582 +do { \
1.3583 + REG_GPIO_GPALR(0) &= 0xFF000000; \
1.3584 + REG_GPIO_GPALR(0) |= 0x00555555; \
1.3585 +} while (0)
1.3586 +
1.3587 +/***************************************************************************
1.3588 + * HARB
1.3589 + ***************************************************************************/
1.3590 +
1.3591 +#define __harb_usb0_udc() \
1.3592 +do { \
1.3593 + REG_HARB_HAPOR &= ~HARB_HAPOR_UCHSEL; \
1.3594 +} while (0)
1.3595 +
1.3596 +#define __harb_usb0_uhc() \
1.3597 +do { \
1.3598 + REG_HARB_HAPOR |= HARB_HAPOR_UCHSEL; \
1.3599 +} while (0)
1.3600 +
1.3601 +#define __harb_set_priority(n) \
1.3602 +do { \
1.3603 + REG_HARB_HAPOR = ((REG_HARB_HAPOR & ~HARB_HAPOR_PRIO_MASK) | n); \
1.3604 +} while (0)
1.3605 +
1.3606 +/***************************************************************************
1.3607 + * I2C
1.3608 + ***************************************************************************/
1.3609 +
1.3610 +#define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE )
1.3611 +#define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE )
1.3612 +
1.3613 +#define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA )
1.3614 +#define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO )
1.3615 +#define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC )
1.3616 +#define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC )
1.3617 +
1.3618 +#define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF )
1.3619 +#define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF )
1.3620 +#define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF )
1.3621 +
1.3622 +#define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) )
1.3623 +#define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY )
1.3624 +#define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND )
1.3625 +
1.3626 +#define __i2c_set_clk(dev_clk, i2c_clk) \
1.3627 + ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 )
1.3628 +
1.3629 +#define __i2c_read() ( REG_I2C_DR )
1.3630 +#define __i2c_write(val) ( REG_I2C_DR = (val) )
1.3631 +
1.3632 +/***************************************************************************
1.3633 + * UDC
1.3634 + ***************************************************************************/
1.3635 +
1.3636 +#define __udc_set_16bit_phy() ( REG_UDC_DevCFGR |= UDC_DevCFGR_PI )
1.3637 +#define __udc_set_8bit_phy() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_PI )
1.3638 +
1.3639 +#define __udc_enable_sync_frame() ( REG_UDC_DevCFGR |= UDC_DevCFGR_SS )
1.3640 +#define __udc_disable_sync_frame() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_SS )
1.3641 +
1.3642 +#define __udc_self_powered() ( REG_UDC_DevCFGR |= UDC_DevCFGR_SP )
1.3643 +#define __udc_bus_powered() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_SP )
1.3644 +
1.3645 +#define __udc_enable_remote_wakeup() ( REG_UDC_DevCFGR |= UDC_DevCFGR_RW )
1.3646 +#define __udc_disable_remote_wakeup() ( REG_UDC_DevCFGR &= ~UDC_DevCFGR_RW )
1.3647 +
1.3648 +#define __udc_set_speed_high() \
1.3649 +do { \
1.3650 + REG_UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; \
1.3651 + REG_UDC_DevCFGR |= UDC_DevCFGR_SPD_HS; \
1.3652 +} while (0)
1.3653 +
1.3654 +#define __udc_set_speed_full() \
1.3655 +do { \
1.3656 + REG_UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; \
1.3657 + REG_UDC_DevCFGR |= UDC_DevCFGR_SPD_FS; \
1.3658 +} while (0)
1.3659 +
1.3660 +#define __udc_set_speed_low() \
1.3661 +do { \
1.3662 + REG_UDC_DevCFGR &= ~UDC_DevCFGR_SPD_MASK; \
1.3663 + REG_UDC_DevCFGR |= UDC_DevCFGR_SPD_LS; \
1.3664 +} while (0)
1.3665 +
1.3666 +
1.3667 +#define __udc_set_dma_mode() ( REG_UDC_DevCR |= UDC_DevCR_DM )
1.3668 +#define __udc_set_slave_mode() ( REG_UDC_DevCR &= ~UDC_DevCR_DM )
1.3669 +#define __udc_set_big_endian() ( REG_UDC_DevCR |= UDC_DevCR_BE )
1.3670 +#define __udc_set_little_endian() ( REG_UDC_DevCR &= ~UDC_DevCR_BE )
1.3671 +#define __udc_generate_resume() ( REG_UDC_DevCR |= UDC_DevCR_RES )
1.3672 +#define __udc_clear_resume() ( REG_UDC_DevCR &= ~UDC_DevCR_RES )
1.3673 +
1.3674 +
1.3675 +#define __udc_get_enumarated_speed() ( REG_UDC_DevSR & UDC_DevSR_ENUMSPD_MASK )
1.3676 +#define __udc_suspend_detected() ( REG_UDC_DevSR & UDC_DevSR_SUSP )
1.3677 +#define __udc_get_alternate_setting() ( (REG_UDC_DevSR & UDC_DevSR_ALT_MASK) >> UDC_DevSR_ALT_BIT )
1.3678 +#define __udc_get_interface_number() ( (REG_UDC_DevSR & UDC_DevSR_INTF_MASK) >> UDC_DevSR_INTF_BIT )
1.3679 +#define __udc_get_config_number() ( (REG_UDC_DevSR & UDC_DevSR_CFG_MASK) >> UDC_DevSR_CFG_BIT )
1.3680 +
1.3681 +
1.3682 +#define __udc_sof_detected(r) ( (r) & UDC_DevIntR_SOF )
1.3683 +#define __udc_usb_suspend_detected(r) ( (r) & UDC_DevIntR_US )
1.3684 +#define __udc_usb_reset_detected(r) ( (r) & UDC_DevIntR_UR )
1.3685 +#define __udc_set_interface_detected(r) ( (r) & UDC_DevIntR_SI )
1.3686 +#define __udc_set_config_detected(r) ( (r) & UDC_DevIntR_SC )
1.3687 +
1.3688 +#define __udc_clear_sof() ( REG_UDC_DevIntR |= UDC_DevIntR_SOF )
1.3689 +#define __udc_clear_usb_suspend() ( REG_UDC_DevIntR |= UDC_DevIntR_US )
1.3690 +#define __udc_clear_usb_reset() ( REG_UDC_DevIntR |= UDC_DevIntR_UR )
1.3691 +#define __udc_clear_set_interface() ( REG_UDC_DevIntR |= UDC_DevIntR_SI )
1.3692 +#define __udc_clear_set_config() ( REG_UDC_DevIntR |= UDC_DevIntR_SC )
1.3693 +
1.3694 +#define __udc_mask_sof() ( REG_UDC_DevIntMR |= UDC_DevIntR_SOF )
1.3695 +#define __udc_mask_usb_suspend() ( REG_UDC_DevIntMR |= UDC_DevIntR_US )
1.3696 +#define __udc_mask_usb_reset() ( REG_UDC_DevIntMR |= UDC_DevIntR_UR )
1.3697 +#define __udc_mask_set_interface() ( REG_UDC_DevIntMR |= UDC_DevIntR_SI )
1.3698 +#define __udc_mask_set_config() ( REG_UDC_DevIntMR |= UDC_DevIntR_SC )
1.3699 +#define __udc_mask_all_dev_intrs() \
1.3700 + ( REG_UDC_DevIntMR = UDC_DevIntR_SOF | UDC_DevIntR_US | \
1.3701 + UDC_DevIntR_UR | UDC_DevIntR_SI | UDC_DevIntR_SC )
1.3702 +
1.3703 +#define __udc_unmask_sof() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_SOF )
1.3704 +#define __udc_unmask_usb_suspend() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_US )
1.3705 +#define __udc_unmask_usb_reset() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_UR )
1.3706 +#define __udc_unmask_set_interface() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_SI )
1.3707 +#define __udc_unmask_set_config() ( REG_UDC_DevIntMR &= ~UDC_DevIntR_SC )
1.3708 +#if 0
1.3709 +#define __udc_unmask_all_dev_intrs() \
1.3710 + ( REG_UDC_DevIntMR = ~(UDC_DevIntR_SOF | UDC_DevIntR_US | \
1.3711 + UDC_DevIntR_UR | UDC_DevIntR_SI | UDC_DevIntR_SC) )
1.3712 +#else
1.3713 +#define __udc_unmask_all_dev_intrs() \
1.3714 + ( REG_UDC_DevIntMR = 0x00000000 )
1.3715 +#endif
1.3716 +
1.3717 +
1.3718 +#define __udc_ep0out_irq_detected(epintr) \
1.3719 + ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 0)) & 0x1 )
1.3720 +#define __udc_ep5out_irq_detected(epintr) \
1.3721 + ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 5)) & 0x1 )
1.3722 +#define __udc_ep6out_irq_detected(epintr) \
1.3723 + ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 6)) & 0x1 )
1.3724 +#define __udc_ep7out_irq_detected(epintr) \
1.3725 + ( (((epintr) & UDC_EPIntR_OUTEP_MASK) >> (UDC_EPIntR_OUTEP_BIT + 7)) & 0x1 )
1.3726 +
1.3727 +#define __udc_ep0in_irq_detected(epintr) \
1.3728 + ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 0)) & 0x1 )
1.3729 +#define __udc_ep1in_irq_detected(epintr) \
1.3730 + ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 1)) & 0x1 )
1.3731 +#define __udc_ep2in_irq_detected(epintr) \
1.3732 + ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 2)) & 0x1 )
1.3733 +#define __udc_ep3in_irq_detected(epintr) \
1.3734 + ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 3)) & 0x1 )
1.3735 +#define __udc_ep4in_irq_detected(epintr) \
1.3736 + ( (((epintr) & UDC_EPIntR_INEP_MASK) >> (UDC_EPIntR_INEP_BIT + 4)) & 0x1 )
1.3737 +
1.3738 +
1.3739 +#define __udc_mask_ep0out_irq() \
1.3740 + ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 0)) )
1.3741 +#define __udc_mask_ep5out_irq() \
1.3742 + ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 5)) )
1.3743 +#define __udc_mask_ep6out_irq() \
1.3744 + ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 6)) )
1.3745 +#define __udc_mask_ep7out_irq() \
1.3746 + ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_OUTEP_BIT + 7)) )
1.3747 +
1.3748 +#define __udc_unmask_ep0out_irq() \
1.3749 + ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 0)) )
1.3750 +#define __udc_unmask_ep5out_irq() \
1.3751 + ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 5)) )
1.3752 +#define __udc_unmask_ep6out_irq() \
1.3753 + ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 6)) )
1.3754 +#define __udc_unmask_ep7out_irq() \
1.3755 + ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_OUTEP_BIT + 7)) )
1.3756 +
1.3757 +#define __udc_mask_ep0in_irq() \
1.3758 + ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 0)) )
1.3759 +#define __udc_mask_ep1in_irq() \
1.3760 + ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 1)) )
1.3761 +#define __udc_mask_ep2in_irq() \
1.3762 + ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 2)) )
1.3763 +#define __udc_mask_ep3in_irq() \
1.3764 + ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 3)) )
1.3765 +#define __udc_mask_ep4in_irq() \
1.3766 + ( REG_UDC_EPIntMR |= (1 << (UDC_EPIntMR_INEP_BIT + 4)) )
1.3767 +
1.3768 +#define __udc_unmask_ep0in_irq() \
1.3769 + ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 0)) )
1.3770 +#define __udc_unmask_ep1in_irq() \
1.3771 + ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 1)) )
1.3772 +#define __udc_unmask_ep2in_irq() \
1.3773 + ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 2)) )
1.3774 +#define __udc_unmask_ep3in_irq() \
1.3775 + ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 3)) )
1.3776 +#define __udc_unmask_ep4in_irq() \
1.3777 + ( REG_UDC_EPIntMR &= ~(1 << (UDC_EPIntMR_INEP_BIT + 4)) )
1.3778 +
1.3779 +#define __udc_mask_all_ep_intrs() \
1.3780 + ( REG_UDC_EPIntMR = 0xffffffff )
1.3781 +#define __udc_unmask_all_ep_intrs() \
1.3782 + ( REG_UDC_EPIntMR = 0x00000000 )
1.3783 +
1.3784 +
1.3785 +/* ep0 only CTRL, ep1 only INTR, ep2/3/5/6 only BULK, ep4/7 only ISO */
1.3786 +#define __udc_config_endpoint_type() \
1.3787 +do { \
1.3788 + REG_UDC_EP0InCR = (REG_UDC_EP0InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_CTRL; \
1.3789 + REG_UDC_EP0OutCR = (REG_UDC_EP0OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_CTRL; \
1.3790 + REG_UDC_EP1InCR = (REG_UDC_EP1InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_INTR; \
1.3791 + REG_UDC_EP2InCR = (REG_UDC_EP2InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \
1.3792 + REG_UDC_EP3InCR = (REG_UDC_EP3InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \
1.3793 + REG_UDC_EP4InCR = (REG_UDC_EP4InCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_ISO; \
1.3794 + REG_UDC_EP5OutCR = (REG_UDC_EP5OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \
1.3795 + REG_UDC_EP6OutCR = (REG_UDC_EP6OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_BULK; \
1.3796 + REG_UDC_EP7OutCR = (REG_UDC_EP7OutCR & ~UDC_EPCR_ET_MASK) | UDC_EPCR_ET_ISO; \
1.3797 +} while (0)
1.3798 +
1.3799 +#define __udc_enable_ep0out_snoop_mode() ( REG_UDC_EP0OutCR |= UDC_EPCR_SN )
1.3800 +#define __udc_enable_ep5out_snoop_mode() ( REG_UDC_EP5OutCR |= UDC_EPCR_SN )
1.3801 +#define __udc_enable_ep6out_snoop_mode() ( REG_UDC_EP6OutCR |= UDC_EPCR_SN )
1.3802 +#define __udc_enable_ep7out_snoop_mode() ( REG_UDC_EP7OutCR |= UDC_EPCR_SN )
1.3803 +
1.3804 +#define __udc_disable_ep0out_snoop_mode() ( REG_UDC_EP0OutCR &= ~UDC_EPCR_SN )
1.3805 +#define __udc_disable_ep5out_snoop_mode() ( REG_UDC_EP5OutCR &= ~UDC_EPCR_SN )
1.3806 +#define __udc_disable_ep6out_snoop_mode() ( REG_UDC_EP6OutCR &= ~UDC_EPCR_SN )
1.3807 +#define __udc_disable_ep7out_snoop_mode() ( REG_UDC_EP7OutCR &= ~UDC_EPCR_SN )
1.3808 +
1.3809 +#define __udc_flush_ep0in_fifo() ( REG_UDC_EP0InCR |= UDC_EPCR_F )
1.3810 +#define __udc_flush_ep1in_fifo() ( REG_UDC_EP1InCR |= UDC_EPCR_F )
1.3811 +#define __udc_flush_ep2in_fifo() ( REG_UDC_EP2InCR |= UDC_EPCR_F )
1.3812 +#define __udc_flush_ep3in_fifo() ( REG_UDC_EP3InCR |= UDC_EPCR_F )
1.3813 +#define __udc_flush_ep4in_fifo() ( REG_UDC_EP4InCR |= UDC_EPCR_F )
1.3814 +
1.3815 +#define __udc_unflush_ep0in_fifo() ( REG_UDC_EP0InCR &= ~UDC_EPCR_F )
1.3816 +#define __udc_unflush_ep1in_fifo() ( REG_UDC_EP1InCR &= ~UDC_EPCR_F )
1.3817 +#define __udc_unflush_ep2in_fifo() ( REG_UDC_EP2InCR &= ~UDC_EPCR_F )
1.3818 +#define __udc_unflush_ep3in_fifo() ( REG_UDC_EP3InCR &= ~UDC_EPCR_F )
1.3819 +#define __udc_unflush_ep4in_fifo() ( REG_UDC_EP4InCR &= ~UDC_EPCR_F )
1.3820 +
1.3821 +#define __udc_enable_ep0in_stall() ( REG_UDC_EP0InCR |= UDC_EPCR_S )
1.3822 +#define __udc_enable_ep0out_stall() ( REG_UDC_EP0OutCR |= UDC_EPCR_S )
1.3823 +#define __udc_enable_ep1in_stall() ( REG_UDC_EP1InCR |= UDC_EPCR_S )
1.3824 +#define __udc_enable_ep2in_stall() ( REG_UDC_EP2InCR |= UDC_EPCR_S )
1.3825 +#define __udc_enable_ep3in_stall() ( REG_UDC_EP3InCR |= UDC_EPCR_S )
1.3826 +#define __udc_enable_ep4in_stall() ( REG_UDC_EP4InCR |= UDC_EPCR_S )
1.3827 +#define __udc_enable_ep5out_stall() ( REG_UDC_EP5OutCR |= UDC_EPCR_S )
1.3828 +#define __udc_enable_ep6out_stall() ( REG_UDC_EP6OutCR |= UDC_EPCR_S )
1.3829 +#define __udc_enable_ep7out_stall() ( REG_UDC_EP7OutCR |= UDC_EPCR_S )
1.3830 +
1.3831 +#define __udc_disable_ep0in_stall() ( REG_UDC_EP0InCR &= ~UDC_EPCR_S )
1.3832 +#define __udc_disable_ep0out_stall() ( REG_UDC_EP0OutCR &= ~UDC_EPCR_S )
1.3833 +#define __udc_disable_ep1in_stall() ( REG_UDC_EP1InCR &= ~UDC_EPCR_S )
1.3834 +#define __udc_disable_ep2in_stall() ( REG_UDC_EP2InCR &= ~UDC_EPCR_S )
1.3835 +#define __udc_disable_ep3in_stall() ( REG_UDC_EP3InCR &= ~UDC_EPCR_S )
1.3836 +#define __udc_disable_ep4in_stall() ( REG_UDC_EP4InCR &= ~UDC_EPCR_S )
1.3837 +#define __udc_disable_ep5out_stall() ( REG_UDC_EP5OutCR &= ~UDC_EPCR_S )
1.3838 +#define __udc_disable_ep6out_stall() ( REG_UDC_EP6OutCR &= ~UDC_EPCR_S )
1.3839 +#define __udc_disable_ep7out_stall() ( REG_UDC_EP7OutCR &= ~UDC_EPCR_S )
1.3840 +
1.3841 +
1.3842 +#define __udc_ep0out_packet_size() \
1.3843 + ( (REG_UDC_EP0OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT )
1.3844 +#define __udc_ep5out_packet_size() \
1.3845 + ( (REG_UDC_EP5OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT )
1.3846 +#define __udc_ep6out_packet_size() \
1.3847 + ( (REG_UDC_EP6OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT )
1.3848 +#define __udc_ep7out_packet_size() \
1.3849 + ( (REG_UDC_EP7OutSR & UDC_EPSR_RXPKTSIZE_MASK) >> UDC_EPSR_RXPKTSIZE_BIT )
1.3850 +
1.3851 +#define __udc_ep0in_received_intoken() ( (REG_UDC_EP0InSR & UDC_EPSR_IN) )
1.3852 +#define __udc_ep1in_received_intoken() ( (REG_UDC_EP1InSR & UDC_EPSR_IN) )
1.3853 +#define __udc_ep2in_received_intoken() ( (REG_UDC_EP2InSR & UDC_EPSR_IN) )
1.3854 +#define __udc_ep3in_received_intoken() ( (REG_UDC_EP3InSR & UDC_EPSR_IN) )
1.3855 +#define __udc_ep4in_received_intoken() ( (REG_UDC_EP4InSR & UDC_EPSR_IN) )
1.3856 +
1.3857 +#define __udc_ep0out_received_none() \
1.3858 + ( (REG_UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE )
1.3859 +#define __udc_ep0out_received_data() \
1.3860 + ( (REG_UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA )
1.3861 +#define __udc_ep0out_received_setup() \
1.3862 + ( (REG_UDC_EP0OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP )
1.3863 +
1.3864 +#define __udc_ep5out_received_none() \
1.3865 + ( (REG_UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE )
1.3866 +#define __udc_ep5out_received_data() \
1.3867 + ( (REG_UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA )
1.3868 +#define __udc_ep5out_received_setup() \
1.3869 + ( (REG_UDC_EP5OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP )
1.3870 +
1.3871 +#define __udc_ep6out_received_none() \
1.3872 + ( (REG_UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE )
1.3873 +#define __udc_ep6out_received_data() \
1.3874 + ( (REG_UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA )
1.3875 +#define __udc_ep6out_received_setup() \
1.3876 + ( (REG_UDC_EP6OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP )
1.3877 +
1.3878 +#define __udc_ep7out_received_none() \
1.3879 + ( (REG_UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_NONE )
1.3880 +#define __udc_ep7out_received_data() \
1.3881 + ( (REG_UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVDATA )
1.3882 +#define __udc_ep7out_received_setup() \
1.3883 + ( (REG_UDC_EP7OutSR & UDC_EPSR_OUT_MASK) == UDC_EPSR_OUT_RCVSETUP )
1.3884 +
1.3885 +/* ep7out ISO only */
1.3886 +#define __udc_ep7out_get_pid() \
1.3887 + ( (REG_UDC_EP7OutSR & UDC_EPSR_PID_MASK) >> UDC_EPSR_PID_BIT )
1.3888 +
1.3889 +
1.3890 +#define __udc_ep0in_set_buffer_size(n) ( REG_UDC_EP0InBSR = (n) )
1.3891 +#define __udc_ep1in_set_buffer_size(n) ( REG_UDC_EP1InBSR = (n) )
1.3892 +#define __udc_ep2in_set_buffer_size(n) ( REG_UDC_EP2InBSR = (n) )
1.3893 +#define __udc_ep3in_set_buffer_size(n) ( REG_UDC_EP3InBSR = (n) )
1.3894 +#define __udc_ep4in_set_buffer_size(n) ( REG_UDC_EP4InBSR = (n) )
1.3895 +
1.3896 +#define __udc_ep0out_get_frame_number(n) ( UDC_EP0OutPFNR )
1.3897 +#define __udc_ep5out_get_frame_number(n) ( UDC_EP5OutPFNR )
1.3898 +#define __udc_ep6out_get_frame_number(n) ( UDC_EP6OutPFNR )
1.3899 +#define __udc_ep7out_get_frame_number(n) ( UDC_EP7OutPFNR )
1.3900 +
1.3901 +
1.3902 +#define __udc_ep0in_set_max_packet_size(n) ( REG_UDC_EP0InMPSR = (n) )
1.3903 +#define __udc_ep0out_set_max_packet_size(n) ( REG_UDC_EP0OutMPSR = (n) )
1.3904 +#define __udc_ep1in_set_max_packet_size(n) ( REG_UDC_EP1InMPSR = (n) )
1.3905 +#define __udc_ep2in_set_max_packet_size(n) ( REG_UDC_EP2InMPSR = (n) )
1.3906 +#define __udc_ep3in_set_max_packet_size(n) ( REG_UDC_EP3InMPSR = (n) )
1.3907 +#define __udc_ep4in_set_max_packet_size(n) ( REG_UDC_EP4InMPSR = (n) )
1.3908 +#define __udc_ep5out_set_max_packet_size(n) ( REG_UDC_EP5OutMPSR = (n) )
1.3909 +#define __udc_ep6out_set_max_packet_size(n) ( REG_UDC_EP6OutMPSR = (n) )
1.3910 +#define __udc_ep7out_set_max_packet_size(n) ( REG_UDC_EP7OutMPSR = (n) )
1.3911 +
1.3912 +/* set to 0xFFFF for UDC */
1.3913 +#define __udc_set_setup_command_address(n) ( REG_UDC_STCMAR = (n) )
1.3914 +
1.3915 +/* Init and configure EPxInfR(x=0,1,2,3,4,5,6,7)
1.3916 + * c: Configuration number to which this endpoint belongs
1.3917 + * i: Interface number to which this endpoint belongs
1.3918 + * a: Alternate setting to which this endpoint belongs
1.3919 + * p: max Packet size of this endpoint
1.3920 + */
1.3921 +
1.3922 +#define __udc_ep0info_init(c,i,a,p) \
1.3923 +do { \
1.3924 + REG_UDC_EP0InfR &= ~UDC_EPInfR_MPS_MASK; \
1.3925 + REG_UDC_EP0InfR |= ((p) << UDC_EPInfR_MPS_BIT); \
1.3926 + REG_UDC_EP0InfR &= ~UDC_EPInfR_ALTS_MASK; \
1.3927 + REG_UDC_EP0InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \
1.3928 + REG_UDC_EP0InfR &= ~UDC_EPInfR_IFN_MASK; \
1.3929 + REG_UDC_EP0InfR |= ((i) << UDC_EPInfR_IFN_BIT); \
1.3930 + REG_UDC_EP0InfR &= ~UDC_EPInfR_CGN_MASK; \
1.3931 + REG_UDC_EP0InfR |= ((c) << UDC_EPInfR_CGN_BIT); \
1.3932 + REG_UDC_EP0InfR &= ~UDC_EPInfR_EPT_MASK; \
1.3933 + REG_UDC_EP0InfR |= UDC_EPInfR_EPT_CTRL; \
1.3934 + REG_UDC_EP0InfR &= ~UDC_EPInfR_EPD; \
1.3935 + REG_UDC_EP0InfR |= UDC_EPInfR_EPD_OUT; \
1.3936 + REG_UDC_EP0InfR &= ~UDC_EPInfR_EPN_MASK; \
1.3937 + REG_UDC_EP0InfR |= (0 << UDC_EPInfR_EPN_BIT); \
1.3938 +} while (0)
1.3939 +
1.3940 +#define __udc_ep1info_init(c,i,a,p) \
1.3941 +do { \
1.3942 + REG_UDC_EP1InfR &= ~UDC_EPInfR_MPS_MASK; \
1.3943 + REG_UDC_EP1InfR |= ((p) << UDC_EPInfR_MPS_BIT); \
1.3944 + REG_UDC_EP1InfR &= ~UDC_EPInfR_ALTS_MASK; \
1.3945 + REG_UDC_EP1InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \
1.3946 + REG_UDC_EP1InfR &= ~UDC_EPInfR_IFN_MASK; \
1.3947 + REG_UDC_EP1InfR |= ((i) << UDC_EPInfR_IFN_BIT); \
1.3948 + REG_UDC_EP1InfR &= ~UDC_EPInfR_CGN_MASK; \
1.3949 + REG_UDC_EP1InfR |= ((c) << UDC_EPInfR_CGN_BIT); \
1.3950 + REG_UDC_EP1InfR &= ~UDC_EPInfR_EPT_MASK; \
1.3951 + REG_UDC_EP1InfR |= UDC_EPInfR_EPT_INTR; \
1.3952 + REG_UDC_EP1InfR &= ~UDC_EPInfR_EPD; \
1.3953 + REG_UDC_EP1InfR |= UDC_EPInfR_EPD_IN; \
1.3954 + REG_UDC_EP1InfR &= ~UDC_EPInfR_EPN_MASK; \
1.3955 + REG_UDC_EP1InfR |= (1 << UDC_EPInfR_EPN_BIT); \
1.3956 +} while (0)
1.3957 +
1.3958 +#define __udc_ep2info_init(c,i,a,p) \
1.3959 +do { \
1.3960 + REG_UDC_EP2InfR &= ~UDC_EPInfR_MPS_MASK; \
1.3961 + REG_UDC_EP2InfR |= ((p) << UDC_EPInfR_MPS_BIT); \
1.3962 + REG_UDC_EP2InfR &= ~UDC_EPInfR_ALTS_MASK; \
1.3963 + REG_UDC_EP2InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \
1.3964 + REG_UDC_EP2InfR &= ~UDC_EPInfR_IFN_MASK; \
1.3965 + REG_UDC_EP2InfR |= ((i) << UDC_EPInfR_IFN_BIT); \
1.3966 + REG_UDC_EP2InfR &= ~UDC_EPInfR_CGN_MASK; \
1.3967 + REG_UDC_EP2InfR |= ((c) << UDC_EPInfR_CGN_BIT); \
1.3968 + REG_UDC_EP2InfR &= ~UDC_EPInfR_EPT_MASK; \
1.3969 + REG_UDC_EP2InfR |= UDC_EPInfR_EPT_BULK; \
1.3970 + REG_UDC_EP2InfR &= ~UDC_EPInfR_EPD; \
1.3971 + REG_UDC_EP2InfR |= UDC_EPInfR_EPD_IN; \
1.3972 + REG_UDC_EP2InfR &= ~UDC_EPInfR_EPN_MASK; \
1.3973 + REG_UDC_EP2InfR |= (2 << UDC_EPInfR_EPN_BIT); \
1.3974 +} while (0)
1.3975 +
1.3976 +#define __udc_ep3info_init(c,i,a,p) \
1.3977 +do { \
1.3978 + REG_UDC_EP3InfR &= ~UDC_EPInfR_MPS_MASK; \
1.3979 + REG_UDC_EP3InfR |= ((p) << UDC_EPInfR_MPS_BIT); \
1.3980 + REG_UDC_EP3InfR &= ~UDC_EPInfR_ALTS_MASK; \
1.3981 + REG_UDC_EP3InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \
1.3982 + REG_UDC_EP3InfR &= ~UDC_EPInfR_IFN_MASK; \
1.3983 + REG_UDC_EP3InfR |= ((i) << UDC_EPInfR_IFN_BIT); \
1.3984 + REG_UDC_EP3InfR &= ~UDC_EPInfR_CGN_MASK; \
1.3985 + REG_UDC_EP3InfR |= ((c) << UDC_EPInfR_CGN_BIT); \
1.3986 + REG_UDC_EP3InfR &= ~UDC_EPInfR_EPT_MASK; \
1.3987 + REG_UDC_EP3InfR |= UDC_EPInfR_EPT_BULK; \
1.3988 + REG_UDC_EP3InfR &= ~UDC_EPInfR_EPD; \
1.3989 + REG_UDC_EP3InfR |= UDC_EPInfR_EPD_IN; \
1.3990 + REG_UDC_EP3InfR &= ~UDC_EPInfR_EPN_MASK; \
1.3991 + REG_UDC_EP3InfR |= (3 << UDC_EPInfR_EPN_BIT); \
1.3992 +} while (0)
1.3993 +
1.3994 +#define __udc_ep4info_init(c,i,a,p) \
1.3995 +do { \
1.3996 + REG_UDC_EP4InfR &= ~UDC_EPInfR_MPS_MASK; \
1.3997 + REG_UDC_EP4InfR |= ((p) << UDC_EPInfR_MPS_BIT); \
1.3998 + REG_UDC_EP4InfR &= ~UDC_EPInfR_ALTS_MASK; \
1.3999 + REG_UDC_EP4InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \
1.4000 + REG_UDC_EP4InfR &= ~UDC_EPInfR_IFN_MASK; \
1.4001 + REG_UDC_EP4InfR |= ((i) << UDC_EPInfR_IFN_BIT); \
1.4002 + REG_UDC_EP4InfR &= ~UDC_EPInfR_CGN_MASK; \
1.4003 + REG_UDC_EP4InfR |= ((c) << UDC_EPInfR_CGN_BIT); \
1.4004 + REG_UDC_EP4InfR &= ~UDC_EPInfR_EPT_MASK; \
1.4005 + REG_UDC_EP4InfR |= UDC_EPInfR_EPT_ISO; \
1.4006 + REG_UDC_EP4InfR &= ~UDC_EPInfR_EPD; \
1.4007 + REG_UDC_EP4InfR |= UDC_EPInfR_EPD_IN; \
1.4008 + REG_UDC_EP4InfR &= ~UDC_EPInfR_EPN_MASK; \
1.4009 + REG_UDC_EP4InfR |= (4 << UDC_EPInfR_EPN_BIT); \
1.4010 +} while (0)
1.4011 +
1.4012 +#define __udc_ep5info_init(c,i,a,p) \
1.4013 +do { \
1.4014 + REG_UDC_EP5InfR &= ~UDC_EPInfR_MPS_MASK; \
1.4015 + REG_UDC_EP5InfR |= ((p) << UDC_EPInfR_MPS_BIT); \
1.4016 + REG_UDC_EP5InfR &= ~UDC_EPInfR_ALTS_MASK; \
1.4017 + REG_UDC_EP5InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \
1.4018 + REG_UDC_EP5InfR &= ~UDC_EPInfR_IFN_MASK; \
1.4019 + REG_UDC_EP5InfR |= ((i) << UDC_EPInfR_IFN_BIT); \
1.4020 + REG_UDC_EP5InfR &= ~UDC_EPInfR_CGN_MASK; \
1.4021 + REG_UDC_EP5InfR |= ((c) << UDC_EPInfR_CGN_BIT); \
1.4022 + REG_UDC_EP5InfR &= ~UDC_EPInfR_EPT_MASK; \
1.4023 + REG_UDC_EP5InfR |= UDC_EPInfR_EPT_BULK; \
1.4024 + REG_UDC_EP5InfR &= ~UDC_EPInfR_EPD; \
1.4025 + REG_UDC_EP5InfR |= UDC_EPInfR_EPD_OUT; \
1.4026 + REG_UDC_EP5InfR &= ~UDC_EPInfR_EPN_MASK; \
1.4027 + REG_UDC_EP5InfR |= (5 << UDC_EPInfR_EPN_BIT); \
1.4028 +} while (0)
1.4029 +
1.4030 +#define __udc_ep6info_init(c,i,a,p) \
1.4031 +do { \
1.4032 + REG_UDC_EP6InfR &= ~UDC_EPInfR_MPS_MASK; \
1.4033 + REG_UDC_EP6InfR |= ((p) << UDC_EPInfR_MPS_BIT); \
1.4034 + REG_UDC_EP6InfR &= ~UDC_EPInfR_ALTS_MASK; \
1.4035 + REG_UDC_EP6InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \
1.4036 + REG_UDC_EP6InfR &= ~UDC_EPInfR_IFN_MASK; \
1.4037 + REG_UDC_EP6InfR |= ((i) << UDC_EPInfR_IFN_BIT); \
1.4038 + REG_UDC_EP6InfR &= ~UDC_EPInfR_CGN_MASK; \
1.4039 + REG_UDC_EP6InfR |= ((c) << UDC_EPInfR_CGN_BIT); \
1.4040 + REG_UDC_EP6InfR &= ~UDC_EPInfR_EPT_MASK; \
1.4041 + REG_UDC_EP6InfR |= UDC_EPInfR_EPT_BULK; \
1.4042 + REG_UDC_EP6InfR &= ~UDC_EPInfR_EPD; \
1.4043 + REG_UDC_EP6InfR |= UDC_EPInfR_EPD_OUT; \
1.4044 + REG_UDC_EP6InfR &= ~UDC_EPInfR_EPN_MASK; \
1.4045 + REG_UDC_EP6InfR |= (6 << UDC_EPInfR_EPN_BIT); \
1.4046 +} while (0)
1.4047 +
1.4048 +#define __udc_ep7info_init(c,i,a,p) \
1.4049 +do { \
1.4050 + REG_UDC_EP7InfR &= ~UDC_EPInfR_MPS_MASK; \
1.4051 + REG_UDC_EP7InfR |= ((p) << UDC_EPInfR_MPS_BIT); \
1.4052 + REG_UDC_EP7InfR &= ~UDC_EPInfR_ALTS_MASK; \
1.4053 + REG_UDC_EP7InfR |= ((a) << UDC_EPInfR_ALTS_BIT); \
1.4054 + REG_UDC_EP7InfR &= ~UDC_EPInfR_IFN_MASK; \
1.4055 + REG_UDC_EP7InfR |= ((i) << UDC_EPInfR_IFN_BIT); \
1.4056 + REG_UDC_EP7InfR &= ~UDC_EPInfR_CGN_MASK; \
1.4057 + REG_UDC_EP7InfR |= ((c) << UDC_EPInfR_CGN_BIT); \
1.4058 + REG_UDC_EP7InfR &= ~UDC_EPInfR_EPT_MASK; \
1.4059 + REG_UDC_EP7InfR |= UDC_EPInfR_EPT_ISO; \
1.4060 + REG_UDC_EP7InfR &= ~UDC_EPInfR_EPD; \
1.4061 + REG_UDC_EP7InfR |= UDC_EPInfR_EPD_OUT; \
1.4062 + REG_UDC_EP7InfR &= ~UDC_EPInfR_EPN_MASK; \
1.4063 + REG_UDC_EP7InfR |= (7 << UDC_EPInfR_EPN_BIT); \
1.4064 +} while (0)
1.4065 +
1.4066 +
1.4067 +/***************************************************************************
1.4068 + * DMAC
1.4069 + ***************************************************************************/
1.4070 +
1.4071 +/* n is the DMA channel (0 - 7) */
1.4072 +
1.4073 +#define __dmac_enable_all_channels() \
1.4074 + ( REG_DMAC_DMACR |= DMAC_DMACR_DME | DMAC_DMACR_PR_ROUNDROBIN )
1.4075 +#define __dmac_disable_all_channels() \
1.4076 + ( REG_DMAC_DMACR &= ~DMAC_DMACR_DME )
1.4077 +
1.4078 +/* p=0,1,2,3 */
1.4079 +#define __dmac_set_priority(p) \
1.4080 +do { \
1.4081 + REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \
1.4082 + REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \
1.4083 +} while (0)
1.4084 +
1.4085 +#define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HTR )
1.4086 +#define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AER )
1.4087 +
1.4088 +#define __dmac_enable_channel(n) \
1.4089 + ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_CHDE )
1.4090 +#define __dmac_disable_channel(n) \
1.4091 + ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_CHDE )
1.4092 +#define __dmac_channel_enabled(n) \
1.4093 + ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_CHDE )
1.4094 +
1.4095 +#define __dmac_channel_enable_irq(n) \
1.4096 + ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_TCIE )
1.4097 +#define __dmac_channel_disable_irq(n) \
1.4098 + ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TCIE )
1.4099 +
1.4100 +#define __dmac_channel_transmit_halt_detected(n) \
1.4101 + ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_HLT )
1.4102 +#define __dmac_channel_transmit_end_detected(n) \
1.4103 + ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_TC )
1.4104 +#define __dmac_channel_address_error_detected(n) \
1.4105 + ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_AR )
1.4106 +
1.4107 +#define __dmac_channel_clear_transmit_halt(n) \
1.4108 + ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT )
1.4109 +#define __dmac_channel_clear_transmit_end(n) \
1.4110 + ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TC )
1.4111 +#define __dmac_channel_clear_address_error(n) \
1.4112 + ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR )
1.4113 +
1.4114 +#define __dmac_channel_set_single_mode(n) \
1.4115 + ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TM )
1.4116 +#define __dmac_channel_set_block_mode(n) \
1.4117 + ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_TM )
1.4118 +
1.4119 +#define __dmac_channel_set_transfer_unit_32bit(n) \
1.4120 +do { \
1.4121 + REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \
1.4122 + REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_32b; \
1.4123 +} while (0)
1.4124 +
1.4125 +#define __dmac_channel_set_transfer_unit_16bit(n) \
1.4126 +do { \
1.4127 + REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \
1.4128 + REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_16b; \
1.4129 +} while (0)
1.4130 +
1.4131 +#define __dmac_channel_set_transfer_unit_8bit(n) \
1.4132 +do { \
1.4133 + REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \
1.4134 + REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_8b; \
1.4135 +} while (0)
1.4136 +
1.4137 +#define __dmac_channel_set_transfer_unit_16byte(n) \
1.4138 +do { \
1.4139 + REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \
1.4140 + REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_16B; \
1.4141 +} while (0)
1.4142 +
1.4143 +#define __dmac_channel_set_transfer_unit_32byte(n) \
1.4144 +do { \
1.4145 + REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK; \
1.4146 + REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_32B; \
1.4147 +} while (0)
1.4148 +
1.4149 +/* w=8,16,32 */
1.4150 +#define __dmac_channel_set_dest_port_width(n,w) \
1.4151 +do { \
1.4152 + REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DWDH_MASK; \
1.4153 + REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DWDH_##w; \
1.4154 +} while (0)
1.4155 +
1.4156 +/* w=8,16,32 */
1.4157 +#define __dmac_channel_set_src_port_width(n,w) \
1.4158 +do { \
1.4159 + REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_SWDH_MASK; \
1.4160 + REG_DMAC_DCCSR(n) |= DMAC_DCCSR_SWDH_##w; \
1.4161 +} while (0)
1.4162 +
1.4163 +/* v=0-15 */
1.4164 +#define __dmac_channel_set_rdil(n,v) \
1.4165 +do { \
1.4166 + REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_RDIL_MASK; \
1.4167 + REG_DMAC_DCCSR(n) |= ((v) << DMAC_DCCSR_RDIL_BIT); \
1.4168 +} while (0)
1.4169 +
1.4170 +#define __dmac_channel_dest_addr_fixed(n) \
1.4171 + ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DAM )
1.4172 +#define __dmac_channel_dest_addr_increment(n) \
1.4173 + ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DAM )
1.4174 +
1.4175 +#define __dmac_channel_src_addr_fixed(n) \
1.4176 + ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_SAM )
1.4177 +#define __dmac_channel_src_addr_increment(n) \
1.4178 + ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_SAM )
1.4179 +
1.4180 +#define __dmac_channel_set_eop_high(n) \
1.4181 + ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_EOPM )
1.4182 +#define __dmac_channel_set_eop_low(n) \
1.4183 + ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_EOPM )
1.4184 +
1.4185 +#define __dmac_channel_set_erdm(n,m) \
1.4186 +do { \
1.4187 + REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_SWDH_MASK; \
1.4188 + REG_DMAC_DCCSR(n) |= ((m) << DMAC_DCCSR_ERDM_BIT); \
1.4189 +} while (0)
1.4190 +
1.4191 +#define __dmac_channel_set_eackm(n) \
1.4192 + ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_EACKM )
1.4193 +#define __dmac_channel_clear_eackm(n) \
1.4194 + ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_EACKM )
1.4195 +
1.4196 +#define __dmac_channel_set_eacks(n) \
1.4197 + ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_EACKS )
1.4198 +#define __dmac_channel_clear_eacks(n) \
1.4199 + ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_EACKS )
1.4200 +
1.4201 +
1.4202 +#define __dmac_channel_irq_detected(n) \
1.4203 + ( REG_DMAC_DCCSR(n) & (DMAC_DCCSR_TC | DMAC_DCCSR_AR) )
1.4204 +
1.4205 +static __inline__ int __dmac_get_irq(void)
1.4206 +{
1.4207 + int i;
1.4208 + for (i=0;i<NUM_DMA;i++)
1.4209 + if (__dmac_channel_irq_detected(i))
1.4210 + return i;
1.4211 + return -1;
1.4212 +}
1.4213 +
1.4214 +/***************************************************************************
1.4215 + * AIC (AC'97 & I2S Controller)
1.4216 + ***************************************************************************/
1.4217 +
1.4218 +#define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB )
1.4219 +#define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB )
1.4220 +#define __aic_reset() ( REG_AIC_FR |= AIC_FR_RST )
1.4221 +#define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL )
1.4222 +#define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL )
1.4223 +
1.4224 +#define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD )
1.4225 +#define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) )
1.4226 +
1.4227 +#define __aic_set_transmit_trigger(n) \
1.4228 +do { \
1.4229 + REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \
1.4230 + REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \
1.4231 +} while(0)
1.4232 +
1.4233 +#define __aic_set_receive_trigger(n) \
1.4234 +do { \
1.4235 + REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \
1.4236 + REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \
1.4237 +} while(0)
1.4238 +
1.4239 +#define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC )
1.4240 +#define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC )
1.4241 +#define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL )
1.4242 +#define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL )
1.4243 +#define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF )
1.4244 +#define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF )
1.4245 +
1.4246 +#define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH )
1.4247 +#define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH )
1.4248 +
1.4249 +#define __aic_enable_transmit_intr() \
1.4250 + ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) )
1.4251 +#define __aic_disable_transmit_intr() \
1.4252 + ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) )
1.4253 +#define __aic_enable_receive_intr() \
1.4254 + ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) )
1.4255 +#define __aic_disable_receive_intr() \
1.4256 + ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) )
1.4257 +
1.4258 +#define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS )
1.4259 +#define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS )
1.4260 +#define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS )
1.4261 +#define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS )
1.4262 +
1.4263 +#define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3
1.4264 +#define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4
1.4265 +#define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6
1.4266 +#define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7
1.4267 +#define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8
1.4268 +#define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9
1.4269 +
1.4270 +#define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3
1.4271 +#define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4
1.4272 +#define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6
1.4273 +#define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7
1.4274 +#define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8
1.4275 +#define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9
1.4276 +
1.4277 +#define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK )
1.4278 +#define __ac97_set_xs_mono() \
1.4279 +do { \
1.4280 + REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
1.4281 + REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \
1.4282 +} while(0)
1.4283 +#define __ac97_set_xs_stereo() \
1.4284 +do { \
1.4285 + REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
1.4286 + REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \
1.4287 +} while(0)
1.4288 +
1.4289 +/* In fact, only stereo is support now. */
1.4290 +#define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK )
1.4291 +#define __ac97_set_rs_mono() \
1.4292 +do { \
1.4293 + REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
1.4294 + REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \
1.4295 +} while(0)
1.4296 +#define __ac97_set_rs_stereo() \
1.4297 +do { \
1.4298 + REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
1.4299 + REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \
1.4300 +} while(0)
1.4301 +
1.4302 +#define __ac97_warm_reset_codec() \
1.4303 + do { \
1.4304 + REG_AIC_ACCR2 |= AIC_ACCR2_SA; \
1.4305 + REG_AIC_ACCR2 |= AIC_ACCR2_SS; \
1.4306 + udelay(1); \
1.4307 + REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \
1.4308 + REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \
1.4309 + } while (0)
1.4310 +
1.4311 +//#define Jz_AC97_RESET_BUG 1
1.4312 +#ifndef Jz_AC97_RESET_BUG
1.4313 +#define __ac97_cold_reset_codec() \
1.4314 + do { \
1.4315 + REG_AIC_ACCR2 |= AIC_ACCR2_SA; \
1.4316 + REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \
1.4317 + REG_AIC_ACCR2 |= AIC_ACCR2_SR; \
1.4318 + udelay(1); \
1.4319 + REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \
1.4320 + REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \
1.4321 + } while (0)
1.4322 +#else
1.4323 +#define __ac97_cold_reset_codec() \
1.4324 + do { \
1.4325 + __gpio_as_output(111); /* SDATA_OUT */ \
1.4326 + __gpio_as_output(110); /* SDATA_IN */ \
1.4327 + __gpio_as_output(112); /* SYNC */ \
1.4328 + __gpio_as_output(114); /* RESET# */ \
1.4329 + __gpio_clear_pin(111); \
1.4330 + __gpio_clear_pin(110); \
1.4331 + __gpio_clear_pin(112); \
1.4332 + __gpio_clear_pin(114); \
1.4333 + udelay(2); \
1.4334 + __gpio_set_pin(114); \
1.4335 + udelay(1); \
1.4336 + __gpio_as_ac97(); \
1.4337 + } while (0)
1.4338 +#endif
1.4339 +
1.4340 +/* n=8,16,18,20 */
1.4341 +#define __ac97_set_iass(n) \
1.4342 + ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT )
1.4343 +#define __ac97_set_oass(n) \
1.4344 + ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT )
1.4345 +
1.4346 +#define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL )
1.4347 +#define __i2s_select_left_justified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL )
1.4348 +
1.4349 +/* n=8,16,18,20,24 */
1.4350 +#define __i2s_set_sample_size(n) \
1.4351 + ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )
1.4352 +
1.4353 +#define __i2s_stop_clock() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK )
1.4354 +#define __i2s_start_clock() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK )
1.4355 +
1.4356 +#define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS )
1.4357 +#define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS )
1.4358 +#define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR )
1.4359 +#define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR )
1.4360 +
1.4361 +#define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) )
1.4362 +
1.4363 +#define __aic_get_transmit_resident() \
1.4364 + ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT )
1.4365 +#define __aic_get_receive_count() \
1.4366 + ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT )
1.4367 +
1.4368 +#define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT )
1.4369 +#define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR )
1.4370 +#define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO )
1.4371 +#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM )
1.4372 +#define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY )
1.4373 +
1.4374 +#define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY )
1.4375 +
1.4376 +#define CODEC_READ_CMD (1 << 19)
1.4377 +#define CODEC_WRITE_CMD (0 << 19)
1.4378 +#define CODEC_REG_INDEX_BIT 12
1.4379 +#define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */
1.4380 +#define CODEC_REG_DATA_BIT 4
1.4381 +#define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */
1.4382 +
1.4383 +#define __ac97_out_rcmd_addr(reg) \
1.4384 +do { \
1.4385 + REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
1.4386 +} while (0)
1.4387 +
1.4388 +#define __ac97_out_wcmd_addr(reg) \
1.4389 +do { \
1.4390 + REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
1.4391 +} while (0)
1.4392 +
1.4393 +#define __ac97_out_data(value) \
1.4394 +do { \
1.4395 + REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \
1.4396 +} while (0)
1.4397 +
1.4398 +#define __ac97_in_data() \
1.4399 + ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT )
1.4400 +
1.4401 +#define __ac97_in_status_addr() \
1.4402 + ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT )
1.4403 +
1.4404 +#define __i2s_set_sample_rate(i2sclk, sync) \
1.4405 + ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) )
1.4406 +
1.4407 +#define __aic_write_tfifo(v) ( REG_AIC_DR = (v) )
1.4408 +#define __aic_read_rfifo() ( REG_AIC_DR )
1.4409 +
1.4410 +//
1.4411 +// Define next ops for AC97 compatible
1.4412 +//
1.4413 +
1.4414 +#define AC97_ACSR AIC_ACSR
1.4415 +
1.4416 +#define __ac97_enable() __aic_enable(); __aic_select_ac97()
1.4417 +#define __ac97_disable() __aic_disable()
1.4418 +#define __ac97_reset() __aic_reset()
1.4419 +
1.4420 +#define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
1.4421 +#define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n)
1.4422 +
1.4423 +#define __ac97_enable_record() __aic_enable_record()
1.4424 +#define __ac97_disable_record() __aic_disable_record()
1.4425 +#define __ac97_enable_replay() __aic_enable_replay()
1.4426 +#define __ac97_disable_replay() __aic_disable_replay()
1.4427 +#define __ac97_enable_loopback() __aic_enable_loopback()
1.4428 +#define __ac97_disable_loopback() __aic_disable_loopback()
1.4429 +
1.4430 +#define __ac97_enable_transmit_dma() __aic_enable_transmit_dma()
1.4431 +#define __ac97_disable_transmit_dma() __aic_disable_transmit_dma()
1.4432 +#define __ac97_enable_receive_dma() __aic_enable_receive_dma()
1.4433 +#define __ac97_disable_receive_dma() __aic_disable_receive_dma()
1.4434 +
1.4435 +#define __ac97_transmit_request() __aic_transmit_request()
1.4436 +#define __ac97_receive_request() __aic_receive_request()
1.4437 +#define __ac97_transmit_underrun() __aic_transmit_underrun()
1.4438 +#define __ac97_receive_overrun() __aic_receive_overrun()
1.4439 +
1.4440 +#define __ac97_clear_errors() __aic_clear_errors()
1.4441 +
1.4442 +#define __ac97_get_transmit_resident() __aic_get_transmit_resident()
1.4443 +#define __ac97_get_receive_count() __aic_get_receive_count()
1.4444 +
1.4445 +#define __ac97_enable_transmit_intr() __aic_enable_transmit_intr()
1.4446 +#define __ac97_disable_transmit_intr() __aic_disable_transmit_intr()
1.4447 +#define __ac97_enable_receive_intr() __aic_enable_receive_intr()
1.4448 +#define __ac97_disable_receive_intr() __aic_disable_receive_intr()
1.4449 +
1.4450 +#define __ac97_write_tfifo(v) __aic_write_tfifo(v)
1.4451 +#define __ac97_read_rfifo() __aic_read_rfifo()
1.4452 +
1.4453 +//
1.4454 +// Define next ops for I2S compatible
1.4455 +//
1.4456 +
1.4457 +#define I2S_ACSR AIC_I2SSR
1.4458 +
1.4459 +#define __i2s_enable() __aic_enable(); __aic_select_i2s()
1.4460 +#define __i2s_disable() __aic_disable()
1.4461 +#define __i2s_reset() __aic_reset()
1.4462 +
1.4463 +#define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
1.4464 +#define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n)
1.4465 +
1.4466 +#define __i2s_enable_record() __aic_enable_record()
1.4467 +#define __i2s_disable_record() __aic_disable_record()
1.4468 +#define __i2s_enable_replay() __aic_enable_replay()
1.4469 +#define __i2s_disable_replay() __aic_disable_replay()
1.4470 +#define __i2s_enable_loopback() __aic_enable_loopback()
1.4471 +#define __i2s_disable_loopback() __aic_disable_loopback()
1.4472 +
1.4473 +#define __i2s_enable_transmit_dma() __aic_enable_transmit_dma()
1.4474 +#define __i2s_disable_transmit_dma() __aic_disable_transmit_dma()
1.4475 +#define __i2s_enable_receive_dma() __aic_enable_receive_dma()
1.4476 +#define __i2s_disable_receive_dma() __aic_disable_receive_dma()
1.4477 +
1.4478 +#define __i2s_transmit_request() __aic_transmit_request()
1.4479 +#define __i2s_receive_request() __aic_receive_request()
1.4480 +#define __i2s_transmit_underrun() __aic_transmit_underrun()
1.4481 +#define __i2s_receive_overrun() __aic_receive_overrun()
1.4482 +
1.4483 +#define __i2s_clear_errors() __aic_clear_errors()
1.4484 +
1.4485 +#define __i2s_get_transmit_resident() __aic_get_transmit_resident()
1.4486 +#define __i2s_get_receive_count() __aic_get_receive_count()
1.4487 +
1.4488 +#define __i2s_enable_transmit_intr() __aic_enable_transmit_intr()
1.4489 +#define __i2s_disable_transmit_intr() __aic_disable_transmit_intr()
1.4490 +#define __i2s_enable_receive_intr() __aic_enable_receive_intr()
1.4491 +#define __i2s_disable_receive_intr() __aic_disable_receive_intr()
1.4492 +
1.4493 +#define __i2s_write_tfifo(v) __aic_write_tfifo(v)
1.4494 +#define __i2s_read_rfifo() __aic_read_rfifo()
1.4495 +
1.4496 +#define __i2s_reset_codec() \
1.4497 + do { \
1.4498 + __gpio_as_output(111); /* SDATA_OUT */ \
1.4499 + __gpio_as_input(110); /* SDATA_IN */ \
1.4500 + __gpio_as_output(112); /* SYNC */ \
1.4501 + __gpio_as_output(114); /* RESET# */ \
1.4502 + __gpio_clear_pin(111); \
1.4503 + __gpio_clear_pin(110); \
1.4504 + __gpio_clear_pin(112); \
1.4505 + __gpio_clear_pin(114); \
1.4506 + __gpio_as_i2s_master(); \
1.4507 + } while (0)
1.4508 +
1.4509 +
1.4510 +/***************************************************************************
1.4511 + * LCD
1.4512 + ***************************************************************************/
1.4513 +
1.4514 +#define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS )
1.4515 +#define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS )
1.4516 +
1.4517 +#define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA )
1.4518 +#define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA )
1.4519 +
1.4520 +/* n=1,2,4,8,16 */
1.4521 +#define __lcd_set_bpp(n) \
1.4522 + ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n )
1.4523 +
1.4524 +/* n=4,8,16 */
1.4525 +#define __lcd_set_burst_length(n) \
1.4526 +do { \
1.4527 + REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \
1.4528 + REG_LCD_CTRL |= LCD_CTRL_BST_n##; \
1.4529 +} while (0)
1.4530 +
1.4531 +#define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 )
1.4532 +#define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 )
1.4533 +
1.4534 +#define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP )
1.4535 +#define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP )
1.4536 +
1.4537 +/* n=2,4,16 */
1.4538 +#define __lcd_set_stn_frc(n) \
1.4539 +do { \
1.4540 + REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \
1.4541 + REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \
1.4542 +} while (0)
1.4543 +
1.4544 +
1.4545 +#define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN )
1.4546 +#define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN )
1.4547 +
1.4548 +#define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN )
1.4549 +#define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN )
1.4550 +
1.4551 +#define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM )
1.4552 +#define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM )
1.4553 +
1.4554 +#define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM )
1.4555 +#define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM )
1.4556 +
1.4557 +#define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM )
1.4558 +#define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM )
1.4559 +
1.4560 +#define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 )
1.4561 +#define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 )
1.4562 +
1.4563 +#define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 )
1.4564 +#define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 )
1.4565 +
1.4566 +#define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM )
1.4567 +#define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM )
1.4568 +
1.4569 +#define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM )
1.4570 +#define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM )
1.4571 +
1.4572 +
1.4573 +/* LCD status register indication */
1.4574 +
1.4575 +#define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD )
1.4576 +#define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD )
1.4577 +#define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 )
1.4578 +#define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 )
1.4579 +#define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU )
1.4580 +#define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF )
1.4581 +#define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF )
1.4582 +
1.4583 +#define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU )
1.4584 +#define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF )
1.4585 +#define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF )
1.4586 +
1.4587 +#define __lcd_panel_white() ( REG_LCD_DEV |= LCD_DEV_WHITE )
1.4588 +#define __lcd_panel_black() ( REG_LCD_DEV &= ~LCD_DEV_WHITE )
1.4589 +
1.4590 +/* n=1,2,4,8 for single mono-STN
1.4591 + * n=4,8 for dual mono-STN
1.4592 + */
1.4593 +#define __lcd_set_panel_datawidth(n) \
1.4594 +do { \
1.4595 + REG_LCD_DEV &= ~LCD_DEV_PDW_MASK; \
1.4596 + REG_LCD_DEV |= LCD_DEV_PDW_n##; \
1.4597 +} while (0)
1.4598 +
1.4599 +/* m=LCD_DEV_MODE_GENERUIC_TFT_xxx */
1.4600 +#define __lcd_set_panel_mode(m) \
1.4601 +do { \
1.4602 + REG_LCD_DEV &= ~LCD_DEV_MODE_MASK; \
1.4603 + REG_LCD_DEV |= (m); \
1.4604 +} while(0)
1.4605 +
1.4606 +/* n = 0-255 */
1.4607 +#define __lcd_disable_ac_bias() ( REG_LCD_IO = 0xff )
1.4608 +#define __lcd_set_ac_bias(n) \
1.4609 +do { \
1.4610 + REG_LCD_IO &= ~LCD_IO_ACB_MASK; \
1.4611 + REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT); \
1.4612 +} while(0)
1.4613 +
1.4614 +#define __lcd_io_set_dir() ( REG_LCD_IO |= LCD_IO_DIR )
1.4615 +#define __lcd_io_clr_dir() ( REG_LCD_IO &= ~LCD_IO_DIR )
1.4616 +
1.4617 +#define __lcd_io_set_dep() ( REG_LCD_IO |= LCD_IO_DEP )
1.4618 +#define __lcd_io_clr_dep() ( REG_LCD_IO &= ~LCD_IO_DEP )
1.4619 +
1.4620 +#define __lcd_io_set_vsp() ( REG_LCD_IO |= LCD_IO_VSP )
1.4621 +#define __lcd_io_clr_vsp() ( REG_LCD_IO &= ~LCD_IO_VSP )
1.4622 +
1.4623 +#define __lcd_io_set_hsp() ( REG_LCD_IO |= LCD_IO_HSP )
1.4624 +#define __lcd_io_clr_hsp() ( REG_LCD_IO &= ~LCD_IO_HSP )
1.4625 +
1.4626 +#define __lcd_io_set_pcp() ( REG_LCD_IO |= LCD_IO_PCP )
1.4627 +#define __lcd_io_clr_pcp() ( REG_LCD_IO &= ~LCD_IO_PCP )
1.4628 +
1.4629 +#define __lcd_vsync_get_vps() \
1.4630 + ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT )
1.4631 +
1.4632 +#define __lcd_vsync_get_vpe() \
1.4633 + ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT )
1.4634 +#define __lcd_vsync_set_vpe(n) \
1.4635 +do { \
1.4636 + REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \
1.4637 + REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \
1.4638 +} while (0)
1.4639 +
1.4640 +#define __lcd_hsync_get_hps() \
1.4641 + ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT )
1.4642 +#define __lcd_hsync_set_hps(n) \
1.4643 +do { \
1.4644 + REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \
1.4645 + REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \
1.4646 +} while (0)
1.4647 +
1.4648 +#define __lcd_hsync_get_hpe() \
1.4649 + ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT )
1.4650 +#define __lcd_hsync_set_hpe(n) \
1.4651 +do { \
1.4652 + REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \
1.4653 + REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \
1.4654 +} while (0)
1.4655 +
1.4656 +#define __lcd_vat_get_ht() \
1.4657 + ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT )
1.4658 +#define __lcd_vat_set_ht(n) \
1.4659 +do { \
1.4660 + REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \
1.4661 + REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \
1.4662 +} while (0)
1.4663 +
1.4664 +#define __lcd_vat_get_vt() \
1.4665 + ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT )
1.4666 +#define __lcd_vat_set_vt(n) \
1.4667 +do { \
1.4668 + REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \
1.4669 + REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \
1.4670 +} while (0)
1.4671 +
1.4672 +#define __lcd_dah_get_hds() \
1.4673 + ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT )
1.4674 +#define __lcd_dah_set_hds(n) \
1.4675 +do { \
1.4676 + REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \
1.4677 + REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \
1.4678 +} while (0)
1.4679 +
1.4680 +#define __lcd_dah_get_hde() \
1.4681 + ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT )
1.4682 +#define __lcd_dah_set_hde(n) \
1.4683 +do { \
1.4684 + REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \
1.4685 + REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \
1.4686 +} while (0)
1.4687 +
1.4688 +#define __lcd_dav_get_vds() \
1.4689 + ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT )
1.4690 +#define __lcd_dav_set_vds(n) \
1.4691 +do { \
1.4692 + REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \
1.4693 + REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \
1.4694 +} while (0)
1.4695 +
1.4696 +#define __lcd_dav_get_vde() \
1.4697 + ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT )
1.4698 +#define __lcd_dav_set_vde(n) \
1.4699 +do { \
1.4700 + REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \
1.4701 + REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \
1.4702 +} while (0)
1.4703 +
1.4704 +#define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT )
1.4705 +#define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT )
1.4706 +#define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT )
1.4707 +#define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT )
1.4708 +
1.4709 +#define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT )
1.4710 +#define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT )
1.4711 +#define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT )
1.4712 +#define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT )
1.4713 +
1.4714 +#define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL )
1.4715 +#define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL )
1.4716 +
1.4717 +#define __lcd_cmd0_get_len() \
1.4718 + ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
1.4719 +#define __lcd_cmd1_get_len() \
1.4720 + ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
1.4721 +
1.4722 +
1.4723 +
1.4724 +/***************************************************************************
1.4725 + * DES
1.4726 + ***************************************************************************/
1.4727 +
1.4728 +
1.4729 +/***************************************************************************
1.4730 + * CPM
1.4731 + ***************************************************************************/
1.4732 +#define __cpm_plcr1_fd() \
1.4733 + ((REG_CPM_PLCR1 & CPM_PLCR1_PLL1FD_MASK) >> CPM_PLCR1_PLL1FD_BIT)
1.4734 +#define __cpm_plcr1_rd() \
1.4735 + ((REG_CPM_PLCR1 & CPM_PLCR1_PLL1RD_MASK) >> CPM_PLCR1_PLL1RD_BIT)
1.4736 +#define __cpm_plcr1_od() \
1.4737 + ((REG_CPM_PLCR1 & CPM_PLCR1_PLL1OD_MASK) >> CPM_PLCR1_PLL1OD_BIT)
1.4738 +#define __cpm_cfcr_mfr() \
1.4739 + ((REG_CPM_CFCR & CPM_CFCR_MFR_MASK) >> CPM_CFCR_MFR_BIT)
1.4740 +#define __cpm_cfcr_pfr() \
1.4741 + ((REG_CPM_CFCR & CPM_CFCR_PFR_MASK) >> CPM_CFCR_PFR_BIT)
1.4742 +#define __cpm_cfcr_sfr() \
1.4743 + ((REG_CPM_CFCR & CPM_CFCR_SFR_MASK) >> CPM_CFCR_SFR_BIT)
1.4744 +#define __cpm_cfcr_ifr() \
1.4745 + ((REG_CPM_CFCR & CPM_CFCR_IFR_MASK) >> CPM_CFCR_IFR_BIT)
1.4746 +
1.4747 +static __inline__ unsigned int __cpm_divisor_encode(unsigned int n)
1.4748 +{
1.4749 + unsigned int encode[10] = {1,2,3,4,6,8,12,16,24,32};
1.4750 + int i;
1.4751 + for (i=0;i<10;i++)
1.4752 + if (n < encode[i])
1.4753 + break;
1.4754 + return i;
1.4755 +}
1.4756 +
1.4757 +#define __cpm_set_mclk_div(n) \
1.4758 +do { \
1.4759 + REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_MFR_MASK) | \
1.4760 + ((n) << (CPM_CFCR_MFR_BIT)); \
1.4761 +} while (0)
1.4762 +
1.4763 +#define __cpm_set_pclk_div(n) \
1.4764 +do { \
1.4765 + REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_PFR_MASK) | \
1.4766 + ((n) << (CPM_CFCR_PFR_BIT)); \
1.4767 +} while (0)
1.4768 +
1.4769 +#define __cpm_set_sclk_div(n) \
1.4770 +do { \
1.4771 + REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_SFR_MASK) | \
1.4772 + ((n) << (CPM_CFCR_SFR_BIT)); \
1.4773 +} while (0)
1.4774 +
1.4775 +#define __cpm_set_iclk_div(n) \
1.4776 +do { \
1.4777 + REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_IFR_MASK) | \
1.4778 + ((n) << (CPM_CFCR_IFR_BIT)); \
1.4779 +} while (0)
1.4780 +
1.4781 +#define __cpm_set_lcdclk_div(n) \
1.4782 +do { \
1.4783 + REG_CPM_CFCR = (REG_CPM_CFCR & ~CPM_CFCR_LFR_MASK) | \
1.4784 + ((n) << (CPM_CFCR_LFR_BIT)); \
1.4785 +} while (0)
1.4786 +
1.4787 +#define __cpm_enable_cko1() (REG_CPM_CFCR |= CPM_CFCR_CKOEN1)
1.4788 +#define __cpm_enable_cko2() (REG_CPM_CFCR |= CPM_CFCR_CKOEN2)
1.4789 +#define __cpm_disable_cko1() (REG_CPM_CFCR &= ~CPM_CFCR_CKOEN1)
1.4790 +#define __cpm_disable_cko2() (REG_CPM_CFCR &= ~CPM_CFCR_CKOEN2)
1.4791 +
1.4792 +#define __cpm_idle_mode() \
1.4793 + (REG_CPM_LPCR = (REG_CPM_LPCR & ~CPM_LPCR_LPM_MASK) | \
1.4794 + CPM_LPCR_LPM_IDLE)
1.4795 +#define __cpm_sleep_mode() \
1.4796 + (REG_CPM_LPCR = (REG_CPM_LPCR & ~CPM_LPCR_LPM_MASK) | \
1.4797 + CPM_LPCR_LPM_SLEEP)
1.4798 +#define __cpm_hibernate_mode() \
1.4799 + (REG_CPM_LPCR = (REG_CPM_LPCR & ~CPM_LPCR_LPM_MASK) | \
1.4800 + CPM_LPCR_LPM_HIBERNATE)
1.4801 +
1.4802 +#define __cpm_start_uart0() \
1.4803 + (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UART0))
1.4804 +#define __cpm_start_uart1() \
1.4805 + (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UART1))
1.4806 +#define __cpm_start_uart2() \
1.4807 + (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UART2))
1.4808 +#define __cpm_start_uart3() \
1.4809 + (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UART3))
1.4810 +#define __cpm_start_ost() \
1.4811 + (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_OST))
1.4812 +#define __cpm_start_dmac() \
1.4813 + (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_DMAC))
1.4814 +#define __cpm_start_uhc() \
1.4815 + (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UHC))
1.4816 +#define __cpm_start_lcd() \
1.4817 + (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_LCD))
1.4818 +#define __cpm_start_i2c() \
1.4819 + (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_I2C))
1.4820 +#define __cpm_start_aic_pclk() \
1.4821 + (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_AICPCLK))
1.4822 +#define __cpm_start_aic_bitclk() \
1.4823 + (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_AICBCLK))
1.4824 +#define __cpm_start_pwm0() \
1.4825 + (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_PWM0))
1.4826 +#define __cpm_start_pwm1() \
1.4827 + (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_PWM1))
1.4828 +#define __cpm_start_ssi() \
1.4829 + (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_SSI))
1.4830 +#define __cpm_start_msc() \
1.4831 + (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_MSC))
1.4832 +#define __cpm_start_scc() \
1.4833 + (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_SCC))
1.4834 +#define __cpm_start_eth() \
1.4835 + (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_ETH))
1.4836 +#define __cpm_start_kbc() \
1.4837 + (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_KBC))
1.4838 +#define __cpm_start_cim() \
1.4839 + (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_CIM))
1.4840 +#define __cpm_start_udc() \
1.4841 + (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UDC))
1.4842 +#define __cpm_start_uprt() \
1.4843 + (REG_CPM_MSCR &= ~(1 << CPM_MSCR_MSTP_UPRT))
1.4844 +#define __cpm_start_all() (REG_CPM_MSCR = 0)
1.4845 +
1.4846 +#define __cpm_stop_uart0() \
1.4847 + (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UART0))
1.4848 +#define __cpm_stop_uart1() \
1.4849 + (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UART1))
1.4850 +#define __cpm_stop_uart2() \
1.4851 + (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UART2))
1.4852 +#define __cpm_stop_uart3() \
1.4853 + (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UART3))
1.4854 +#define __cpm_stop_ost() \
1.4855 + (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_OST))
1.4856 +#define __cpm_stop_dmac() \
1.4857 + (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_DMAC))
1.4858 +#define __cpm_stop_uhc() \
1.4859 + (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UHC))
1.4860 +#define __cpm_stop_lcd() \
1.4861 + (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_LCD))
1.4862 +#define __cpm_stop_i2c() \
1.4863 + (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_I2C))
1.4864 +#define __cpm_stop_aic_pclk() \
1.4865 + (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_AICPCLK))
1.4866 +#define __cpm_stop_aic_bitclk() \
1.4867 + (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_AICBCLK))
1.4868 +#define __cpm_stop_pwm0() \
1.4869 + (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_PWM0))
1.4870 +#define __cpm_stop_pwm1() \
1.4871 + (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_PWM1))
1.4872 +#define __cpm_stop_ssi() \
1.4873 + (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_SSI))
1.4874 +#define __cpm_stop_msc() \
1.4875 + (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_MSC))
1.4876 +#define __cpm_stop_scc() \
1.4877 + (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_SCC))
1.4878 +#define __cpm_stop_eth() \
1.4879 + (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_ETH))
1.4880 +#define __cpm_stop_kbc() \
1.4881 + (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_KBC))
1.4882 +#define __cpm_stop_cim() \
1.4883 + (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_CIM))
1.4884 +#define __cpm_stop_udc() \
1.4885 + (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UDC))
1.4886 +#define __cpm_stop_uprt() \
1.4887 + (REG_CPM_MSCR |= (1 << CPM_MSCR_MSTP_UPRT))
1.4888 +#define __cpm_stop_all() (REG_CPM_MSCR = 0xffffffff)
1.4889 +
1.4890 +#define __cpm_set_pin(n) \
1.4891 +do { \
1.4892 + unsigned int p, o; \
1.4893 + p = (n) / 32; \
1.4894 + o = (n) % 32; \
1.4895 + if (p == 0) \
1.4896 + REG_CPM_GSR0 |= (1 << o); \
1.4897 + else if (p == 1) \
1.4898 + REG_CPM_GSR1 |= (1 << o); \
1.4899 + else if (p == 2) \
1.4900 + REG_CPM_GSR2 |= (1 << o); \
1.4901 + else if (p == 3) \
1.4902 + REG_CPM_GSR3 |= (1 << o); \
1.4903 +} while (0)
1.4904 +
1.4905 +#define __cpm_clear_pin(n) \
1.4906 +do { \
1.4907 + unsigned int p, o; \
1.4908 + p = (n) / 32; \
1.4909 + o = (n) % 32; \
1.4910 + if (p == 0) \
1.4911 + REG_CPM_GSR0 &= ~(1 << o); \
1.4912 + else if (p == 1) \
1.4913 + REG_CPM_GSR1 &= ~(1 << o); \
1.4914 + else if (p == 2) \
1.4915 + REG_CPM_GSR2 &= ~(1 << o); \
1.4916 + else if (p == 3) \
1.4917 + REG_CPM_GSR3 &= ~(1 << o); \
1.4918 +} while (0)
1.4919 +
1.4920 +
1.4921 +#define __cpm_select_msc_clk(type) \
1.4922 +do { \
1.4923 + if (type == 0) \
1.4924 + REG_CPM_CFCR &= ~CPM_CFCR_MSC; \
1.4925 + else \
1.4926 + REG_CPM_CFCR |= CPM_CFCR_MSC; \
1.4927 + REG_CPM_CFCR |= CPM_CFCR_UPE; \
1.4928 +} while(0)
1.4929 +
1.4930 +
1.4931 +/***************************************************************************
1.4932 + * SSI
1.4933 + ***************************************************************************/
1.4934 +
1.4935 +#define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE )
1.4936 +#define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE )
1.4937 +#define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL )
1.4938 +
1.4939 +#define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK )
1.4940 +
1.4941 +#define __ssi_select_ce2() \
1.4942 +do { \
1.4943 + REG_SSI_CR0 |= SSI_CR0_FSEL; \
1.4944 + REG_SSI_CR1 &= ~SSI_CR1_MULTS; \
1.4945 +} while (0)
1.4946 +
1.4947 +#define __ssi_select_gpc() \
1.4948 +do { \
1.4949 + REG_SSI_CR0 &= ~SSI_CR0_FSEL; \
1.4950 + REG_SSI_CR1 |= SSI_CR1_MULTS; \
1.4951 +} while (0)
1.4952 +
1.4953 +#define __ssi_enable_tx_intr() \
1.4954 + ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE )
1.4955 +
1.4956 +#define __ssi_disable_tx_intr() \
1.4957 + ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) )
1.4958 +
1.4959 +#define __ssi_enable_rx_intr() \
1.4960 + ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE )
1.4961 +
1.4962 +#define __ssi_disable_rx_intr() \
1.4963 + ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) )
1.4964 +
1.4965 +#define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP )
1.4966 +#define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP )
1.4967 +
1.4968 +#define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV )
1.4969 +#define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV )
1.4970 +
1.4971 +#define __ssi_finish_receive() \
1.4972 + ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) )
1.4973 +
1.4974 +#define __ssi_disable_recvfinish() \
1.4975 + ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) )
1.4976 +
1.4977 +#define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH )
1.4978 +#define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH )
1.4979 +
1.4980 +#define __ssi_flush_fifo() \
1.4981 + ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH )
1.4982 +
1.4983 +#define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN )
1.4984 +
1.4985 +/* Motorola's SPI format, set 1 delay */
1.4986 +#define __ssi_spi_format() \
1.4987 +do { \
1.4988 + REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \
1.4989 + REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \
1.4990 + REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\
1.4991 + REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \
1.4992 +} while (0)
1.4993 +
1.4994 +/* TI's SSP format, must clear SSI_CR1.UNFIN */
1.4995 +#define __ssi_ssp_format() \
1.4996 +do { \
1.4997 + REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \
1.4998 + REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \
1.4999 +} while (0)
1.5000 +
1.5001 +/* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */
1.5002 +#define __ssi_microwire_format() \
1.5003 +do { \
1.5004 + REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \
1.5005 + REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \
1.5006 + REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\
1.5007 + REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \
1.5008 + REG_SSI_CR0 &= ~SSI_CR0_RFINE; \
1.5009 +} while (0)
1.5010 +
1.5011 +/* CE# level (FRMHL), CE# in interval time (ITFRM),
1.5012 + clock phase and polarity (PHA POL),
1.5013 + interval time (SSIITR), interval characters/frame (SSIICR) */
1.5014 +
1.5015 + /* frmhl,endian,mcom,flen,pha,pol MASK */
1.5016 +#define SSICR1_MISC_MASK \
1.5017 + ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \
1.5018 + | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \
1.5019 +
1.5020 +#define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \
1.5021 +do { \
1.5022 + REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \
1.5023 + REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \
1.5024 + (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \
1.5025 + ((pha) << 1) | (pol); \
1.5026 +} while(0)
1.5027 +
1.5028 +/* Transfer with MSB or LSB first */
1.5029 +#define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST )
1.5030 +#define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST )
1.5031 +
1.5032 +/* n = 2 - 17 */
1.5033 +#define __ssi_set_frame_length(n) \
1.5034 + ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | SSI_CR1_FLEN_##n##BIT) )
1.5035 +
1.5036 +/* n = 1 - 16 */
1.5037 +#define __ssi_set_microwire_command_length(n) \
1.5038 + ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) )
1.5039 +
1.5040 +/* Set the clock phase for SPI */
1.5041 +#define __ssi_set_spi_clock_phase(n) \
1.5042 + ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) )
1.5043 +
1.5044 +/* Set the clock polarity for SPI */
1.5045 +#define __ssi_set_spi_clock_polarity(n) \
1.5046 + ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) )
1.5047 +
1.5048 +/* n = 1,4,8,14 */
1.5049 +#define __ssi_set_tx_trigger(n) \
1.5050 +do { \
1.5051 + REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \
1.5052 + REG_SSI_CR1 |= SSI_CR1_TTRG_##n; \
1.5053 +} while (0)
1.5054 +
1.5055 +/* n = 1,4,8,14 */
1.5056 +#define __ssi_set_rx_trigger(n) \
1.5057 +do { \
1.5058 + REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \
1.5059 + REG_SSI_CR1 |= SSI_CR1_RTRG_##n; \
1.5060 +} while (0)
1.5061 +
1.5062 +#define __ssi_get_txfifo_count() \
1.5063 + ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT )
1.5064 +
1.5065 +#define __ssi_get_rxfifo_count() \
1.5066 + ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT )
1.5067 +
1.5068 +#define __ssi_clear_errors() \
1.5069 + ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) )
1.5070 +
1.5071 +#define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END )
1.5072 +#define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY )
1.5073 +
1.5074 +#define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF )
1.5075 +#define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE )
1.5076 +#define __ssi_rxfifo_noempty() ( REG_SSI_SR & SSI_SR_RFHF )
1.5077 +
1.5078 +#define __ssi_set_clk(dev_clk, ssi_clk) \
1.5079 + ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 )
1.5080 +
1.5081 +#define __ssi_receive_data() REG_SSI_DR
1.5082 +#define __ssi_transmit_data(v) ( REG_SSI_DR = (v) )
1.5083 +
1.5084 +/***************************************************************************
1.5085 + * WDT
1.5086 + ***************************************************************************/
1.5087 +
1.5088 +#define __wdt_set_count(count) ( REG_WDT_WTCNT = (count) )
1.5089 +#define __wdt_start() ( REG_WDT_WTCSR |= WDT_WTCSR_START )
1.5090 +#define __wdt_stop() ( REG_WDT_WTCSR &= ~WDT_WTCSR_START )
1.5091 +
1.5092 +
1.5093 +/***************************************************************************
1.5094 + ***************************************************************************/
1.5095 +
1.5096 +/*
1.5097 + * CPU clocks
1.5098 + */
1.5099 +#define JZ_EXTAL CONFIG_SYS_EXTAL
1.5100 +#define JZ_EXTAL2 32768 /* RTC clock */
1.5101 +
1.5102 +static __inline__ unsigned int __cpm_get_pllout(void)
1.5103 +{
1.5104 + unsigned int nf, nr, no, pllout;
1.5105 + unsigned long plcr = REG_CPM_PLCR1;
1.5106 + unsigned long od[4] = {1, 2, 2, 4};
1.5107 + if (plcr & CPM_PLCR1_PLL1EN) {
1.5108 + nf = (plcr & CPM_PLCR1_PLL1FD_MASK) >> CPM_PLCR1_PLL1FD_BIT;
1.5109 + nr = (plcr & CPM_PLCR1_PLL1RD_MASK) >> CPM_PLCR1_PLL1RD_BIT;
1.5110 + no = od[((plcr & CPM_PLCR1_PLL1OD_MASK) >> CPM_PLCR1_PLL1OD_BIT)];
1.5111 + pllout = (JZ_EXTAL) / ((nr+2) * no) * (nf+2);
1.5112 + } else
1.5113 + pllout = JZ_EXTAL;
1.5114 + return pllout;
1.5115 +}
1.5116 +
1.5117 +static __inline__ unsigned int __cpm_get_iclk(void)
1.5118 +{
1.5119 + unsigned int iclk;
1.5120 + int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.5121 + unsigned long cfcr = REG_CPM_CFCR;
1.5122 + unsigned long plcr = REG_CPM_PLCR1;
1.5123 + if (plcr & CPM_PLCR1_PLL1EN)
1.5124 + iclk = __cpm_get_pllout() /
1.5125 + div[(cfcr & CPM_CFCR_IFR_MASK) >> CPM_CFCR_IFR_BIT];
1.5126 + else
1.5127 + iclk = JZ_EXTAL;
1.5128 + return iclk;
1.5129 +}
1.5130 +
1.5131 +static __inline__ unsigned int __cpm_get_sclk(void)
1.5132 +{
1.5133 + unsigned int sclk;
1.5134 + int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.5135 + unsigned long cfcr = REG_CPM_CFCR;
1.5136 + unsigned long plcr = REG_CPM_PLCR1;
1.5137 + if (plcr & CPM_PLCR1_PLL1EN)
1.5138 + sclk = __cpm_get_pllout() /
1.5139 + div[(cfcr & CPM_CFCR_SFR_MASK) >> CPM_CFCR_SFR_BIT];
1.5140 + else
1.5141 + sclk = JZ_EXTAL;
1.5142 + return sclk;
1.5143 +}
1.5144 +
1.5145 +static __inline__ unsigned int __cpm_get_mclk(void)
1.5146 +{
1.5147 + unsigned int mclk;
1.5148 + int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.5149 + unsigned long cfcr = REG_CPM_CFCR;
1.5150 + unsigned long plcr = REG_CPM_PLCR1;
1.5151 + if (plcr & CPM_PLCR1_PLL1EN)
1.5152 + mclk = __cpm_get_pllout() /
1.5153 + div[(cfcr & CPM_CFCR_MFR_MASK) >> CPM_CFCR_MFR_BIT];
1.5154 + else
1.5155 + mclk = JZ_EXTAL;
1.5156 + return mclk;
1.5157 +}
1.5158 +
1.5159 +static __inline__ unsigned int __cpm_get_pclk(void)
1.5160 +{
1.5161 + unsigned int devclk;
1.5162 + int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.5163 + unsigned long cfcr = REG_CPM_CFCR;
1.5164 + unsigned long plcr = REG_CPM_PLCR1;
1.5165 + if (plcr & CPM_PLCR1_PLL1EN)
1.5166 + devclk = __cpm_get_pllout() /
1.5167 + div[(cfcr & CPM_CFCR_PFR_MASK) >> CPM_CFCR_PFR_BIT];
1.5168 + else
1.5169 + devclk = JZ_EXTAL;
1.5170 + return devclk;
1.5171 +}
1.5172 +
1.5173 +static __inline__ unsigned int __cpm_get_devclk(void)
1.5174 +{
1.5175 + unsigned int devclk;
1.5176 + int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1.5177 + unsigned long cfcr = REG_CPM_CFCR;
1.5178 + unsigned long plcr = REG_CPM_PLCR1;
1.5179 + if (plcr & CPM_PLCR1_PLL1EN)
1.5180 + devclk = __cpm_get_pllout() /
1.5181 + div[(cfcr & CPM_CFCR_PFR_MASK) >> CPM_CFCR_PFR_BIT];
1.5182 + else
1.5183 + devclk = JZ_EXTAL;
1.5184 + return devclk;
1.5185 +}
1.5186 +
1.5187 +#endif /* !__ASSEMBLY__ */
1.5188 +
1.5189 +#endif /* __JZ4730_H__ */