paul@22 | 1 | Timing
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paul@22 | 2 | ------
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paul@22 | 3 |
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paul@22 | 4 | According to the above (15.3.2 in the AUG), there are 312 scanlines, 256 of
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paul@22 | 5 | which are used to generate pixel data. At 50Hz, this means that 128 cycles are
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paul@37 | 6 | used to produce pixel data (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
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paul@37 | 7 | 312 ~= 128 cycles). This is consistent with the observation that each scanline
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paul@37 | 8 | requires at most 80 bytes of data, and that the ULA is apparently busy for 40
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paul@37 | 9 | out of 64 microseconds in each scanline.
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paul@22 | 10 |
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paul@31 | 11 | See: Acorn Electron Advanced User Guide
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paul@22 | 12 | See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
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paul@22 | 13 |
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paul@33 | 14 | Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
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paul@33 | 15 | each providing two bits of each byte) using two cycles within the 500ns period
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paul@36 | 16 | of the 2MHz clock to complete each access operation. Since the CPU and ULA
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paul@36 | 17 | have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
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paul@36 | 18 | effectively run at 1MHz (since every other 500ns period involves the ULA
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paul@36 | 19 | accessing RAM). The CPU is driven by an external clock (IC8) whose 16MHz
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paul@36 | 20 | frequency is divided by the ULA (IC1) depending on the screen mode in use.
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paul@33 | 21 |
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paul@33 | 22 | See: Acorn Electron Service Manual
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paul@37 | 23 | http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
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paul@37 | 24 |
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paul@37 | 25 | Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
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paul@37 | 26 | patterns corresponding to 16MHz cycles are required:
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paul@37 | 27 |
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paul@37 | 28 | Time (ns): 0-------------- 500------------
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paul@37 | 29 | 2 MHz cycle: 0 1 ...
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paul@37 | 30 | 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
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paul@37 | 31 | ~RAS: 0 1 0 1 ...
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paul@37 | 32 | ~CAS: 0 1 0 1 0 1 0 1 ...
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paul@38 | 33 | A B B A B B
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paul@38 | 34 | F S F S
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paul@37 | 35 |
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paul@37 | 36 | Here, "A" indicates the row and column addresses being latched into the RAM
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paul@38 | 37 | (on a negative edge for ~RAS and ~CAS respectively), and "B" indicates the
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paul@37 | 38 | second column address being latched into the RAM. Presumably, the first and
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paul@37 | 39 | second half-bytes can be read at "F" and "S" respectively.
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paul@37 | 40 |
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paul@38 | 41 | Note that the Service Manual refers to the negative edge of RAS and CAS, but
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paul@38 | 42 | the datasheet for the similar TM4164EC4 product shows latching on the negative
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paul@38 | 43 | edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
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paul@38 | 44 | communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
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paul@38 | 45 | "page mode" provides the appropriate behaviour for that particular product.
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paul@38 | 46 |
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paul@37 | 47 | Shadow/Expanded Memory
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paul@37 | 48 | ----------------------
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paul@37 | 49 |
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paul@37 | 50 | The Electron exposes all sixteen address lines and all eight data lines
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paul@37 | 51 | through the expansion bus. Using such lines, it is possible to provide
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paul@37 | 52 | additional memory - typically sideways ROM and RAM - on expansion cards and
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paul@37 | 53 | through cartridges, although the official cartridge specification provides
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paul@37 | 54 | fewer address lines and only seeks to provide access to memory in 16K units.
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paul@37 | 55 |
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paul@37 | 56 | Various modifications and upgrades were developed to offer "turbo"
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paul@37 | 57 | capabilities to the Electron, permitting the CPU to access a separate 8K of
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paul@37 | 58 | RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
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paul@37 | 59 | the ULA through additional logic. However, an enhanced ULA might support
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paul@37 | 60 | independent CPU access to memory over the expansion bus by allowing itself to
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paul@37 | 61 | be discharged from providing access to memory, potentially for a range of
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paul@37 | 62 | addresses, and for the CPU to communicate with external memory uninterrupted.
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paul@33 | 63 |
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paul@0 | 64 | Hardware Scrolling
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paul@0 | 65 | ------------------
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paul@0 | 66 |
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paul@0 | 67 | On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
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paul@0 | 68 | the least significant 5 bits being zero, thus limiting the scrolling
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paul@0 | 69 | resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
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paul@0 | 70 | using the same layout of these addresses.
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paul@0 | 71 |
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paul@0 | 72 | |--&FE02--------------| |--&FE03--------------|
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paul@0 | 73 | XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
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paul@0 | 74 |
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paul@0 | 75 | XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
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paul@0 | 76 |
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paul@4 | 77 | Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
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paul@4 | 78 | memory to pixel locations is character oriented. A change in 8 bytes would
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paul@4 | 79 | permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
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paul@4 | 80 | MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
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paul@4 | 81 | observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
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paul@4 | 82 | Guide).
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paul@4 | 83 |
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paul@4 | 84 | One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
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paul@4 | 85 | of changing the screen address by 2 bytes is the change in the number of lines
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paul@4 | 86 | from the initial and final character rows that need reading by the ULA, which
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paul@9 | 87 | would need to maintain this state information (although this is a relatively
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paul@9 | 88 | trivial change). Another pitfall is the complication that might be introduced
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paul@9 | 89 | to software writing bitmaps of character height to the screen.
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paul@4 | 90 |
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paul@4 | 91 | Region Blanking
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paul@4 | 92 | ---------------
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paul@4 | 93 |
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paul@4 | 94 | The problem of permitting character-oriented blitting in programs whilst
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paul@4 | 95 | scrolling the screen by sub-character amounts could be mitigated by permitting
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paul@4 | 96 | a region of the display to be blank, such as the final lines of the display.
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paul@4 | 97 | Consider the following vertical scrolling by 2 bytes that would cause an
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paul@4 | 98 | initial character row of 6 lines and a final character row of 2 lines:
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paul@4 | 99 |
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paul@4 | 100 | 6 lines - initial, partial character row
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paul@4 | 101 | 248 lines - 31 complete rows
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paul@4 | 102 | 2 lines - final, partial character row
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paul@4 | 103 |
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paul@4 | 104 | If a routine were in use that wrote 8 line bitmaps to the partial character
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paul@4 | 105 | row now split in two, it would be advisable to hide one of the regions in
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paul@4 | 106 | order to prevent content appearing in the wrong place on screen (such as
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paul@4 | 107 | content meant to appear at the top "leaking" onto the bottom). Blanking 6
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paul@4 | 108 | lines would be sufficient, as can be seen from the following cases.
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paul@4 | 109 |
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paul@4 | 110 | Scrolling up by 2 lines:
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paul@4 | 111 |
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paul@4 | 112 | 6 lines - initial, partial character row
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paul@4 | 113 | 240 lines - 30 complete rows
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paul@4 | 114 | 4 lines - part of 1 complete row
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paul@4 | 115 | -----------------------------------------------------------------
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paul@4 | 116 | 4 lines - part of 1 complete row (hidden to maintain 250 lines)
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paul@4 | 117 | 2 lines - final, partial character row (hidden)
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paul@4 | 118 |
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paul@4 | 119 | Scrolling down by 2 lines:
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paul@4 | 120 |
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paul@4 | 121 | 2 lines - initial, partial character row
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paul@4 | 122 | 248 lines - 31 complete rows
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paul@4 | 123 | ----------------------------------------------------------
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paul@4 | 124 | 6 lines - final, partial character row (hidden)
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paul@4 | 125 |
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paul@24 | 126 | Thus, in this case, region blanking would impose a 250 line display with the
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paul@24 | 127 | bottom 6 lines blank.
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paul@24 | 128 |
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paul@24 | 129 | Screen Height Adjustment
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paul@24 | 130 | ------------------------
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paul@24 | 131 |
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paul@24 | 132 | The height of the screen could be configurable in order to reduce screen
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paul@24 | 133 | memory consumption. This is not quite done in MODE 3 and 6 since the start of
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paul@24 | 134 | the screen appears to be rounded down to the nearest page, but by reducing the
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paul@24 | 135 | height by amounts more than a page, savings would be possible. For example:
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paul@24 | 136 |
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paul@24 | 137 | Screen width Depth Height Bytes per line Saving in bytes Start address
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paul@24 | 138 | ------------ ----- ------ -------------- --------------- -------------
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paul@24 | 139 | 640 1 252 80 320 &3140 -> &3100
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paul@24 | 140 | 640 1 248 80 640 &3280 -> &3200
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paul@24 | 141 | 320 1 240 40 640 &5A80 -> &5A00
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paul@24 | 142 | 320 2 240 80 1280 &3500
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paul@0 | 143 |
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paul@0 | 144 | Palette Definition
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paul@0 | 145 | ------------------
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paul@0 | 146 |
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paul@0 | 147 | Since all memory accesses go via the ULA, an enhanced ULA could employ more
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paul@0 | 148 | specific addresses than &FE*X to perform enhanced functions. For example, the
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paul@0 | 149 | palette control is done using &FE*8-F and merely involves selecting predefined
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paul@0 | 150 | colours, whereas an enhanced ULA could support the redefinition of all 16
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paul@0 | 151 | colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
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paul@0 | 152 | (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
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paul@0 | 153 | specifications similar to those used on the Archimedes.
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paul@0 | 154 |
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paul@4 | 155 | The principal limitation here is actually the hardware: the Electron has only
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paul@4 | 156 | a single output line for each of the red, green and blue channels, and if
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paul@4 | 157 | those outputs are strictly digital and can only be set to a "high" and "low"
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paul@4 | 158 | value, then only the existing eight colours are possible. If a modern ULA were
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paul@4 | 159 | able to output analogue values, it would still need to be assessed whether the
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paul@4 | 160 | circuitry could successfully handle and propagate such values.
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paul@4 | 161 |
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paul@4 | 162 | Palette Definition Lists
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paul@4 | 163 | ------------------------
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paul@4 | 164 |
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paul@4 | 165 | It can be useful to redefine the palette in order to change the colours
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paul@4 | 166 | available for a particular region of the screen, particularly in modes where
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paul@4 | 167 | the choice of colours is constrained, and if an increased colour depth were
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paul@4 | 168 | available, palette redefinition would be useful to give the illusion of more
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paul@4 | 169 | than 16 colours in MODE 2. Traditionally, palette redefinition has been done
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paul@4 | 170 | by using interrupt-driven timers, but a more efficient approach would involve
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paul@4 | 171 | presenting lists of palette definitions to the ULA so that it can change the
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paul@4 | 172 | palette at a particular display line.
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paul@4 | 173 |
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paul@4 | 174 | One might define a palette redefinition list in a region of memory and then
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paul@4 | 175 | communicate its contents to the ULA by writing the address and length of the
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paul@4 | 176 | list, along with the display line at which the palette is to be changed, to
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paul@4 | 177 | ULA registers such that the ULA buffers the list and performs the redefinition
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paul@4 | 178 | at the appropriate time. Throughput/bandwidth considerations might impose
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paul@4 | 179 | restrictions on the practical length of such a list, however.
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paul@4 | 180 |
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paul@4 | 181 | Palette-Free Modes
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paul@4 | 182 | ------------------
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paul@4 | 183 |
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paul@4 | 184 | Palette-free modes might be defined where bit values directly correspond to
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paul@4 | 185 | the red, green and blue channels, although this would mostly make sense only
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paul@4 | 186 | for modes with depths greater than the standard 4 bits per pixel, and such
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paul@4 | 187 | modes would require more memory than MODE 2 if they were to have an acceptable
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paul@4 | 188 | resolution.
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paul@4 | 189 |
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paul@4 | 190 | Display Suspend
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paul@4 | 191 | ---------------
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paul@4 | 192 |
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paul@4 | 193 | Especially when writing to the screen memory, it could be beneficial to be
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paul@4 | 194 | able to suspend the ULA's access to the memory, instead producing blank values
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paul@4 | 195 | for all screen pixels until a program is ready to reveal the screen. This is
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paul@4 | 196 | different from palette blanking since with a blank palette, the ULA is still
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paul@4 | 197 | reading screen memory and translating its contents into pixel values that end
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paul@4 | 198 | up being blank.
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paul@4 | 199 |
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paul@4 | 200 | This function is reminiscent of a capability of the ZX81, albeit necessary on
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paul@4 | 201 | that hardware to reduce the load on the system CPU which was responsible for
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paul@4 | 202 | producing the video output.
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paul@4 | 203 |
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paul@35 | 204 | Hardware Sprites
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paul@35 | 205 | ----------------
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paul@0 | 206 |
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paul@0 | 207 | An enhanced ULA might provide hardware sprites, but this would be done in an
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paul@0 | 208 | way that is incompatible with the standard ULA, since no &FE*X locations are
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paul@34 | 209 | available for allocation. To keep the facility simple, hardware sprites would
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paul@34 | 210 | have a standard byte width and height.
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paul@34 | 211 |
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paul@34 | 212 | The specification of sprites could involve the reservation of 16 locations
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paul@34 | 213 | (for example, &FE20-F) specifying a fixed number of eight sprites, with each
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paul@34 | 214 | location pair referring to the sprite data. By limiting the ULA to dealing
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paul@34 | 215 | with a fixed number of sprites, the work required inside the ULA would be
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paul@35 | 216 | reduced since it would avoid having to deal with arbitrary numbers of sprites.
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paul@0 | 217 |
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paul@35 | 218 | The principal limitation on providing hardware sprites is that of having to
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paul@35 | 219 | obtain sprite data, given that the ULA is usually required to retrieve screen
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paul@35 | 220 | data, and given the lack of memory bandwidth available to retrieve sprite data
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paul@35 | 221 | (particularly from multiple sprites supposedly at the same position) and
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paul@35 | 222 | screen data simultaneously. Although the ULA could potentially read sprite
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paul@35 | 223 | data and screen data in alternate memory accesses in screen modes where the
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paul@35 | 224 | bandwidth is not already fully utilised, this would result in a degradation of
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paul@35 | 225 | performance.
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paul@34 | 226 |
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paul@24 | 227 | Additional Screen Mode Configurations
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paul@24 | 228 | -------------------------------------
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paul@24 | 229 |
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paul@24 | 230 | Alternative screen mode configurations could be supported. The ULA has to
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paul@24 | 231 | produce 640 pixel values across the screen, with pixel doubling or quadrupling
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paul@24 | 232 | employed to fill the screen width:
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paul@24 | 233 |
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paul@24 | 234 | Screen width Columns Scaling Depth Bytes
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paul@24 | 235 | ------------ ------- ------- ----- -----
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paul@24 | 236 | 640 80 x1 1 80
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paul@24 | 237 | 320 40 x2 1, 2 40, 80
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paul@24 | 238 | 160 20 x4 2, 4 40, 80
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paul@24 | 239 |
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paul@24 | 240 | It must also use at most 80 byte-sized memory accesses to provide the
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paul@24 | 241 | information for the display. Given that characters must occupy an 8x8 pixel
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paul@24 | 242 | array, if a configuration featuring anything other than 20, 40 or 80 character
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paul@24 | 243 | columns is to be supported, compromises must be made such as the introduction
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paul@24 | 244 | of blank pixels either between characters (such as occurs between rows in MODE
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paul@24 | 245 | 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
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paul@24 | 246 | in MODE 3 and 6). Consider the following configuration:
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paul@24 | 247 |
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paul@24 | 248 | Screen width Columns Scaling Depth Bytes Blank
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paul@24 | 249 | ------------ ------- ------- ----- ------ -----
|
paul@24 | 250 | 208 26 x3 1, 2 26, 52 16
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paul@24 | 251 |
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paul@24 | 252 | Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
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paul@24 | 253 | colours could be provided, with 16 blank pixel values (out of a total of 640)
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paul@24 | 254 | generated either at the start or end (or split between the start and end) of
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paul@24 | 255 | each scanline.
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paul@24 | 256 |
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paul@24 | 257 | Character Attributes
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paul@24 | 258 | --------------------
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paul@24 | 259 |
|
paul@24 | 260 | The BBC Micro MODE 7 employs something resembling character attributes to
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paul@24 | 261 | support teletext displays, but depends on circuitry providing a character
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paul@24 | 262 | generator. The ZX Spectrum, on the other hand, provides character attributes
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paul@24 | 263 | as a means of colouring bitmapped graphics. Although such a feature is very
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paul@24 | 264 | limiting as the sole means of providing multicolour graphics, in situations
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paul@24 | 265 | where the choice is between low resolution multicolour graphics or high
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paul@24 | 266 | resolution monochrome graphics, character attributes provide a potentially
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paul@24 | 267 | useful compromise.
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paul@24 | 268 |
|
paul@24 | 269 | For each byte read, the ULA must deliver 8 pixel values (out of a total of
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paul@24 | 270 | 640) to the video output, doing so by either emptying its pixel buffer on a
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paul@24 | 271 | pixel per cycle basis, or by multiplying pixels and thus holding them for more
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paul@24 | 272 | than one cycle. For example for a screen mode having 640 pixels in width:
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paul@24 | 273 |
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paul@24 | 274 | Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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paul@24 | 275 | Reads: B B
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paul@24 | 276 | Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
|
paul@24 | 277 |
|
paul@24 | 278 | And for a screen mode having 320 pixels in width:
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paul@24 | 279 |
|
paul@24 | 280 | Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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paul@24 | 281 | Reads: B
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paul@24 | 282 | Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
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paul@24 | 283 |
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paul@24 | 284 | However, in modes where less than 80 bytes are required to generate the pixel
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paul@24 | 285 | values, an enhanced ULA might be able to read additional bytes between those
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paul@24 | 286 | providing the bitmapped graphics data:
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paul@24 | 287 |
|
paul@24 | 288 | Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
|
paul@24 | 289 | Reads: B A
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paul@24 | 290 | Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
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paul@24 | 291 |
|
paul@24 | 292 | These additional bytes could provide colour information for the bitmapped data
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paul@24 | 293 | in the following character column (of 8 pixels). Since it would be desirable
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paul@24 | 294 | to apply attribute data to the first column, the initial 8 cycles might be
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paul@24 | 295 | configured to not produce pixel values.
|
paul@24 | 296 |
|
paul@35 | 297 | For an entire character, attribute data need only be read for the first row of
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paul@35 | 298 | pixels for a character. The subsequent rows would have attribute information
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paul@35 | 299 | applied to them, although this would require the attribute data to be stored
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paul@35 | 300 | in some kind of buffer. Thus, the following access pattern would be observed:
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paul@35 | 301 |
|
paul@35 | 302 | Cycle: A B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ...
|
paul@35 | 303 |
|
paul@24 | 304 | A whole byte used for colour information for a whole character would result in
|
paul@35 | 305 | a choice of 256 colours, and this might be somewhat excessive. By only reading
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paul@35 | 306 | attribute bytes at every other opportunity, a choice of 16 colours could be
|
paul@35 | 307 | applied individually to two characters.
|
paul@24 | 308 |
|
paul@24 | 309 | Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
|
paul@24 | 310 | Reads: B A B -
|
paul@24 | 311 | Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
|
paul@24 | 312 |
|
paul@35 | 313 | Further reductions in attribute data access, offering 4 colours for every
|
paul@35 | 314 | character in a four character block, for example, might also be worth
|
paul@34 | 315 | considering.
|
paul@34 | 316 |
|
paul@24 | 317 | Consider the following configurations for screen modes with a colour depth of
|
paul@24 | 318 | 1 bit per pixel for bitmap information:
|
paul@24 | 319 |
|
paul@35 | 320 | Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
|
paul@35 | 321 | ------------ ------- ------- --------- --------- ------- ------------
|
paul@35 | 322 | 320 40 x2 40 40 256 &5300
|
paul@35 | 323 | 320 40 x2 40 20 16 &5580 -> &5500
|
paul@35 | 324 | 320 40 x2 40 10 4 &56C0 -> &5600
|
paul@35 | 325 | 208 26 x3 26 26 256 &62C0 -> &6200
|
paul@35 | 326 | 208 26 x3 26 13 16 &6460 -> &6400
|
paul@34 | 327 |
|
paul@34 | 328 | MODE 7 Emulation using Character Attributes
|
paul@34 | 329 | -------------------------------------------
|
paul@24 | 330 |
|
paul@24 | 331 | If the scheme of applying attributes to character regions were employed to
|
paul@24 | 332 | emulate MODE 7, in conjunction with the MODE 6 display technique, the
|
paul@24 | 333 | following configuration would be required:
|
paul@24 | 334 |
|
paul@24 | 335 | Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
|
paul@24 | 336 | ------------ ------- ---- --------- --------- ------- ------------
|
paul@35 | 337 | 320 40 25 40 20 16 &5ECC -> &5E00
|
paul@35 | 338 | 320 40 25 40 10 4 &5FC6 -> &5F00
|
paul@24 | 339 |
|
paul@35 | 340 | Although this requires much more memory than MODE 7 (8500 bytes versus MODE
|
paul@35 | 341 | 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
|
paul@35 | 342 | at least make a limited 40-column multicolour mode available as a substitute
|
paul@35 | 343 | for MODE 7.
|
paul@24 | 344 |
|
paul@24 | 345 | Enhanced Graphics and Mode Layouts
|
paul@24 | 346 | ----------------------------------
|
paul@0 | 347 |
|
paul@0 | 348 | Screen modes with different screen memory mappings, higher resolutions and
|
paul@0 | 349 | larger colour depths might be possible, but this would in most cases involve
|
paul@0 | 350 | the allocation of more screen memory, and the ULA would probably then be
|
paul@0 | 351 | obliged to page in such memory for the CPU to be able to sensibly access it
|
paul@0 | 352 | all. Merely changing the memory mappings in order to have Archimedes-style
|
paul@0 | 353 | row-oriented screen addresses (instead of character-oriented addresses) could
|
paul@0 | 354 | be done for the existing modes, but this might not be sufficiently beneficial,
|
paul@0 | 355 | especially since accessing regions of the screen would involve incrementing
|
paul@0 | 356 | pointers by amounts that are inconvenient on an 8-bit CPU.
|
paul@0 | 357 |
|
paul@0 | 358 | Enhanced Sound
|
paul@0 | 359 | --------------
|
paul@0 | 360 |
|
paul@0 | 361 | The standard ULA reserves &FE*6 for sound generation and cassette
|
paul@0 | 362 | input/output, thus making it impossible to support multiple channels within
|
paul@0 | 363 | the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
|
paul@0 | 364 | and an enhanced ULA could adopt this interface.
|
paul@0 | 365 |
|
paul@9 | 366 | The BBC Micro uses the SN76489 chip to produce sound, and the entire
|
paul@9 | 367 | functionality of this chip could be emulated for enhanced sound, with a subset
|
paul@9 | 368 | of the functionality exposed via the &FE*6 interface.
|
paul@9 | 369 |
|
paul@9 | 370 | See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
|
paul@9 | 371 |
|
paul@0 | 372 | Waveform Upload
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paul@0 | 373 | ---------------
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paul@0 | 374 |
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paul@0 | 375 | As with a hardware sprite function, waveforms could be uploaded or referenced
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paul@0 | 376 | using locations as registers referencing memory regions.
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paul@0 | 377 |
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paul@0 | 378 | BBC ULA Compatibility
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paul@0 | 379 | ---------------------
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paul@0 | 380 |
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paul@0 | 381 | Although some new ULA functions could be defined in a way that is also
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paul@0 | 382 | compatible with the BBC Micro, the BBC ULA is itself incompatible with the
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paul@0 | 383 | Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
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paul@0 | 384 | map, but controls various functions specific to the 6845 video controller;
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paul@0 | 385 | &FE08-F is reserved for the serial controller. It therefore becomes possible
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paul@0 | 386 | to disregard compatibility where compatibility is already disregarded for a
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paul@0 | 387 | particular area of functionality.
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paul@0 | 388 |
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paul@0 | 389 | &FE20-F maps to video ULA functionality on the BBC Micro which provides
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paul@0 | 390 | control over the palette (using address &FE21, compared to &FE07-F on the
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paul@0 | 391 | Electron) and other system-specific functions. Since the location usage is
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paul@0 | 392 | generally incompatible, this region could be reused for other purposes.
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paul@31 | 393 |
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paul@31 | 394 | ULA Pin Functions
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paul@31 | 395 | -----------------
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paul@31 | 396 |
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paul@31 | 397 | The functions of the ULA pins are described in the Electron Service Manual. Of
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paul@31 | 398 | interest to video processing are the following:
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paul@31 | 399 |
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paul@31 | 400 | CSYNC (low during horizontal or vertical synchronisation periods, high
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paul@31 | 401 | otherwise)
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paul@31 | 402 |
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paul@31 | 403 | HS (low during horizontal synchronisation periods, high otherwise)
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paul@31 | 404 |
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paul@31 | 405 | RED, GREEN, BLUE (pixel colour outputs)
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paul@31 | 406 |
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paul@31 | 407 | CLOCK IN (a 16MHz clock input, 4V peak to peak)
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paul@31 | 408 |
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paul@31 | 409 | PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
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paul@31 | 410 |
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paul@31 | 411 | More general memory access pins:
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paul@31 | 412 |
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paul@31 | 413 | RAM0...RAM3 (data lines to/from the RAM)
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paul@31 | 414 |
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paul@31 | 415 | RA0...RA7 (address lines for sending both row and column addresses to the RAM)
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paul@31 | 416 |
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paul@38 | 417 | RAS (row address strobe setting the row address on a negative edge - see the
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paul@38 | 418 | timing notes)
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paul@31 | 419 |
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paul@38 | 420 | CAS (column address strobe setting the column address on a negative edge -
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paul@38 | 421 | see the timing notes)
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paul@31 | 422 |
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paul@31 | 423 | WE (sets write enable with logic 0, read with logic 1)
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paul@31 | 424 |
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paul@31 | 425 | ROM (select data access from ROM)
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paul@31 | 426 |
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paul@31 | 427 | CPU-oriented memory access pins:
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paul@31 | 428 |
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paul@31 | 429 | A0...A15 (CPU address lines)
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paul@31 | 430 |
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paul@31 | 431 | PD0...PD7 (CPU data lines)
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paul@31 | 432 |
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paul@31 | 433 | R/W (indicates CPU write with logic 0, CPU read with logic 1)
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paul@31 | 434 |
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paul@31 | 435 | Interrupt-related pins:
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paul@31 | 436 |
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paul@31 | 437 | NMI (CPU request for uninterrupted 1MHz access to memory)
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paul@31 | 438 |
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paul@31 | 439 | IRQ (signal event to CPU)
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paul@31 | 440 |
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paul@31 | 441 | POR (power-on reset, resetting the ULA on a positive edge and asserting the
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paul@31 | 442 | CPU's RST pin)
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paul@31 | 443 |
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paul@31 | 444 | RST (master reset for the CPU signalled on power-up and by the Break key)
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paul@31 | 445 |
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paul@31 | 446 | Keyboard-related pins:
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paul@31 | 447 |
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paul@31 | 448 | KBD0...KBD3 (keyboard inputs)
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paul@31 | 449 |
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paul@31 | 450 | CAPS LOCK (control status LED)
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paul@31 | 451 |
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paul@31 | 452 | Sound-related pins:
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paul@31 | 453 |
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paul@31 | 454 | SOUND O/P (sound output using internal oscillator)
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paul@31 | 455 |
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paul@31 | 456 | Cassette-related pins:
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paul@31 | 457 |
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paul@31 | 458 | CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
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paul@31 | 459 |
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paul@31 | 460 | CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
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paul@31 | 461 |
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paul@31 | 462 | CAS RC (detect high tone)
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paul@31 | 463 |
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paul@31 | 464 | CAS MO (motor relay output)
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paul@31 | 465 |
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paul@31 | 466 | ÷13 IN (~1200 baud clock input)
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