paul@1 | 1 | #!/usr/bin/env python |
paul@1 | 2 | |
paul@1 | 3 | """ |
paul@1 | 4 | Acorn Electron ULA simulation. |
paul@1 | 5 | """ |
paul@1 | 6 | |
paul@29 | 7 | from array import array |
paul@29 | 8 | from itertools import repeat |
paul@29 | 9 | |
paul@22 | 10 | LINES_PER_ROW = 8 # the number of pixel lines per character row |
paul@22 | 11 | MAX_HEIGHT = 256 # the height of the screen in pixels |
paul@40 | 12 | MAX_WIDTH = 640 # the width of the screen in pixels |
paul@40 | 13 | |
paul@40 | 14 | MAX_CSYNC = 2 # the scanline during which vsync ends |
paul@40 | 15 | MIN_PIXELLINE = 38 # the first scanline involving pixel generation |
paul@22 | 16 | MAX_SCANLINE = 312 # the number of scanlines in each frame |
paul@40 | 17 | |
paul@40 | 18 | MAX_PIXELLINE = MIN_PIXELLINE + MAX_HEIGHT |
paul@40 | 19 | |
paul@40 | 20 | MAX_HSYNC = 75 # the number of cycles in each hsync period |
paul@42 | 21 | MIN_PIXELPOS = 256 # the first cycle involving pixel generation |
paul@40 | 22 | MAX_SCANPOS = 1024 # the number of cycles in each scanline |
paul@40 | 23 | |
paul@40 | 24 | MAX_PIXELPOS = MIN_PIXELPOS + MAX_WIDTH |
paul@40 | 25 | |
paul@22 | 26 | SCREEN_LIMIT = 0x8000 # the first address after the screen memory |
paul@22 | 27 | MAX_MEMORY = 0x10000 # the number of addressable memory locations |
paul@40 | 28 | MAX_RAM = 0x10000 # the number of addressable RAM locations (64Kb in each IC) |
paul@3 | 29 | BLANK = (0, 0, 0) |
paul@1 | 30 | |
paul@29 | 31 | def update(ula): |
paul@1 | 32 | |
paul@1 | 33 | """ |
paul@31 | 34 | Update the 'ula' for one frame. Return the resulting screen. |
paul@31 | 35 | """ |
paul@31 | 36 | |
paul@31 | 37 | video = ula.video |
paul@31 | 38 | |
paul@31 | 39 | i = 0 |
paul@31 | 40 | limit = MAX_SCANLINE * MAX_SCANPOS |
paul@31 | 41 | while i < limit: |
paul@31 | 42 | ula.update() |
paul@31 | 43 | video.update() |
paul@31 | 44 | i += 1 |
paul@40 | 45 | |
paul@31 | 46 | return video.screen |
paul@31 | 47 | |
paul@31 | 48 | class Video: |
paul@31 | 49 | |
paul@31 | 50 | """ |
paul@31 | 51 | A class representing the video circuitry. |
paul@1 | 52 | """ |
paul@1 | 53 | |
paul@31 | 54 | def __init__(self): |
paul@31 | 55 | self.screen = array("B", repeat(0, MAX_WIDTH * 3 * MAX_HEIGHT)) |
paul@31 | 56 | self.colour = BLANK |
paul@31 | 57 | self.csync = 1 |
paul@31 | 58 | self.hs = 1 |
paul@40 | 59 | self.x = 0 |
paul@40 | 60 | self.y = 0 |
paul@1 | 61 | |
paul@40 | 62 | def set_csync(self, value): |
paul@40 | 63 | if self.csync and not value: |
paul@40 | 64 | self.y = 0 |
paul@40 | 65 | self.pos = 0 |
paul@40 | 66 | self.csync = value |
paul@40 | 67 | |
paul@40 | 68 | def set_hs(self, value): |
paul@40 | 69 | if self.hs and not value: |
paul@40 | 70 | self.x = 0 |
paul@40 | 71 | self.y += 1 |
paul@40 | 72 | self.hs = value |
paul@31 | 73 | |
paul@31 | 74 | def update(self): |
paul@40 | 75 | if MIN_PIXELLINE <= self.y < MAX_PIXELLINE: |
paul@42 | 76 | if MIN_PIXELPOS + 8 <= self.x < MAX_PIXELPOS + 8: |
paul@31 | 77 | self.screen[self.pos] = self.colour[0]; self.pos += 1 |
paul@31 | 78 | self.screen[self.pos] = self.colour[1]; self.pos += 1 |
paul@31 | 79 | self.screen[self.pos] = self.colour[2]; self.pos += 1 |
paul@40 | 80 | self.x += 1 |
paul@40 | 81 | |
paul@40 | 82 | class RAM: |
paul@40 | 83 | |
paul@40 | 84 | """ |
paul@40 | 85 | A class representing the RAM circuits (IC4 to IC7). Each circuit |
paul@48 | 86 | traditionally holds 64 kilobits, with each access obtaining 1 bit from each |
paul@48 | 87 | IC, and thus two accesses being required to obtain a whole byte. Here, we |
paul@48 | 88 | model the circuits with a list of 65536 half-bytes with each bit in a |
paul@48 | 89 | half-byte representing a bit stored on a separate IC. |
paul@40 | 90 | """ |
paul@40 | 91 | |
paul@40 | 92 | def __init__(self): |
paul@40 | 93 | |
paul@40 | 94 | "Initialise the RAM circuits." |
paul@40 | 95 | |
paul@40 | 96 | self.memory = [0] * MAX_RAM |
paul@40 | 97 | self.row_address = 0 |
paul@40 | 98 | self.column_address = 0 |
paul@40 | 99 | self.data = 0 |
paul@40 | 100 | |
paul@40 | 101 | def row_select(self, address): |
paul@59 | 102 | |
paul@59 | 103 | "The operation of asserting a row 'address' via RA0...RA7." |
paul@59 | 104 | |
paul@40 | 105 | self.row_address = address |
paul@40 | 106 | |
paul@40 | 107 | def row_deselect(self): |
paul@40 | 108 | pass |
paul@40 | 109 | |
paul@40 | 110 | def column_select(self, address): |
paul@59 | 111 | |
paul@59 | 112 | "The operation of asserting a column 'address' via RA0...RA7." |
paul@59 | 113 | |
paul@40 | 114 | self.column_address = address |
paul@40 | 115 | |
paul@40 | 116 | # Read the data. |
paul@40 | 117 | |
paul@40 | 118 | self.data = self.memory[self.row_address << 8 | self.column_address] |
paul@40 | 119 | |
paul@40 | 120 | def column_deselect(self): |
paul@40 | 121 | pass |
paul@40 | 122 | |
paul@40 | 123 | # Convenience methods. |
paul@40 | 124 | |
paul@40 | 125 | def fill(self, start, end, value): |
paul@40 | 126 | for i in xrange(start, end): |
paul@40 | 127 | self.memory[i << 1] = value >> 4 |
paul@40 | 128 | self.memory[i << 1 | 0x1] = value & 0xf |
paul@29 | 129 | |
paul@2 | 130 | class ULA: |
paul@2 | 131 | |
paul@31 | 132 | """ |
paul@31 | 133 | A class providing the ULA functionality. Instances of this class refer to |
paul@31 | 134 | the system memory, maintain internal state (such as information about the |
paul@31 | 135 | current screen mode), and provide outputs (such as the current pixel |
paul@31 | 136 | colour). |
paul@31 | 137 | """ |
paul@1 | 138 | |
paul@2 | 139 | modes = [ |
paul@2 | 140 | (640, 1, 32), (320, 2, 32), (160, 4, 32), # (width, depth, rows) |
paul@3 | 141 | (640, 1, 25), (320, 1, 32), (160, 2, 32), |
paul@3 | 142 | (320, 1, 25) |
paul@2 | 143 | ] |
paul@2 | 144 | |
paul@2 | 145 | palette = range(0, 8) * 2 |
paul@2 | 146 | |
paul@40 | 147 | def __init__(self, ram, video): |
paul@1 | 148 | |
paul@40 | 149 | "Initialise the ULA with the given 'ram' and 'video' instances." |
paul@2 | 150 | |
paul@40 | 151 | self.ram = ram |
paul@31 | 152 | self.video = video |
paul@2 | 153 | self.set_mode(6) |
paul@1 | 154 | |
paul@31 | 155 | self.reset() |
paul@31 | 156 | |
paul@31 | 157 | def reset(self): |
paul@31 | 158 | |
paul@31 | 159 | "Reset the ULA." |
paul@31 | 160 | |
paul@43 | 161 | # General state. |
paul@43 | 162 | |
paul@43 | 163 | self.nmi = 0 # no NMI asserted initially |
paul@43 | 164 | self.irq_vsync = 0 # no IRQ asserted initially |
paul@43 | 165 | |
paul@59 | 166 | # Communication. |
paul@59 | 167 | |
paul@59 | 168 | self.ram_address = 0 # address given to the RAM via RA0...RA7 |
paul@59 | 169 | self.data = 0 # data read from the RAM via RAM0...RAM3 |
paul@59 | 170 | self.cpu_address = 0 # address selected by the CPU via A0...A15 |
paul@59 | 171 | self.cpu_read = 0 # data read/write by the CPU selected using R/W |
paul@59 | 172 | |
paul@40 | 173 | # Internal state. |
paul@40 | 174 | |
paul@50 | 175 | self.cycle = [0]*8 # counter within each 2MHz period represented by 8 latches |
paul@40 | 176 | self.access = 0 # counter used to determine whether a byte needs reading |
paul@42 | 177 | self.have_pixels = 0 # whether pixel data has been read |
paul@42 | 178 | self.writing_pixels = 0 # whether pixel data can be written |
paul@45 | 179 | self.buffer = [BLANK]*8 # pixel buffer for decoded RAM data |
paul@40 | 180 | |
paul@50 | 181 | self.cycle[7] = 1 # assert the final latch (asserting the first on update) |
paul@50 | 182 | |
paul@40 | 183 | self.reset_vertical() |
paul@31 | 184 | |
paul@2 | 185 | def set_mode(self, mode): |
paul@1 | 186 | |
paul@2 | 187 | """ |
paul@2 | 188 | For the given 'mode', initialise the... |
paul@1 | 189 | |
paul@2 | 190 | * width in pixels |
paul@2 | 191 | * colour depth in bits per pixel |
paul@2 | 192 | * number of character rows |
paul@2 | 193 | * character row size in bytes |
paul@2 | 194 | * screen size in bytes |
paul@2 | 195 | * default screen start address |
paul@2 | 196 | * horizontal pixel scaling factor |
paul@2 | 197 | * line spacing in pixels |
paul@2 | 198 | * number of entries in the pixel buffer |
paul@31 | 199 | |
paul@31 | 200 | The ULA should be reset after a mode switch in order to cleanly display |
paul@31 | 201 | a full screen. |
paul@2 | 202 | """ |
paul@1 | 203 | |
paul@3 | 204 | self.width, self.depth, rows = self.modes[mode] |
paul@3 | 205 | |
paul@31 | 206 | columns = (self.width * self.depth) / 8 # bits read -> bytes read |
paul@40 | 207 | self.access_frequency = 80 / columns # cycle frequency for reading bytes |
paul@31 | 208 | row_size = columns * LINES_PER_ROW |
paul@2 | 209 | |
paul@3 | 210 | # Memory access configuration. |
paul@4 | 211 | # Note the limitation on positioning the screen start. |
paul@3 | 212 | |
paul@4 | 213 | screen_size = row_size * rows |
paul@4 | 214 | self.screen_start = (SCREEN_LIMIT - screen_size) & 0xff00 |
paul@4 | 215 | self.screen_size = SCREEN_LIMIT - self.screen_start |
paul@3 | 216 | |
paul@3 | 217 | # Scanline configuration. |
paul@1 | 218 | |
paul@22 | 219 | self.xscale = MAX_WIDTH / self.width # pixel width in display pixels |
paul@3 | 220 | self.spacing = MAX_HEIGHT / rows - LINES_PER_ROW # pixels between rows |
paul@3 | 221 | |
paul@3 | 222 | # Start of unused region. |
paul@3 | 223 | |
paul@3 | 224 | self.footer = rows * LINES_PER_ROW |
paul@22 | 225 | self.margin = MAX_SCANLINE - rows * (LINES_PER_ROW + self.spacing) + self.spacing |
paul@3 | 226 | |
paul@3 | 227 | # Internal pixel buffer size. |
paul@3 | 228 | |
paul@2 | 229 | self.buffer_limit = 8 / self.depth |
paul@1 | 230 | |
paul@40 | 231 | def vsync(self, value=0): |
paul@40 | 232 | |
paul@40 | 233 | "Signal the start of a frame." |
paul@40 | 234 | |
paul@40 | 235 | self.csync = value |
paul@40 | 236 | self.video.set_csync(value) |
paul@40 | 237 | |
paul@40 | 238 | def hsync(self, value=0): |
paul@40 | 239 | |
paul@40 | 240 | "Signal the end of a scanline." |
paul@40 | 241 | |
paul@40 | 242 | self.hs = value |
paul@40 | 243 | self.video.set_hs(value) |
paul@40 | 244 | |
paul@40 | 245 | def reset_vertical(self): |
paul@2 | 246 | |
paul@2 | 247 | "Signal the start of a frame." |
paul@1 | 248 | |
paul@2 | 249 | self.line_start = self.address = self.screen_start |
paul@5 | 250 | self.line = self.line_start % LINES_PER_ROW |
paul@3 | 251 | self.ssub = 0 |
paul@31 | 252 | self.y = 0 |
paul@40 | 253 | self.x = 0 |
paul@2 | 254 | |
paul@40 | 255 | def reset_horizontal(self): |
paul@1 | 256 | |
paul@40 | 257 | "Reset horizontal state within the active region of the frame." |
paul@31 | 258 | |
paul@31 | 259 | self.y += 1 |
paul@40 | 260 | self.x = 0 |
paul@40 | 261 | |
paul@40 | 262 | if not self.inside_frame(): |
paul@40 | 263 | return |
paul@2 | 264 | |
paul@3 | 265 | # Support spacing between character rows. |
paul@3 | 266 | |
paul@3 | 267 | if self.ssub: |
paul@3 | 268 | self.ssub -= 1 |
paul@3 | 269 | return |
paul@3 | 270 | |
paul@2 | 271 | self.line += 1 |
paul@2 | 272 | |
paul@3 | 273 | # If not on a row boundary, move to the next line. |
paul@3 | 274 | |
paul@3 | 275 | if self.line % LINES_PER_ROW: |
paul@2 | 276 | self.address = self.line_start + 1 |
paul@2 | 277 | self.wrap_address() |
paul@2 | 278 | |
paul@2 | 279 | # After the end of the last line in a row, the address should already |
paul@2 | 280 | # have been positioned on the last line of the next column. |
paul@1 | 281 | |
paul@2 | 282 | else: |
paul@2 | 283 | self.address -= LINES_PER_ROW - 1 |
paul@2 | 284 | self.wrap_address() |
paul@1 | 285 | |
paul@3 | 286 | # Test for the footer region. |
paul@3 | 287 | |
paul@3 | 288 | if self.spacing and self.line == self.footer: |
paul@22 | 289 | self.ssub = self.margin |
paul@3 | 290 | return |
paul@1 | 291 | |
paul@3 | 292 | # Support spacing between character rows. |
paul@2 | 293 | |
paul@22 | 294 | self.ssub = self.spacing |
paul@3 | 295 | |
paul@3 | 296 | self.line_start = self.address |
paul@1 | 297 | |
paul@40 | 298 | def in_frame(self): return MIN_PIXELLINE <= self.y < MAX_PIXELLINE |
paul@40 | 299 | def inside_frame(self): return MIN_PIXELLINE < self.y < MAX_PIXELLINE |
paul@42 | 300 | def read_pixels(self): return MIN_PIXELPOS <= self.x < MAX_PIXELPOS and self.in_frame() |
paul@31 | 301 | |
paul@31 | 302 | def update(self): |
paul@1 | 303 | |
paul@2 | 304 | """ |
paul@40 | 305 | Update the state of the ULA for each clock cycle. This involves updating |
paul@40 | 306 | the pixel colour by reading from the pixel buffer. |
paul@2 | 307 | """ |
paul@2 | 308 | |
paul@40 | 309 | # Detect the end of the scanline. |
paul@40 | 310 | |
paul@40 | 311 | if self.x == MAX_SCANPOS: |
paul@40 | 312 | self.reset_horizontal() |
paul@40 | 313 | |
paul@40 | 314 | # Detect the end of the frame. |
paul@40 | 315 | |
paul@40 | 316 | if self.y == MAX_SCANLINE: |
paul@40 | 317 | self.reset_vertical() |
paul@40 | 318 | |
paul@40 | 319 | |
paul@40 | 320 | |
paul@40 | 321 | # Clock management. |
paul@40 | 322 | |
paul@43 | 323 | access_ram = not self.nmi and self.access == 0 and self.read_pixels() and not self.ssub |
paul@40 | 324 | |
paul@50 | 325 | # Update the state of the device. |
paul@50 | 326 | # NOTE: This is not meant to be "nice" Python, but instead models the |
paul@50 | 327 | # NOTE: propagation of state through the latches. |
paul@50 | 328 | |
paul@50 | 329 | self.cycle[0], self.cycle[1], self.cycle[2], self.cycle[3], \ |
paul@50 | 330 | self.cycle[4], self.cycle[5], self.cycle[6], self.cycle[7] = \ |
paul@50 | 331 | self.cycle[7], self.cycle[0], self.cycle[1], self.cycle[2], \ |
paul@50 | 332 | self.cycle[3], self.cycle[4], self.cycle[5], self.cycle[6] |
paul@50 | 333 | |
paul@40 | 334 | # Set row address (for ULA access only). |
paul@40 | 335 | |
paul@50 | 336 | if self.cycle[0]: |
paul@40 | 337 | |
paul@59 | 338 | # Either assert a required address or propagate the CPU address. |
paul@40 | 339 | |
paul@40 | 340 | if access_ram: |
paul@59 | 341 | self.init_row_address(self.address) |
paul@59 | 342 | else: |
paul@59 | 343 | self.init_row_address(self.cpu_address) |
paul@40 | 344 | |
paul@42 | 345 | # Initialise the pixel buffer if appropriate. |
paul@42 | 346 | |
paul@42 | 347 | if not self.writing_pixels and self.have_pixels: |
paul@42 | 348 | self.xcounter = self.xscale |
paul@42 | 349 | self.buffer_index = 0 |
paul@42 | 350 | self.fill_pixel_buffer() |
paul@42 | 351 | self.writing_pixels = 1 |
paul@42 | 352 | |
paul@40 | 353 | # Latch row address, set column address (for ULA access only). |
paul@40 | 354 | |
paul@50 | 355 | elif self.cycle[1]: |
paul@40 | 356 | |
paul@59 | 357 | # Select an address needed by the ULA or CPU. |
paul@59 | 358 | |
paul@59 | 359 | self.ram.row_select(self.ram_address) |
paul@59 | 360 | |
paul@59 | 361 | # Either assert a required address or propagate the CPU address. |
paul@31 | 362 | |
paul@40 | 363 | if access_ram: |
paul@59 | 364 | self.init_column_address(self.address, 0) |
paul@59 | 365 | else: |
paul@59 | 366 | self.init_column_address(self.cpu_address, 0) |
paul@40 | 367 | |
paul@40 | 368 | # Latch column address. |
paul@40 | 369 | |
paul@50 | 370 | elif self.cycle[2]: |
paul@40 | 371 | |
paul@59 | 372 | # Select an address needed by the ULA or CPU. |
paul@31 | 373 | |
paul@59 | 374 | self.ram.column_select(self.ram_address) |
paul@40 | 375 | |
paul@40 | 376 | # Read 4 bits (for ULA access only). |
paul@40 | 377 | # NOTE: Perhaps map alternate bits, not half-bytes. |
paul@40 | 378 | |
paul@50 | 379 | elif self.cycle[3]: |
paul@40 | 380 | |
paul@59 | 381 | # Either read from a required address or transfer CPU data. |
paul@40 | 382 | |
paul@40 | 383 | if access_ram: |
paul@40 | 384 | self.data = self.ram.data << 4 |
paul@59 | 385 | else: |
paul@59 | 386 | self.cpu_transfer_high() |
paul@40 | 387 | |
paul@40 | 388 | # Set column address (for ULA access only). |
paul@40 | 389 | |
paul@50 | 390 | elif self.cycle[4]: |
paul@40 | 391 | self.ram.column_deselect() |
paul@31 | 392 | |
paul@59 | 393 | # Either assert a required address or propagate the CPU address. |
paul@40 | 394 | |
paul@40 | 395 | if access_ram: |
paul@59 | 396 | self.init_column_address(self.address, 1) |
paul@59 | 397 | else: |
paul@59 | 398 | self.init_column_address(self.cpu_address, 1) |
paul@40 | 399 | |
paul@40 | 400 | # Latch column address. |
paul@40 | 401 | |
paul@50 | 402 | elif self.cycle[5]: |
paul@40 | 403 | |
paul@59 | 404 | # Select an address needed by the ULA or CPU. |
paul@40 | 405 | |
paul@59 | 406 | self.ram.column_select(self.ram_address) |
paul@31 | 407 | |
paul@40 | 408 | # Read 4 bits (for ULA access only). |
paul@40 | 409 | # NOTE: Perhaps map alternate bits, not half-bytes. |
paul@40 | 410 | |
paul@50 | 411 | elif self.cycle[6]: |
paul@40 | 412 | |
paul@59 | 413 | # Either read from a required address or transfer CPU data. |
paul@40 | 414 | |
paul@40 | 415 | if access_ram: |
paul@40 | 416 | self.data = self.data | self.ram.data |
paul@42 | 417 | self.have_pixels = 1 |
paul@40 | 418 | |
paul@40 | 419 | # Advance to the next column. |
paul@40 | 420 | |
paul@40 | 421 | self.address += LINES_PER_ROW |
paul@40 | 422 | self.wrap_address() |
paul@59 | 423 | else: |
paul@59 | 424 | self.cpu_transfer_low() |
paul@40 | 425 | |
paul@40 | 426 | # Reset addresses. |
paul@31 | 427 | |
paul@50 | 428 | elif self.cycle[7]: |
paul@40 | 429 | self.ram.column_deselect() |
paul@40 | 430 | self.ram.row_deselect() |
paul@40 | 431 | |
paul@40 | 432 | # Update the RAM access controller. |
paul@40 | 433 | |
paul@40 | 434 | self.access = (self.access + 1) % self.access_frequency |
paul@40 | 435 | |
paul@40 | 436 | |
paul@40 | 437 | |
paul@40 | 438 | # Video signalling. |
paul@40 | 439 | |
paul@40 | 440 | # Detect any sync conditions. |
paul@31 | 441 | |
paul@40 | 442 | if self.x == 0: |
paul@40 | 443 | self.hsync() |
paul@40 | 444 | if self.y == 0: |
paul@40 | 445 | self.vsync() |
paul@43 | 446 | self.irq_vsync = 0 |
paul@43 | 447 | elif self.y == MAX_PIXELLINE: |
paul@43 | 448 | self.irq_vsync = 1 |
paul@40 | 449 | |
paul@40 | 450 | # Detect the end of hsync. |
paul@31 | 451 | |
paul@40 | 452 | elif self.x == MAX_HSYNC: |
paul@40 | 453 | self.hsync(1) |
paul@40 | 454 | |
paul@40 | 455 | # Detect the end of vsync. |
paul@40 | 456 | |
paul@40 | 457 | elif self.y == MAX_CSYNC and self.x == MAX_SCANPOS / 2: |
paul@40 | 458 | self.vsync(1) |
paul@40 | 459 | |
paul@40 | 460 | |
paul@40 | 461 | |
paul@40 | 462 | # Pixel production. |
paul@31 | 463 | |
paul@3 | 464 | # Detect spacing between character rows. |
paul@3 | 465 | |
paul@42 | 466 | if not self.writing_pixels or self.ssub: |
paul@31 | 467 | self.video.colour = BLANK |
paul@3 | 468 | |
paul@31 | 469 | # For pixels within the frame, obtain and output the value. |
paul@31 | 470 | |
paul@31 | 471 | else: |
paul@40 | 472 | |
paul@42 | 473 | self.xcounter -= 1 |
paul@42 | 474 | self.video.colour = self.buffer[self.buffer_index] |
paul@1 | 475 | |
paul@31 | 476 | # Scale pixels horizontally, only accessing the next pixel value |
paul@31 | 477 | # after the required number of scan positions. |
paul@22 | 478 | |
paul@42 | 479 | if self.xcounter == 0: |
paul@40 | 480 | self.xcounter = self.xscale |
paul@31 | 481 | self.buffer_index += 1 |
paul@31 | 482 | |
paul@42 | 483 | # Handle the buffer empty condition. |
paul@22 | 484 | |
paul@40 | 485 | if self.buffer_index >= self.buffer_limit: |
paul@42 | 486 | self.writing_pixels = 0 |
paul@2 | 487 | |
paul@31 | 488 | self.x += 1 |
paul@2 | 489 | |
paul@2 | 490 | def fill_pixel_buffer(self): |
paul@1 | 491 | |
paul@2 | 492 | """ |
paul@2 | 493 | Fill the pixel buffer by translating memory content for the current |
paul@2 | 494 | mode. |
paul@2 | 495 | """ |
paul@1 | 496 | |
paul@40 | 497 | byte_value = self.data # which should have been read automatically |
paul@1 | 498 | |
paul@2 | 499 | i = 0 |
paul@2 | 500 | for colour in decode(byte_value, self.depth): |
paul@2 | 501 | self.buffer[i] = get_physical_colour(self.palette[colour]) |
paul@2 | 502 | i += 1 |
paul@2 | 503 | |
paul@2 | 504 | def wrap_address(self): |
paul@2 | 505 | if self.address >= SCREEN_LIMIT: |
paul@2 | 506 | self.address -= self.screen_size |
paul@1 | 507 | |
paul@59 | 508 | def init_row_address(self, address): |
paul@59 | 509 | self.ram_address = (address & 0xff80) >> 7 |
paul@59 | 510 | |
paul@59 | 511 | def init_column_address(self, address, offset): |
paul@59 | 512 | self.ram_address = (address & 0x7f) << 1 | offset |
paul@59 | 513 | |
paul@59 | 514 | def cpu_transfer_high(self): |
paul@59 | 515 | if self.cpu_read: |
paul@59 | 516 | self.cpu_data = self.ram.data << 4 |
paul@59 | 517 | |
paul@59 | 518 | def cpu_transfer_low(self): |
paul@59 | 519 | if self.cpu_read: |
paul@59 | 520 | self.cpu_data = self.data | self.ram.data |
paul@59 | 521 | |
paul@1 | 522 | def get_physical_colour(value): |
paul@1 | 523 | |
paul@1 | 524 | """ |
paul@1 | 525 | Return the physical colour as an RGB triple for the given 'value'. |
paul@1 | 526 | """ |
paul@1 | 527 | |
paul@1 | 528 | return value & 1, value >> 1 & 1, value >> 2 & 1 |
paul@1 | 529 | |
paul@1 | 530 | def decode(value, depth): |
paul@1 | 531 | |
paul@1 | 532 | """ |
paul@1 | 533 | Decode the given byte 'value' according to the 'depth' in bits per pixel, |
paul@1 | 534 | returning a sequence of pixel values. |
paul@1 | 535 | """ |
paul@1 | 536 | |
paul@1 | 537 | if depth == 1: |
paul@1 | 538 | return (value >> 7, value >> 6 & 1, value >> 5 & 1, value >> 4 & 1, |
paul@1 | 539 | value >> 3 & 1, value >> 2 & 1, value >> 1 & 1, value & 1) |
paul@1 | 540 | elif depth == 2: |
paul@1 | 541 | return (value >> 6 & 2 | value >> 3 & 1, value >> 5 & 2 | value >> 2 & 1, |
paul@1 | 542 | value >> 4 & 2 | value >> 1 & 1, value >> 3 & 2 | value & 1) |
paul@1 | 543 | elif depth == 4: |
paul@1 | 544 | return (value >> 4 & 8 | value >> 3 & 4 | value >> 2 & 2 | value >> 1 & 1, |
paul@1 | 545 | value >> 3 & 8 | value >> 2 & 4 | value >> 1 & 2 | value & 1) |
paul@1 | 546 | else: |
paul@1 | 547 | raise ValueError, "Only depths of 1, 2 and 4 are supported, not %d." % depth |
paul@1 | 548 | |
paul@1 | 549 | # Convenience functions. |
paul@1 | 550 | |
paul@1 | 551 | def encode(values, depth): |
paul@1 | 552 | |
paul@1 | 553 | """ |
paul@1 | 554 | Encode the given 'values' according to the 'depth' in bits per pixel, |
paul@1 | 555 | returning a byte value for the pixels. |
paul@1 | 556 | """ |
paul@1 | 557 | |
paul@1 | 558 | result = 0 |
paul@1 | 559 | |
paul@1 | 560 | if depth == 1: |
paul@1 | 561 | for value in values: |
paul@1 | 562 | result = result << 1 | (value & 1) |
paul@1 | 563 | elif depth == 2: |
paul@1 | 564 | for value in values: |
paul@1 | 565 | result = result << 1 | (value & 2) << 3 | (value & 1) |
paul@1 | 566 | elif depth == 4: |
paul@1 | 567 | for value in values: |
paul@1 | 568 | result = result << 1 | (value & 8) << 3 | (value & 4) << 2 | (value & 2) << 1 | (value & 1) |
paul@1 | 569 | else: |
paul@1 | 570 | raise ValueError, "Only depths of 1, 2 and 4 are supported, not %d." % depth |
paul@1 | 571 | |
paul@1 | 572 | return result |
paul@1 | 573 | |
paul@11 | 574 | def get_ula(): |
paul@11 | 575 | |
paul@31 | 576 | "Return a ULA initialised with a memory array and video." |
paul@31 | 577 | |
paul@40 | 578 | return ULA(get_ram(), get_video()) |
paul@11 | 579 | |
paul@31 | 580 | def get_video(): |
paul@31 | 581 | |
paul@31 | 582 | "Return a video circuit." |
paul@31 | 583 | |
paul@31 | 584 | return Video() |
paul@11 | 585 | |
paul@40 | 586 | def get_ram(): |
paul@10 | 587 | |
paul@40 | 588 | "Return an instance representing the computer's RAM hardware." |
paul@7 | 589 | |
paul@40 | 590 | return RAM() |
paul@1 | 591 | |
paul@7 | 592 | # Test program providing coverage (necessary for compilers like Shedskin). |
paul@7 | 593 | |
paul@7 | 594 | if __name__ == "__main__": |
paul@11 | 595 | ula = get_ula() |
paul@7 | 596 | ula.set_mode(2) |
paul@40 | 597 | ula.reset() |
paul@40 | 598 | ula.ram.fill(0x5800 - 320, 0x8000, encode((2, 7), 4)) |
paul@7 | 599 | |
paul@7 | 600 | # Make a simple two-dimensional array of tuples (three-dimensional in pygame |
paul@7 | 601 | # terminology). |
paul@7 | 602 | |
paul@29 | 603 | a = update(ula) |
paul@7 | 604 | |
paul@1 | 605 | # vim: tabstop=4 expandtab shiftwidth=4 |