paul@22 | 1 | Timing
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paul@22 | 2 | ------
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paul@22 | 3 |
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paul@22 | 4 | According to the above (15.3.2 in the AUG), there are 312 scanlines, 256 of
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paul@22 | 5 | which are used to generate pixel data. At 50Hz, this means that 128 cycles are
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paul@22 | 6 | used to produce pixel data (2000000 / 50 = 40000; 40000 / 312 ~= 128). This is
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paul@22 | 7 | consistent with the observation that each scanline requires at most 80 bytes
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paul@22 | 8 | of data, and that the ULA is apparently busy for 40 out of 64 microseconds in
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paul@22 | 9 | each scanline.
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paul@22 | 10 |
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paul@22 | 11 | See: The Advanced User Guide for the Acorn Electron
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paul@22 | 12 | See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
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paul@22 | 13 |
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paul@0 | 14 | Hardware Scrolling
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paul@0 | 15 | ------------------
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paul@0 | 16 |
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paul@0 | 17 | On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
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paul@0 | 18 | the least significant 5 bits being zero, thus limiting the scrolling
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paul@0 | 19 | resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
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paul@0 | 20 | using the same layout of these addresses.
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paul@0 | 21 |
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paul@0 | 22 | |--&FE02--------------| |--&FE03--------------|
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paul@0 | 23 | XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
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paul@0 | 24 |
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paul@0 | 25 | XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
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paul@0 | 26 |
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paul@4 | 27 | Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
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paul@4 | 28 | memory to pixel locations is character oriented. A change in 8 bytes would
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paul@4 | 29 | permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
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paul@4 | 30 | MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
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paul@4 | 31 | observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
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paul@4 | 32 | Guide).
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paul@4 | 33 |
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paul@4 | 34 | One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
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paul@4 | 35 | of changing the screen address by 2 bytes is the change in the number of lines
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paul@4 | 36 | from the initial and final character rows that need reading by the ULA, which
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paul@9 | 37 | would need to maintain this state information (although this is a relatively
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paul@9 | 38 | trivial change). Another pitfall is the complication that might be introduced
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paul@9 | 39 | to software writing bitmaps of character height to the screen.
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paul@4 | 40 |
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paul@4 | 41 | Region Blanking
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paul@4 | 42 | ---------------
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paul@4 | 43 |
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paul@4 | 44 | The problem of permitting character-oriented blitting in programs whilst
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paul@4 | 45 | scrolling the screen by sub-character amounts could be mitigated by permitting
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paul@4 | 46 | a region of the display to be blank, such as the final lines of the display.
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paul@4 | 47 | Consider the following vertical scrolling by 2 bytes that would cause an
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paul@4 | 48 | initial character row of 6 lines and a final character row of 2 lines:
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paul@4 | 49 |
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paul@4 | 50 | 6 lines - initial, partial character row
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paul@4 | 51 | 248 lines - 31 complete rows
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paul@4 | 52 | 2 lines - final, partial character row
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paul@4 | 53 |
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paul@4 | 54 | If a routine were in use that wrote 8 line bitmaps to the partial character
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paul@4 | 55 | row now split in two, it would be advisable to hide one of the regions in
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paul@4 | 56 | order to prevent content appearing in the wrong place on screen (such as
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paul@4 | 57 | content meant to appear at the top "leaking" onto the bottom). Blanking 6
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paul@4 | 58 | lines would be sufficient, as can be seen from the following cases.
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paul@4 | 59 |
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paul@4 | 60 | Scrolling up by 2 lines:
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paul@4 | 61 |
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paul@4 | 62 | 6 lines - initial, partial character row
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paul@4 | 63 | 240 lines - 30 complete rows
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paul@4 | 64 | 4 lines - part of 1 complete row
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paul@4 | 65 | -----------------------------------------------------------------
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paul@4 | 66 | 4 lines - part of 1 complete row (hidden to maintain 250 lines)
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paul@4 | 67 | 2 lines - final, partial character row (hidden)
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paul@4 | 68 |
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paul@4 | 69 | Scrolling down by 2 lines:
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paul@4 | 70 |
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paul@4 | 71 | 2 lines - initial, partial character row
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paul@4 | 72 | 248 lines - 31 complete rows
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paul@4 | 73 | ----------------------------------------------------------
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paul@4 | 74 | 6 lines - final, partial character row (hidden)
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paul@4 | 75 |
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paul@4 | 76 | Thus, region blanking would impose a 250 line display with the bottom 6 lines
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paul@4 | 77 | blank. The height of the screen could be configurable still further.
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paul@0 | 78 |
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paul@0 | 79 | Palette Definition
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paul@0 | 80 | ------------------
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paul@0 | 81 |
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paul@0 | 82 | Since all memory accesses go via the ULA, an enhanced ULA could employ more
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paul@0 | 83 | specific addresses than &FE*X to perform enhanced functions. For example, the
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paul@0 | 84 | palette control is done using &FE*8-F and merely involves selecting predefined
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paul@0 | 85 | colours, whereas an enhanced ULA could support the redefinition of all 16
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paul@0 | 86 | colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
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paul@0 | 87 | (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
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paul@0 | 88 | specifications similar to those used on the Archimedes.
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paul@0 | 89 |
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paul@4 | 90 | The principal limitation here is actually the hardware: the Electron has only
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paul@4 | 91 | a single output line for each of the red, green and blue channels, and if
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paul@4 | 92 | those outputs are strictly digital and can only be set to a "high" and "low"
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paul@4 | 93 | value, then only the existing eight colours are possible. If a modern ULA were
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paul@4 | 94 | able to output analogue values, it would still need to be assessed whether the
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paul@4 | 95 | circuitry could successfully handle and propagate such values.
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paul@4 | 96 |
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paul@4 | 97 | Palette Definition Lists
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paul@4 | 98 | ------------------------
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paul@4 | 99 |
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paul@4 | 100 | It can be useful to redefine the palette in order to change the colours
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paul@4 | 101 | available for a particular region of the screen, particularly in modes where
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paul@4 | 102 | the choice of colours is constrained, and if an increased colour depth were
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paul@4 | 103 | available, palette redefinition would be useful to give the illusion of more
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paul@4 | 104 | than 16 colours in MODE 2. Traditionally, palette redefinition has been done
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paul@4 | 105 | by using interrupt-driven timers, but a more efficient approach would involve
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paul@4 | 106 | presenting lists of palette definitions to the ULA so that it can change the
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paul@4 | 107 | palette at a particular display line.
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paul@4 | 108 |
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paul@4 | 109 | One might define a palette redefinition list in a region of memory and then
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paul@4 | 110 | communicate its contents to the ULA by writing the address and length of the
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paul@4 | 111 | list, along with the display line at which the palette is to be changed, to
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paul@4 | 112 | ULA registers such that the ULA buffers the list and performs the redefinition
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paul@4 | 113 | at the appropriate time. Throughput/bandwidth considerations might impose
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paul@4 | 114 | restrictions on the practical length of such a list, however.
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paul@4 | 115 |
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paul@4 | 116 | Palette-Free Modes
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paul@4 | 117 | ------------------
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paul@4 | 118 |
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paul@4 | 119 | Palette-free modes might be defined where bit values directly correspond to
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paul@4 | 120 | the red, green and blue channels, although this would mostly make sense only
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paul@4 | 121 | for modes with depths greater than the standard 4 bits per pixel, and such
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paul@4 | 122 | modes would require more memory than MODE 2 if they were to have an acceptable
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paul@4 | 123 | resolution.
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paul@4 | 124 |
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paul@4 | 125 | Display Suspend
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paul@4 | 126 | ---------------
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paul@4 | 127 |
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paul@4 | 128 | Especially when writing to the screen memory, it could be beneficial to be
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paul@4 | 129 | able to suspend the ULA's access to the memory, instead producing blank values
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paul@4 | 130 | for all screen pixels until a program is ready to reveal the screen. This is
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paul@4 | 131 | different from palette blanking since with a blank palette, the ULA is still
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paul@4 | 132 | reading screen memory and translating its contents into pixel values that end
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paul@4 | 133 | up being blank.
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paul@4 | 134 |
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paul@4 | 135 | This function is reminiscent of a capability of the ZX81, albeit necessary on
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paul@4 | 136 | that hardware to reduce the load on the system CPU which was responsible for
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paul@4 | 137 | producing the video output.
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paul@4 | 138 |
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paul@9 | 139 | Hardware Sprites and Colour Planes
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paul@9 | 140 | ----------------------------------
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paul@0 | 141 |
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paul@0 | 142 | An enhanced ULA might provide hardware sprites, but this would be done in an
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paul@0 | 143 | way that is incompatible with the standard ULA, since no &FE*X locations are
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paul@0 | 144 | available for allocation. In a special ULA mode, one might allocate a pair of
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paul@0 | 145 | locations (for example, &FE20 and &FE21) as a pair of registers referencing a
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paul@0 | 146 | region of memory from which a sprite might be found and potentially copied
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paul@0 | 147 | into internal RAM, with other locations (for example, &FE22 and &FE23)
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paul@4 | 148 | providing the size of the region. Alternatively, one might write the region
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paul@4 | 149 | location and size through a single ULA location, with the ULA being put into a
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paul@4 | 150 | particular state after each write. For example: read LSB of region, read MSB
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paul@4 | 151 | of region, read size, read height.
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paul@0 | 152 |
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paul@9 | 153 | Providing hardware sprites can be awkward without having some kind of working
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paul@9 | 154 | area, since the ULA would need to remember where each sprite is to be plotted
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paul@9 | 155 | and then deduce which sprites would be contributing to any given pixel. An
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paul@9 | 156 | alternative is to use memory into which the sprites would be plotted, and this
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paul@9 | 157 | memory would be combined with the main screen memory, taking a particular
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paul@9 | 158 | colour as the "colourkey" which is to be considered transparent, and only
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paul@9 | 159 | overwriting the main screen pixels with pixel values for other colours.
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paul@9 | 160 |
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paul@0 | 161 | Enhanced Graphics
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paul@0 | 162 | -----------------
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paul@0 | 163 |
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paul@0 | 164 | Screen modes with different screen memory mappings, higher resolutions and
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paul@0 | 165 | larger colour depths might be possible, but this would in most cases involve
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paul@0 | 166 | the allocation of more screen memory, and the ULA would probably then be
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paul@0 | 167 | obliged to page in such memory for the CPU to be able to sensibly access it
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paul@0 | 168 | all. Merely changing the memory mappings in order to have Archimedes-style
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paul@0 | 169 | row-oriented screen addresses (instead of character-oriented addresses) could
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paul@0 | 170 | be done for the existing modes, but this might not be sufficiently beneficial,
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paul@0 | 171 | especially since accessing regions of the screen would involve incrementing
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paul@0 | 172 | pointers by amounts that are inconvenient on an 8-bit CPU.
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paul@0 | 173 |
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paul@0 | 174 | Enhanced Sound
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paul@0 | 175 | --------------
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paul@0 | 176 |
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paul@0 | 177 | The standard ULA reserves &FE*6 for sound generation and cassette
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paul@0 | 178 | input/output, thus making it impossible to support multiple channels within
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paul@0 | 179 | the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
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paul@0 | 180 | and an enhanced ULA could adopt this interface.
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paul@0 | 181 |
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paul@9 | 182 | The BBC Micro uses the SN76489 chip to produce sound, and the entire
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paul@9 | 183 | functionality of this chip could be emulated for enhanced sound, with a subset
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paul@9 | 184 | of the functionality exposed via the &FE*6 interface.
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paul@9 | 185 |
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paul@9 | 186 | See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
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paul@9 | 187 |
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paul@0 | 188 | Waveform Upload
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paul@0 | 189 | ---------------
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paul@0 | 190 |
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paul@0 | 191 | As with a hardware sprite function, waveforms could be uploaded or referenced
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paul@0 | 192 | using locations as registers referencing memory regions.
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paul@0 | 193 |
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paul@0 | 194 | BBC ULA Compatibility
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paul@0 | 195 | ---------------------
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paul@0 | 196 |
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paul@0 | 197 | Although some new ULA functions could be defined in a way that is also
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paul@0 | 198 | compatible with the BBC Micro, the BBC ULA is itself incompatible with the
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paul@0 | 199 | Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
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paul@0 | 200 | map, but controls various functions specific to the 6845 video controller;
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paul@0 | 201 | &FE08-F is reserved for the serial controller. It therefore becomes possible
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paul@0 | 202 | to disregard compatibility where compatibility is already disregarded for a
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paul@0 | 203 | particular area of functionality.
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paul@0 | 204 |
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paul@0 | 205 | &FE20-F maps to video ULA functionality on the BBC Micro which provides
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paul@0 | 206 | control over the palette (using address &FE21, compared to &FE07-F on the
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paul@0 | 207 | Electron) and other system-specific functions. Since the location usage is
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paul@0 | 208 | generally incompatible, this region could be reused for other purposes.
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