1.1 --- a/ULA.txt Tue Apr 07 21:31:19 2020 +0200
1.2 +++ b/ULA.txt Tue Apr 07 22:13:13 2020 +0200
1.3 @@ -137,6 +137,36 @@
1.4 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
1.5 See: http://stardot.org.uk/forums/viewtopic.php?p=120438#p120438
1.6
1.7 +A Note on 8-Bit Wide RAM Access
1.8 +-------------------------------
1.9 +
1.10 +It is worth considering the timing when 8 bits of data can be obtained at once
1.11 +from the RAM chips:
1.12 +
1.13 + Time (ns): 0-------------- 500------------- ...
1.14 + 2 MHz cycle: 0 1 ...
1.15 + 8 MHz cycle: 0 1 2 3 0 1 2 3 ...
1.16 + /-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_ ...
1.17 + ~RAS: /---\___________/---\___________ ...
1.18 + ~CAS: /-------\_______/-------\_______ ...
1.19 +Address events: A B A B ...
1.20 + Data events: F F ...
1.21 +
1.22 + ~RAS ops: 1 0 1 0 ...
1.23 + ~CAS ops: 1 0 1 0 ...
1.24 +
1.25 + Address ops: a b a b ...
1.26 + Data ops: f s f ...
1.27 +
1.28 + ~WE: ........W ...
1.29 + PHI OUT: \_______/-------\_______/------- ...
1.30 + CPU: L D L D ...
1.31 + RnW: R R ...
1.32 +
1.33 +Since only one fetch is required per 2MHz cycle, instead of two fetches for
1.34 +the 4-bit wide RAM arrangement, it seems likely that longer 8MHz cycles could
1.35 +be used to coordinate the necessary signalling.
1.36 +
1.37 CPU Clock Notes
1.38 ---------------
1.39