1.1 --- a/ULA.txt Tue Jun 21 16:06:47 2016 +0200
1.2 +++ b/ULA.txt Tue Jun 21 20:18:37 2016 +0200
1.3 @@ -54,20 +54,28 @@
1.4 /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ ...
1.5 ~RAS: /---\___________/---\___________ ...
1.6 ~CAS: /-----\___/-\___/-----\___/-\___ ...
1.7 - A B C A B C ...
1.8 - F S F S ...
1.9 - a b c a b c ...
1.10 - s f s f ...
1.11 +Address events: A B C A B C ...
1.12 + Data events: F S F S ...
1.13
1.14 - ~WE: ......W ...
1.15 + ~RAS ops: 1 0 1 0 ...
1.16 + ~CAS ops: 1 0 1 0 1 0 1 0 ...
1.17 +
1.18 + Address ops: a b c a b c ...
1.19 + Data ops: s f s f ...
1.20 +
1.21 + ~WE: ......W ...
1.22 PHI OUT: \_______________/--------------- ...
1.23 CPU (RAM): L D ...
1.24 - RnW: R ...
1.25 + RnW: R ...
1.26
1.27 PHI OUT: \_______/-------\_______/------- ...
1.28 CPU (ROM): L D L D ...
1.29 RnW: R R ...
1.30
1.31 +~RAS must be high for 100ns, ~CAS must be high for 50ns.
1.32 +~RAS must be low for 150ns, ~CAS must be low for 90ns.
1.33 +Data is available 150ns after ~RAS goes low, 90ns after ~CAS goes low.
1.34 +
1.35 Here, "A" and "B" respectively indicate the row and first column addresses
1.36 being latched into the RAM (on a negative edge for ~RAS and ~CAS
1.37 respectively), and "C" indicates the second column address being latched into