1.1 --- a/ULA.txt Fri Oct 14 16:59:34 2022 +0200
1.2 +++ b/ULA.txt Fri Oct 14 17:01:47 2022 +0200
1.3 @@ -1543,13 +1543,53 @@
1.4 smaller unit of storage than a byte could possibly help to reduce the amount
1.5 of storage and bandwidth required to reproduce the characters on the display.
1.6
1.7 -Enhancement: High Resolution Graphics
1.8 --------------------------------------
1.9 +Enhancement: High Resolution Graphics and Larger Colour Depths
1.10 +--------------------------------------------------------------
1.11
1.12 Screen modes with higher resolutions and larger colour depths might be
1.13 possible, but this would in most cases involve the allocation of more screen
1.14 memory, and the ULA would probably then be obliged to page in such memory for
1.15 -the CPU to be able to sensibly access it all.
1.16 +the CPU to be able to sensibly access it all. Higher resolutions would also
1.17 +involve a faster pixel clock.
1.18 +
1.19 +However, we may consider a doubled colour depth and the need for higher
1.20 +bandwidth transfers by a ULA having an 8-bit data bus to access the RAM,
1.21 +utilising two "page mode" transfers per 2MHz cycle. If such transfers were to
1.22 +access consecutive bytes in the same memory region (for example, bytes &3000
1.23 +and &3001) this would require a change to the arrangement of screen memory,
1.24 +also incurring changes to the memory map for larger modes:
1.25 +
1.26 + (&3000 &3001) (&3010 &3011) ...
1.27 + (&3002 &3003) (&3012 &3013)
1.28 + ... ...
1.29 + (&300E &300F) (&301E &301F)
1.30 +
1.31 +If such transfers were to access two adjacent columns of bytes (for example,
1.32 +bytes &3000 and &3008), this would still require a change in the step size
1.33 +across the screen memory, also incur memory map changes for larger modes, and
1.34 +the method for programs to update the screen would be more complicated:
1.35 +
1.36 + (&3000 &3008) (&3010 &3018) ...
1.37 + (&3001 &3009) (&3011 &3019)
1.38 + ... ...
1.39 + (&3007 &300F) (&3017 &301F)
1.40 +
1.41 +However, such transfers could instead map the device address bit that is
1.42 +toggled between transfers to the most significant system memory address bit.
1.43 +Thus, bits in adjacent locations within each RAM device would actually reside
1.44 +in different memory regions:
1.45 +
1.46 + (&3000 &B000) (&3008 &B008) ...
1.47 + (&3001 &B001) (&3009 &B009)
1.48 + ... ...
1.49 + (&3007 &B007) (&300F &B00F)
1.50 +
1.51 +Since &B000 can also be considered as &3000 combined with &8000, this
1.52 +introducing the asserted uppermost bit, address &B000 can be considered as
1.53 +&3000 in an upper memory bank.
1.54 +
1.55 +Other mechanisms might be employed to allow programs to access the uppermost
1.56 +bank, but the ULA would be able to access it trivially and unconditionally.
1.57
1.58 Enhancement: Genlock Support
1.59 ----------------------------