1.1 --- a/ULA.txt Sun Dec 18 19:29:20 2011 +0100
1.2 +++ b/ULA.txt Tue Dec 20 00:56:33 2011 +0100
1.3 @@ -8,7 +8,7 @@
1.4 of data, and that the ULA is apparently busy for 40 out of 64 microseconds in
1.5 each scanline.
1.6
1.7 -See: The Advanced User Guide for the Acorn Electron
1.8 +See: Acorn Electron Advanced User Guide
1.9 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
1.10
1.11 Hardware Scrolling
1.12 @@ -338,3 +338,75 @@
1.13 control over the palette (using address &FE21, compared to &FE07-F on the
1.14 Electron) and other system-specific functions. Since the location usage is
1.15 generally incompatible, this region could be reused for other purposes.
1.16 +
1.17 +ULA Pin Functions
1.18 +-----------------
1.19 +
1.20 +The functions of the ULA pins are described in the Electron Service Manual. Of
1.21 +interest to video processing are the following:
1.22 +
1.23 + CSYNC (low during horizontal or vertical synchronisation periods, high
1.24 + otherwise)
1.25 +
1.26 + HS (low during horizontal synchronisation periods, high otherwise)
1.27 +
1.28 + RED, GREEN, BLUE (pixel colour outputs)
1.29 +
1.30 + CLOCK IN (a 16MHz clock input, 4V peak to peak)
1.31 +
1.32 + PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
1.33 +
1.34 +More general memory access pins:
1.35 +
1.36 + RAM0...RAM3 (data lines to/from the RAM)
1.37 +
1.38 + RA0...RA7 (address lines for sending both row and column addresses to the RAM)
1.39 +
1.40 + RAS (row address strobe setting the row address on a negative edge)
1.41 +
1.42 + CAS (column address strobe setting the column address on a negative edge)
1.43 +
1.44 + WE (sets write enable with logic 0, read with logic 1)
1.45 +
1.46 + ROM (select data access from ROM)
1.47 +
1.48 +CPU-oriented memory access pins:
1.49 +
1.50 + A0...A15 (CPU address lines)
1.51 +
1.52 + PD0...PD7 (CPU data lines)
1.53 +
1.54 + R/W (indicates CPU write with logic 0, CPU read with logic 1)
1.55 +
1.56 +Interrupt-related pins:
1.57 +
1.58 + NMI (CPU request for uninterrupted 1MHz access to memory)
1.59 +
1.60 + IRQ (signal event to CPU)
1.61 +
1.62 + POR (power-on reset, resetting the ULA on a positive edge and asserting the
1.63 + CPU's RST pin)
1.64 +
1.65 + RST (master reset for the CPU signalled on power-up and by the Break key)
1.66 +
1.67 +Keyboard-related pins:
1.68 +
1.69 + KBD0...KBD3 (keyboard inputs)
1.70 +
1.71 + CAPS LOCK (control status LED)
1.72 +
1.73 +Sound-related pins:
1.74 +
1.75 + SOUND O/P (sound output using internal oscillator)
1.76 +
1.77 +Cassette-related pins:
1.78 +
1.79 + CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
1.80 +
1.81 + CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
1.82 +
1.83 + CAS RC (detect high tone)
1.84 +
1.85 + CAS MO (motor relay output)
1.86 +
1.87 + ÷13 IN (~1200 baud clock input)