1.1 --- a/ULA.txt Tue Apr 07 22:13:13 2020 +0200
1.2 +++ b/ULA.txt Sun Apr 12 17:05:08 2020 +0200
1.3 @@ -150,7 +150,7 @@
1.4 ~RAS: /---\___________/---\___________ ...
1.5 ~CAS: /-------\_______/-------\_______ ...
1.6 Address events: A B A B ...
1.7 - Data events: F F ...
1.8 + Data events: E E ...
1.9
1.10 ~RAS ops: 1 0 1 0 ...
1.11 ~CAS ops: 1 0 1 0 ...
1.12 @@ -163,10 +163,17 @@
1.13 CPU: L D L D ...
1.14 RnW: R R ...
1.15
1.16 +Here, "E" indicates the availability of an entire byte.
1.17 +
1.18 Since only one fetch is required per 2MHz cycle, instead of two fetches for
1.19 the 4-bit wide RAM arrangement, it seems likely that longer 8MHz cycles could
1.20 be used to coordinate the necessary signalling.
1.21
1.22 +Another conceivable simplification from using an 8-bit wide RAM access channel
1.23 +with a single access within each 2MHz cycle is the possibility of allowing the
1.24 +CPU to signal directly to the RAM instead of having the ULA perform the access
1.25 +signalling on the CPU's behalf.
1.26 +
1.27 CPU Clock Notes
1.28 ---------------
1.29