1.1 --- a/ULA.txt Sun Oct 16 01:27:06 2022 +0200
1.2 +++ b/ULA.txt Mon Oct 17 01:09:49 2022 +0200
1.3 @@ -72,7 +72,8 @@
1.4 ~RAS: /---\___________/---\___________ ...
1.5 ~CAS: /-----\___/-\___/-----\___/-\___ ...
1.6 Address events: A B C A B C ...
1.7 - Data events: F S F S ...
1.8 + Data events: ...F ...S ...F ...S ...
1.9 + ~WE: W W ...
1.10
1.11 ~RAS ops: 1 0 1 0 ...
1.12 ~CAS ops: 1 0 1 0 1 0 1 0 ...
1.13 @@ -80,14 +81,13 @@
1.14 Address ops: a.b. c. a.b. c. ...
1.15 Data ops: s f s f ...
1.16
1.17 - ~WE: ......W ...
1.18 - PHI OUT: \_______________/--------------- ...
1.19 - CPU (RAM): L D ...
1.20 - RnW: R ...
1.21 + PHI OUT: ----\_______/------------------- ...
1.22 + CPU (RAM): .....L ....D ...
1.23 + RnW: .....R ...
1.24
1.25 - PHI OUT: \_______/-------\_______/------- ...
1.26 - CPU (ROM): L D L D ...
1.27 - RnW: R R ...
1.28 + PHI OUT: ----\_______/-------\_______/--- ...
1.29 + CPU (ROM): D .....L ....D .....L .... ...
1.30 + RnW: .....R .....R ...
1.31
1.32 ~RAS must be high for 100ns, ~CAS must be high for 50ns.
1.33 ~RAS must be low for 150ns, ~CAS must be low for 90ns.
1.34 @@ -103,15 +103,6 @@
1.35 are brought low. Data can be read at "f" and "s" for the first and second
1.36 half-bytes respectively.
1.37
1.38 -For the CPU, "L" indicates the point at which an address is taken from the CPU
1.39 -address bus, on a negative edge of PHI OUT, with "D" being the point at which
1.40 -data may either be read or be asserted for writing, on a positive edge of PHI
1.41 -OUT. Here, PHI OUT is driven at 1MHz. Given that ~WE needs to be driven low
1.42 -for writing or high for reading, and thus propagates RnW from the CPU, this
1.43 -would need to be done before data would be retrieved and, according to the
1.44 -TM4164EC4 datasheet, even as late as the column address is presented and ~CAS
1.45 -brought low.
1.46 -
1.47 The TM4164EC4-15 has a row address access time of 150ns (maximum) and a column
1.48 address access time of 90ns (maximum), which appears to mean that ~RAS must be
1.49 held low for at least 150ns and that ~CAS must be held low for at least 90ns
1.50 @@ -133,6 +124,29 @@
1.51 from the RAM, which is approximately 7 cycles (at 16MHz): much longer than the
1.52 4 cycles that would be required for 2MHz operation.
1.53
1.54 +Write operations expose some uncertainty about the relationship between the
1.55 +ULA's RAM access schedule and the PHI OUT clock. The Service Manual shows PHI
1.56 +IN (which should be the ULA's PHI OUT signal) as being synchronised with ~RAS.
1.57 +Since the CPU makes its address available potentially as late as 140ns after
1.58 +its PHI2 clock goes low (this clock being broadly similar to PHI OUT), it
1.59 +would make no sense to expect the ULA to be able perform a memory access
1.60 +immediately. What seems more likely is that the CPU makes data available, and
1.61 +this is written during the next 2MHz cycle.
1.62 +
1.63 +For the CPU, "L" indicates the point at which an address is taken from the CPU
1.64 +address bus, following a negative edge of PHI OUT, with "D" being the point at
1.65 +which data may be asserted for writing, following a positive edge of PHI OUT.
1.66 +Here, PHI OUT is driven at 1MHz. Given that ~WE needs to be driven low for
1.67 +writing or high for reading, and thus propagates RnW from the CPU, this would
1.68 +need to be done before data would be retrieved and, according to the TM4164EC4
1.69 +datasheet, even as late as the column address is presented and ~CAS brought
1.70 +low.
1.71 +
1.72 +It must be concluded that where accesses are interleaved between the CPU and
1.73 +ULA, the CPU access begins concurrently with the ULA access, with the CPU
1.74 +address and data retained by the ULA, and after the ULA access, the rest of
1.75 +the CPU transaction occurs in the following 2MHz cycle.
1.76 +
1.77 See: Acorn Electron Advanced User Guide
1.78 See: Acorn Electron Service Manual
1.79 http://chrisacorns.computinghistory.org.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
1.80 @@ -140,6 +154,9 @@
1.81 See: http://stardot.org.uk/forums/viewtopic.php?p=120438#p120438
1.82 See: One of the Most Popular 65,536-Bit (64K) Dynamic RAMs The TMS 4164
1.83 http://smithsonianchips.si.edu/augarten/p64.htm
1.84 +See: https://www.mups.co.uk/project/hardware/acorn_electron/
1.85 +See: Rockwell R650X and R651X Microprocessors (CPU)
1.86 +See: http://wilsonminesco.com/6502primer/
1.87
1.88 A Note on 8-Bit Wide RAM Access
1.89 -------------------------------
1.90 @@ -154,18 +171,18 @@
1.91 ~RAS: /---\___________/---\___________ ...
1.92 ~CAS: /-------\_______/-------\_______ ...
1.93 Address events: A B A B ...
1.94 - Data events: E E ...
1.95 + Data events: ...E ...E ...
1.96 + ~WE: W W ...
1.97
1.98 ~RAS ops: 1 0 1 0 ...
1.99 ~CAS ops: 1 0 1 0 ...
1.100
1.101 - Address ops: a b a b ...
1.102 + Address ops: a. b. a. b. ...
1.103 Data ops: f s f ...
1.104
1.105 - ~WE: ........W ...
1.106 - PHI OUT: \_______/-------\_______/------- ...
1.107 - CPU: L D L D ...
1.108 - RnW: R R ...
1.109 + PHI OUT: ----\_______/-------\_______/--- ...
1.110 + CPU: D .....L ....D .....L .... ...
1.111 + RnW: .....R .....R ...
1.112
1.113 Here, "E" indicates the availability of an entire byte.
1.114
1.115 @@ -194,18 +211,18 @@
1.116 ~RAS: /---\___________/---\___________ ...
1.117 ~CAS: /-----\___/-\___/-----\___/-\___ ...
1.118 Address events: A B C A B C ...
1.119 - Data events: 1 2 1 2 ...
1.120 + Data events: ...1 ...2 ...1 ...2 ...
1.121 + ~WE: W W ...
1.122
1.123 ~RAS ops: 1 0 1 0 ...
1.124 ~CAS ops: 1 0 1 0 1 0 1 0 ...
1.125
1.126 - Address ops: a b c a b c ...
1.127 + Address ops: a.b. c a.b. c ...
1.128 Data ops: s f s f ...
1.129
1.130 - ~WE: ......W ...
1.131 - PHI OUT: \_______/-------\_______/------- ...
1.132 - CPU: L D L D ...
1.133 - RnW: R R ...
1.134 + PHI OUT: ----\_______/-------\_______/--- ...
1.135 + CPU: D .....L ....D .....L .... ...
1.136 + RnW: .....R .....R ...
1.137
1.138 Here, "1" and "2" in the data events correspond to whole byte accesses,
1.139 effectively upgrading the half-byte "F" and "S" events in the existing ULA