1 The Acorn Electron ULA
2 ======================
3
4 Principal Design and Feature Constraints
5 ----------------------------------------
6
7 The features of the ULA are limited by the amount of time and resources that
8 can be allocated to each activity necessary to support such features given the
9 fundamental obligations of the unit. Maintaining a screen display based on the
10 contents of RAM itself requires the ULA to have exclusive access to such
11 hardware resources for a significant period of time. Whilst other elements of
12 the ULA can in principle run in parallel with this activity, they cannot also
13 access the RAM. Consequently, other features that might use the RAM must
14 accept a reduced allocation of that resource in comparison to a hypothetical
15 architecture where concurrent RAM access is possible.
16
17 Thus, the principal constraint for many features is bandwidth. The duration of
18 access to hardware resources is one aspect of this; the rate at which such
19 resources can be accessed is another. For example, the RAM is not fast enough
20 to support access more frequently than one byte per 2MHz cycle, and for screen
21 modes involving 80 bytes of screen data per scanline, there are no free cycles
22 for anything other than the production of pixel output during the active
23 scanline periods.
24
25 Timing
26 ------
27
28 According to 15.3.2 in the Advanced User Guide, there are 312 scanlines, 256
29 of which are used to generate pixel data. At 50Hz, this means that 128 cycles
30 are spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
31 312 ~= 128 cycles). This is consistent with the observation that each scanline
32 requires at most 80 bytes of data, and that the ULA is apparently busy for 40
33 out of 64 microseconds in each scanline.
34
35 (In fact, since the ULA is seeking to provide an image for an interlaced
36 625-line display, there are in fact two "fields" involved, one providing 312
37 scanlines and one providing 313 scanlines. See below for a description of the
38 video system.)
39
40 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
41 each providing two bits of each byte) using two cycles within the 500ns period
42 of the 2MHz clock to complete each access operation. Since the CPU and ULA
43 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
44 effectively run at 1MHz (since every other 500ns period involves the ULA
45 accessing RAM). The CPU is driven by an external clock (IC8) whose 16MHz
46 frequency is divided by the ULA (IC1) depending on the screen mode in use.
47
48 Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
49 patterns corresponding to 16MHz cycles are required:
50
51 Time (ns): 0-------------- 500------------- ...
52 2 MHz cycle: 0 1 ...
53 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
54 /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ ...
55 ~RAS: /---\___________/---\___________ ...
56 ~CAS: /-----\___/-\___/-----\___/-\___ ...
57 A B C A B C ...
58 F S F S ...
59 a b c a b c ...
60 s f s f ...
61
62 ~WE: ......W ...
63 PHI OUT: \_______________/--------------- ...
64 CPU (RAM): L D ...
65 RnW: R ...
66
67 PHI OUT: \_______/-------\_______/------- ...
68 CPU (ROM): L D L D ...
69 RnW: R R ...
70
71 Here, "A" and "B" respectively indicate the row and first column addresses
72 being latched into the RAM (on a negative edge for ~RAS and ~CAS
73 respectively), and "C" indicates the second column address being latched into
74 the RAM. Presumably, the first and second half-bytes can be read at "F" and
75 "S" respectively, and the row and column addresses must be made available at
76 "a" and "b" (and "c") respectively at the latest. Data can be read at "f" and
77 "s" for the first and second half-bytes respectively.
78
79 For the CPU, "L" indicates the point at which an address is taken from the CPU
80 address bus, on a negative edge of PHI OUT, with "D" being the point at which
81 data may either be read or be asserted for writing, on a positive edge of PHI
82 OUT. Here, PHI OUT is driven at 1MHz. Given that ~WE needs to be driven low
83 for writing or high for reading, and thus propagates RnW from the CPU, this
84 would need to be done before data would be retrieved and, according to the
85 TM4164EC4 datasheet, even as late as the column address is presented and ~CAS
86 brought low.
87
88 The TM4164EC4-15 has a row address access time of 150ns (maximum) and a column
89 address access time of 90ns (maximum), which appears to mean that ~RAS must be
90 held low for at least 150ns and that ~CAS must be held low for at least 90ns
91 before data becomes available. 150ns is 2.4 cycles (at 16MHz) and 90ns is 1.44
92 cycles. Thus, "A" to "F" is 2.5 cycles, "B" to "F" is 1.5 cycles, "C" to "S"
93 is 1.5 cycles.
94
95 Note that the Service Manual refers to the negative edge of RAS and CAS, but
96 the datasheet for the similar TM4164EC4 product shows latching on the negative
97 edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
98 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
99 "page mode" provides the appropriate behaviour for that particular product.
100
101 The CPU, when accessing the RAM alone, apparently does not make use of the
102 vacated "slot" that the ULA would otherwise use (when interleaving accesses in
103 MODE 4, 5 and 6). It only employs a full 2MHz access frequency to memory when
104 accessing ROM (and potentially sideways RAM).
105
106 See: Acorn Electron Advanced User Guide
107 See: Acorn Electron Service Manual
108 http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
109 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
110 See: http://stardot.org.uk/forums/viewtopic.php?p=120438#p120438
111
112 Bandwidth Figures
113 -----------------
114
115 Using an observation of 128 2MHz cycles per scanline, 256 active lines and 312
116 total lines, with 80 cycles occurring in the active periods of display
117 scanlines, the following bandwidth calculations can be performed:
118
119 Total theoretical maximum:
120 128 cycles * 312 lines
121 = 39936 bytes
122
123 MODE 0, 1, 2:
124 ULA: 80 cycles * 256 lines
125 = 20480 bytes
126 CPU: 48 cycles / 2 * 256 lines
127 + 128 cycles / 2 * (312 - 256) lines
128 = 9728 bytes
129
130 MODE 3:
131 ULA: 80 cycles * 24 rows * 8 lines
132 = 15360 bytes
133 CPU: 48 cycles / 2 * 24 rows * 8 lines
134 + 128 cycles / 2 * (312 - (24 rows * 8 lines))
135 = 12288 bytes
136
137 MODE 4, 5:
138 ULA: 40 cycles * 256 lines
139 = 10240 bytes
140 CPU: (40 cycles + 48 cycles / 2) * 256 lines
141 + 128 cycles / 2 * (312 - 256) lines
142 = 19968 bytes
143
144 MODE 6:
145 ULA: 40 cycles * 24 rows * 8 lines
146 = 7680 bytes
147 CPU: (40 cycles + 48 cycles / 2) * 24 rows * 8 lines
148 + 128 cycles / 2 * (312 - (24 rows * 8 lines))
149 = 19968 bytes
150
151 Here, the division of 2 for CPU accesses is performed to indicate that the CPU
152 only uses every other access opportunity even in uncontended periods. See the
153 2MHz RAM Access enhancement below for bandwidth calculations that consider
154 this limitation removed.
155
156 Video Timing
157 ------------
158
159 According to 8.7 in the Service Manual, and the PAL Wikipedia page,
160 approximately 4.7µs is used for the sync pulse, 5.7µs for the "back porch"
161 (including the "colour burst"), and 1.65µs for the "front porch", totalling
162 12.05µs and thus leaving 51.95µs for the active video signal for each
163 scanline. As the Service Manual suggests in the oscilloscope traces, the
164 display information is transmitted more or less centred within the active
165 video period since the ULA will only be providing pixel data for 40µs in each
166 scanline.
167
168 Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that
169 each scanline can be divided into 1024 cycles, although only 640 at most are
170 actively used to provide pixel data. Pixel data production should only occur
171 within a certain period on each scanline, approximately 262 cycles after the
172 start of hsync:
173
174 active video period = 51.95µs
175 pixel data period = 40µs
176 total silent period = 51.95µs - 40µs = 11.95µs
177 silent periods (before and after) = 11.95µs / 2 = 5.975µs
178 hsync and back porch period = 4.7µs + 5.7µs = 10.4µs
179 time before pixel data period = 10.4µs + 5.975µs = 16.375µs
180 pixel data period start cycle = 16.375µs / 62.5ns = 262
181
182 By choosing a number divisible by 8, the RAM access mechanism can be
183 synchronised with the pixel production. Thus, 256 is a more appropriate start
184 cycle, where the HS (horizontal sync) signal corresponding to the 4µs sync
185 pulse (or "normal sync" pulse as described by the "PAL TV timing and voltages"
186 document) occurs at cycle 0.
187
188 To summarise:
189
190 HS signal starts at cycle 0 on each horizontal scanline
191 HS signal ends approximately 4µs later at cycle 64
192 Pixel data starts approximately 12µs later at cycle 256
193
194 "Re: Electron Memory Contention" provides measurements that appear consistent
195 with these calculations.
196
197 The "vertical blanking period", meaning the period before picture information
198 in each field is 25 lines out of 312 (or 313) and thus lasts for 1.6ms. Of
199 this, 2.5 lines occur before the vsync (field sync) which also lasts for 2.5
200 lines. Thus, the first visible scanline on the first field of a frame occurs
201 half way through the 23rd scanline period measured from the start of vsync
202 (indicated by "V" in the diagrams below):
203
204 10 20 23
205 Line in frame: 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
206 Line from 1: 0 22 3
207 Line on screen: .:::::VVVVV::::: 12233445566
208 |_________________________________________________|
209 25 line vertical blanking period
210
211 In the second field of a frame, the first visible scanline coincides with the
212 24th scanline period measured from the start of line 313 in the frame:
213
214 310 336
215 Line in frame: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
216 Line from 313: 0 23 4
217 Line on screen: 88:::::VVVVV:::: 11223344
218 288 | |
219 |_________________________________________________|
220 25 line vertical blanking period
221
222 In order to consider only full lines, we might consider the start of each
223 frame to occur 23 lines after the start of vsync.
224
225 Again, it is likely that pixel data production should only occur on scanlines
226 within a certain period on each frame. The "625/50" document indicates that
227 only a certain region is "safe" to use, suggesting a vertically centred region
228 with approximately 15 blank lines above and below the picture. However, the
229 "PAL TV timing and voltages" document suggests 28 blank lines above and below
230 the picture. This would centre the 256 lines within the 312 lines of each
231 field and thus provide a start of picture approximately 5.5 or 5 lines after
232 the end of the blanking period or 28 or 27.5 lines after the start of vsync.
233
234 To summarise:
235
236 CSYNC signal starts at cycle 0
237 CSYNC signal ends approximately 160µs (2.5 lines) later at cycle 2560
238 Start of line occurs approximately 1632µs (5.5 lines) later at cycle 28672
239
240 See: http://en.wikipedia.org/wiki/PAL
241 See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal
242 See: The 625/50 PAL Video Signal and TV Compatible Graphics Modes
243 http://lipas.uwasa.fi/~f76998/video/modes/
244 See: PAL TV timing and voltages
245 http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
246 See: Line Standards
247 http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html
248 See: Horizontal Blanking Interval of 405-, 525-, 625- and 819-Line Standards
249 http://www.pembers.freeserve.co.uk/World-TV-Standards/HBI.pdf
250 See: Re: Electron Memory Contention
251 http://www.stardot.org.uk/forums/viewtopic.php?p=134109#p134109
252
253 RAM Integrated Circuits
254 -----------------------
255
256 Unicorn Electronics appears to offer 4164 RAM chips (as well as 6502 series
257 CPUs such as the 6502, 6502A, 6502B and 65C02). These 4164 devices are
258 available in 100ns (4164-100), 120ns (4164-120) and 150ns (4164-150) variants,
259 have 16 pins and address 65536 bits through a 1-bit wide channel. Similarly,
260 ByteDelight.com sell 4164 devices primarily for the ZX Spectrum.
261
262 The documentation for the Electron mentions 4164-15 RAM chips for IC4-7, and
263 the Samsung-produced KM41464 series is apparently equivalent to the Texas
264 Instruments 4164 chips presumably used in the Electron.
265
266 The TM4164EC4 series combines 4 64K x 1b units into a single package and
267 appears similar to the TM4164EA4 featured on the Electron's circuit diagram
268 (in the Advanced User Guide but not the Service Manual), and it also has 22
269 pins providing 3 additional inputs and 3 additional outputs over the 16 pins
270 of the individual 4164-15 modules, presumably allowing concurrent access to
271 the packaged memory units.
272
273 As far as currently available replacements are concerned, the NTE4164 is a
274 potential candidate: according to the Vetco Electronics entry, it is
275 supposedly a replacement for the TMS4164-15 amongst many other parts. Similar
276 parts include the NTE2164 and the NTE6664, both of which appear to have
277 largely the same performance and connection characteristics. Meanwhile, the
278 NTE21256 appears to be a 16-pin replacement with four times the capacity that
279 maintains the single data input and output pins. Using the NTE21256 as a
280 replacement for all ICs combined would be difficult because of the single bit
281 output.
282
283 Another device equivalent to the 4164-15 appears to be available under the
284 code 41662 from Jameco Electronics as the Siemens HYB 4164-2. The Jameco Web
285 site lists data sheets for other devices on the same page, but these are
286 different and actually appear to be provided under the 41574 product code (but
287 are listed under 41464-10) and appear to be replacements for the TM4164EC4:
288 the Samsung KM41464A-15 and NEC µPD41464 employ 18 pins, eliminating 4 pins by
289 employing 4 pins for both input and output.
290
291 Pins I/O pins Row access Column access
292 ---- -------- ---------- -------------
293 TM4164EC4 22 4 + 4 150ns (15) 90ns (15)
294 KM41464AP 18 4 150ns (15) 75ns (15)
295 NTE21256 16 1 + 1 150ns 75ns
296 HYB 4164-2 16 1 + 1 150ns 100ns
297 µPD41464 18 4 120ns (12) 60ns (12)
298
299 See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module
300 http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
301 See: Dynamic RAMS
302 http://www.unicornelectronics.com/IC/DYNAMIC.html
303 See: New old stock 8x 4164 chips
304 http://www.bytedelight.com/?product=8x-4164-chips-new-old-stock
305 See: KM4164B 64K x 1 Bit Dynamic RAM with Page Mode
306 http://images.ihscontent.net/vipimages/VipMasterIC/IC/SAMS/SAMSD020/SAMSD020-45.pdf
307 See: NTE2164 Integrated Circuit 65,536 X 1 Bit Dynamic Random Access Memory
308 http://www.vetco.net/catalog/product_info.php?products_id=2806
309 See: NTE4164 - IC-NMOS 64K DRAM 150NS
310 http://www.vetco.net/catalog/product_info.php?products_id=3680
311 See: NTE21256 - IC-256K DRAM 150NS
312 http://www.vetco.net/catalog/product_info.php?products_id=2799
313 See: NTE21256 262,144-Bit Dynamic Random Access Memory (DRAM)
314 http://www.nteinc.com/specs/21000to21999/pdf/nte21256.pdf
315 See: NTE6664 - IC-MOS 64K DRAM 150NS
316 http://www.vetco.net/catalog/product_info.php?products_id=5213
317 See: NTE6664 Integrated Circuit 64K-Bit Dynamic RAM
318 http://www.nteinc.com/specs/6600to6699/pdf/nte6664.pdf
319 See: 4164-150: MAJOR BRANDS
320 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41662_-1
321 See: HYB 4164-1, HYB 4164-2, HYB 4164-3 65,536-Bit Dynamic Random Access Memory (RAM)
322 http://www.jameco.com/Jameco/Products/ProdDS/41662SIEMENS.pdf
323 See: KM41464A NMOS DRAM 64K x 4 Bit Dynamic RAM with Page Mode
324 http://www.jameco.com/Jameco/Products/ProdDS/41662SAM.pdf
325 See: NEC µ41464 65,536 x 4-Bit Dynamic NMOS RAM
326 http://www.jameco.com/Jameco/Products/ProdDS/41662NEC.pdf
327 See: 41464-10: MAJOR BRANDS
328 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41574_-1
329
330 Interrupts
331 ----------
332
333 The ULA generates IRQs (maskable interrupts) according to certain conditions
334 and these conditions are controlled by location &FE00:
335
336 * Vertical sync (bottom of displayed screen)
337 * 50MHz real time clock
338 * Transmit data empty
339 * Receive data full
340 * High tone detect
341
342 The ULA is also used to clear interrupt conditions through location &FE05. Of
343 particular significance is bit 7, which must be set if an NMI (non-maskable
344 interrupt) has occurred and has thus suspended ULA access to memory, restoring
345 the normal function of the ULA.
346
347 ROM Paging
348 ----------
349
350 Accessing different ROMs involves bits 0 to 3 of &FE05. Some special ROM
351 mappings exist:
352
353 8 keyboard
354 9 keyboard (duplicate)
355 10 BASIC ROM
356 11 BASIC ROM (duplicate)
357
358 Paging in a ROM involves the following procedure:
359
360 1. Assert ROM page enable (bit 3) together with a ROM number n in bits 0 to
361 2, corresponding to ROM number 8+n, such that one of ROMs 12 to 15 is
362 selected.
363 2. Where a ROM numbered from 0 to 7 is to be selected, set bit 3 to zero
364 whilst writing the desired ROM number n in bits 0 to 2.
365
366 See: http://stardot.org.uk/forums/viewtopic.php?p=136686#p136686
367
368 Shadow/Expanded Memory
369 ----------------------
370
371 The Electron exposes all sixteen address lines and all eight data lines
372 through the expansion bus. Using such lines, it is possible to provide
373 additional memory - typically sideways ROM and RAM - on expansion cards and
374 through cartridges, although the official cartridge specification provides
375 fewer address lines and only seeks to provide access to memory in 16K units.
376
377 Various modifications and upgrades were developed to offer "turbo"
378 capabilities to the Electron, permitting the CPU to access a separate 8K of
379 RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
380 the ULA through additional logic. However, an enhanced ULA might support
381 independent CPU access to memory over the expansion bus by allowing itself to
382 be discharged from providing access to memory, potentially for a range of
383 addresses, and for the CPU to communicate with external memory uninterrupted.
384
385 Sideways RAM/ROM and Upper Memory Access
386 ----------------------------------------
387
388 Although the ULA controls the CPU clock, effectively slowing or stopping the
389 CPU when the ULA needs to access screen memory, it is apparently able to allow
390 the CPU to access addresses of &8000 and above - the upper region of memory -
391 at 2MHz independently of any access to RAM that the ULA might be performing,
392 only blocking the CPU if it attempts to access addresses of &7FFF and below
393 during any ULA memory access - the lower region of memory - by stopping or
394 stalling its clock.
395
396 Thus, the ULA remains aware of the level of the A15 line, only inhibiting the
397 CPU clock if the line goes low, when the CPU is attempting to access the lower
398 region of memory.
399
400 Hardware Scrolling (and Enhancement)
401 ------------------------------------
402
403 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
404 the least significant 5 bits being zero, thus limiting the scrolling
405 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
406 using the same layout of these addresses.
407
408 |--&FE02--------------| |--&FE03--------------|
409 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
410
411 XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
412
413 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
414 memory to pixel locations is character oriented. A change in 8 bytes would
415 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
416 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
417 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
418 Guide).
419
420 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
421 of changing the screen address by 2 bytes is the change in the number of lines
422 from the initial and final character rows that need reading by the ULA, which
423 would need to maintain this state information (although this is a relatively
424 trivial change). Another pitfall is the complication that might be introduced
425 to software writing bitmaps of character height to the screen.
426
427 See: http://pastraiser.com/computers/acornelectron/acornelectron.html
428
429 Enhancement: Mode Layouts
430 -------------------------
431
432 Merely changing the screen memory mappings in order to have Archimedes-style
433 row-oriented screen addresses (instead of character-oriented addresses) could
434 be done for the existing modes, but this might not be sufficiently beneficial,
435 especially since accessing regions of the screen would involve incrementing
436 pointers by amounts that are inconvenient on an 8-bit CPU.
437
438 However, instead of using a Archimedes-style mapping, column-oriented screen
439 addresses could be more feasibly employed: incrementing the address would
440 reference the vertical screen location below the currently-referenced location
441 (just as occurs within characters using the existing ULA); instead of
442 returning to the top of the character row and referencing the next horizontal
443 location after eight bytes, the address would reference the next character row
444 and continue to reference locations downwards over the height of the screen
445 until reaching the bottom; at the bottom, the next location would be the next
446 horizontal location at the top of the screen.
447
448 In other words, the memory layout for the screen would resemble the following
449 (for MODE 2):
450
451 &3000 &3100 ... &7F00
452 &3001 &3101
453 ... ...
454 &3007
455 &3008
456 ...
457 ... ...
458 &30FF ... &7FFF
459
460 Since there are 256 pixel rows, each column of locations would be addressable
461 using the low byte of the address. Meanwhile, the high byte would be
462 incremented to address different columns. Thus, addressing screen locations
463 would become a lot more convenient and potentially much more efficient for
464 certain kinds of graphical output.
465
466 One potential complication with this simplified addressing scheme arises with
467 hardware scrolling. Vertical hardware scrolling by one pixel row (not supported
468 with the existing ULA) would be achieved by incrementing or decrementing the
469 screen start address; by one character row, it would involve adding or
470 subtracting 8. However, the ULA only supports multiples of 64 when changing the
471 screen start address. Thus, if such a scheme were to be adopted, three
472 additional bits would need to be supported in the screen start register (see
473 "Hardware Scrolling (and Enhancement)" for more details). However, horizontal
474 scrolling would be much improved even under the severe constraints of the
475 existing ULA: only adjustments of 256 to the screen start address would be
476 required to produce single-location scrolling of as few as two pixels in MODE 2
477 (four pixels in MODEs 1 and 5, eight pixels otherwise).
478
479 More disruptive is the effect of this alternative layout on software.
480 Presumably, compatibility with the BBC Micro was the primary goal of the
481 Electron's hardware design. With the character-oriented screen layout in
482 place, system software (and application software accessing the screen
483 directly) would be relying on this layout to run on the Electron with little
484 or no modification. Although it might have been possible to change the system
485 software to use this column-oriented layout instead, this would have incurred
486 a development cost and caused additional work porting things like games to the
487 Electron. Moreover, a separate branch of the software from that supporting the
488 BBC Micro and closer derivatives would then have needed maintaining.
489
490 The decision to use the character-oriented layout in the BBC Micro may have
491 been related to the choice of circuitry and to facilitate a convenient
492 hardware implementation, and by the time the Electron was planned, it was too
493 late to do anything about this somewhat unfortunate choice.
494
495 Pixel Layouts
496 -------------
497
498 The pixel layouts are as follows:
499
500 Modes Depth (bpp) Pixels (from bits)
501 ----- ----------- ------------------
502 0, 3, 4, 6 1 7 6 5 4 3 2 1 0
503 1, 5 2 73 62 51 40
504 2 4 7531 6420
505
506 Since the ULA reads a half-byte at a time, one might expect it to attempt to
507 produce pixels for every half-byte, as opposed to handling entire bytes.
508 However, the pixel layout is not conducive to producing pixels as soon as a
509 half-byte has been read for a given full-byte location: in 1bpp modes the
510 first four pixels can indeed be produced, but in 2bpp and 4bpp modes the pixel
511 data is spread across the entire byte in different ways.
512
513 An alternative arrangement might be as follows:
514
515 Modes Depth (bpp) Pixels (from bits)
516 ----- ----------- ------------------
517 0, 3, 4, 6 1 7 6 5 4 3 2 1 0
518 1, 5 2 76 54 32 10
519 2 4 7654 3210
520
521 Just as the mode layouts were presumably decided by compatibility with the BBC
522 Micro, the pixel layouts will have been maintained for similar reasons.
523 Unfortunately, this layout prevents any optimisation of the ULA for handling
524 half-byte pixel data generally.
525
526 Enhancement: The Missing MODE 4
527 -------------------------------
528
529 The Electron inherits its screen mode selection from the BBC Micro, where MODE
530 3 is a text version of MODE 0, and where MODE 6 is a text version of MODE 4.
531 Neither MODE 3 nor MODE 6 is a genuine character-based text mode like MODE 7,
532 however, and they are merely implemented by skipping two scanlines in every
533 ten after the eight required to produce a character line. Thus, such modes
534 provide a 24-row display.
535
536 In principle, nothing prevents this "text mode" effect being applied to other
537 modes. The 20-column modes are not well-suited to displaying text, which
538 leaves MODE 1 which, unlike MODEs 3 and 6, can display 4 colours rather than
539 2. Although the need for a non-monochrome 40-column text mode is addressed by
540 MODE 7 on the BBC Micro, the Electron lacks such a mode.
541
542 If the 4-colour, 24-row variant of MODE 1 were to be provided, logically it
543 would occupy MODE 4 instead of the current MODE 4:
544
545 Screen mode Size (kilobytes) Colours Rows Resolution
546 ----------- ---------------- ------- ---- ----------
547 0 20 2 32 640x256
548 1 20 4 32 320x256
549 2 20 16 32 160x256
550 3 16 2 24 640x256
551 4 (new) 16 4 24 320x256
552 4 (old) 10 2 32 320x256
553 5 10 4 32 160x256
554 6 8 2 24 320x256
555
556 Thus, for increasing mode numbers, the size of each mode would be the same or
557 less than the preceding mode.
558
559 Enhancement: 2MHz RAM Access
560 ----------------------------
561
562 Given that the CPU and ULA both access RAM at 2MHz, but given that the CPU
563 when not competing with the ULA only accesses RAM every other 2MHz cycle (as
564 if the ULA still needed to access the RAM), one useful enhancement would be a
565 mechanism to let the CPU take over the ULA cycles outside the ULA's period of
566 activity comparable to the way the ULA takes over the CPU cycles in MODE 0 to
567 3.
568
569 Thus, the RAM access cycles would resemble the following in MODE 0 to 3:
570
571 Upon a transition from display cycles: UUUUCCCC (instead of UUUUC_C_)
572 On a non-display line: CCCCCCCC (instead of C_C_C_C_)
573
574 In MODE 4 to 6:
575
576 Upon a transition from display cycles: CUCUCCCC (instead of CUCUC_C_)
577 On a non-display line: CCCCCCCC (instead of C_C_C_C_)
578
579 This would improve CPU bandwidth as follows:
580
581 Standard ULA Enhanced ULA
582 MODE 0, 1, 2 9728 bytes 19456 bytes
583 MODE 3 12288 bytes 24576 bytes
584 MODE 4, 5 19968 bytes 29696 bytes
585 MODE 6 19968 bytes 32256 bytes
586
587 With such an enhancement, MODE 0 to 3 experience a doubling of CPU bandwidth
588 because all access opportunities to RAM are doubled. Meanwhile, in the other
589 modes, some CPU accesses occur alongside ULA accesses and thus cannot be
590 doubled, but the CPU bandwidth increase is still significant.
591
592 Enhancement: Region Blanking
593 ----------------------------
594
595 The problem of permitting character-oriented blitting in programs whilst
596 scrolling the screen by sub-character amounts could be mitigated by permitting
597 a region of the display to be blank, such as the final lines of the display.
598 Consider the following vertical scrolling by 2 bytes that would cause an
599 initial character row of 6 lines and a final character row of 2 lines:
600
601 6 lines - initial, partial character row
602 248 lines - 31 complete rows
603 2 lines - final, partial character row
604
605 If a routine were in use that wrote 8 line bitmaps to the partial character
606 row now split in two, it would be advisable to hide one of the regions in
607 order to prevent content appearing in the wrong place on screen (such as
608 content meant to appear at the top "leaking" onto the bottom). Blanking 6
609 lines would be sufficient, as can be seen from the following cases.
610
611 Scrolling up by 2 lines:
612
613 6 lines - initial, partial character row
614 240 lines - 30 complete rows
615 4 lines - part of 1 complete row
616 -----------------------------------------------------------------
617 4 lines - part of 1 complete row (hidden to maintain 250 lines)
618 2 lines - final, partial character row (hidden)
619
620 Scrolling down by 2 lines:
621
622 2 lines - initial, partial character row
623 248 lines - 31 complete rows
624 ----------------------------------------------------------
625 6 lines - final, partial character row (hidden)
626
627 Thus, in this case, region blanking would impose a 250 line display with the
628 bottom 6 lines blank.
629
630 See the description of the display suspend enhancement for a more efficient
631 way of blanking lines than merely blanking the palette whilst allowing the CPU
632 to perform useful work during the blanking period.
633
634 To control the blanking or suspending of lines at the top and bottom of the
635 display, a memory location could be dedicated to the task: the upper 4 bits
636 could define a blanking region of up to 16 lines at the top of the screen,
637 whereas the lower 4 bits could define such a region at the bottom of the
638 screen. If more lines were required, two locations could be employed, allowing
639 the top and bottom regions to occupy the entire screen.
640
641 Enhancement: Screen Height Adjustment
642 -------------------------------------
643
644 The height of the screen could be configurable in order to reduce screen
645 memory consumption. This is not quite done in MODE 3 and 6 since the start of
646 the screen appears to be rounded down to the nearest page, but by reducing the
647 height by amounts more than a page, savings would be possible. For example:
648
649 Screen width Depth Height Bytes per line Saving in bytes Start address
650 ------------ ----- ------ -------------- --------------- -------------
651 640 1 252 80 320 &3140 -> &3100
652 640 1 248 80 640 &3280 -> &3200
653 320 1 240 40 640 &5A80 -> &5A00
654 320 2 240 80 1280 &3500
655
656 Screen Mode Selection
657 ---------------------
658
659 Bits 3, 4 and 5 of address &FE*7 control the selected screen mode. For a wider
660 range of modes, the other bits of &FE*7 (related to sound, cassette
661 input/output and the Caps Lock LED) would need to be reassigned and bit 0
662 potentially being made available for use.
663
664 Enhancement: Palette Definition
665 -------------------------------
666
667 Since all memory accesses go via the ULA, an enhanced ULA could employ more
668 specific addresses than &FE*X to perform enhanced functions. For example, the
669 palette control is done using &FE*8-F and merely involves selecting predefined
670 colours, whereas an enhanced ULA could support the redefinition of all 16
671 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
672 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
673 specifications similar to those used on the Archimedes.
674
675 The principal limitation here is actually the hardware: the Electron has only
676 a single output line for each of the red, green and blue channels, and if
677 those outputs are strictly digital and can only be set to a "high" and "low"
678 value, then only the existing eight colours are possible. If a modern ULA were
679 able to output analogue values (or values at well-defined points between the
680 high and low values, such as the half-on value supported by the Amstrad CPC
681 series), it would still need to be assessed whether the circuitry could
682 successfully handle and propagate such values. Various sources indicate that
683 only "TTL levels" are supported by the RGB output circuit, and since there are
684 74LS08 AND logic gates involved in the RGB component outputs from the ULA, it
685 is likely that the ULA is expected to provide only "high" or "low" values.
686
687 Short of adding extra outputs from the ULA (either additional red, green and
688 blue outputs or a combined intensity output), another approach might involve
689 some kind of modulation where an output value might be encoded in multiple
690 pulses at a higher frequency than the pixel frequency. However, this would
691 demand additional circuitry outside the ULA, and component RGB monitors would
692 probably not be able to take advantage of this feature; only UHF and composite
693 video devices (the latter with the composite video colour support enabled on
694 the Electron's circuit board) would potentially benefit.
695
696 Flashing Colours
697 ----------------
698
699 According to the Advanced User Guide, "The cursor and flashing colours are
700 entirely generated in software: This means that all of the logical to physical
701 colour map must be changed to cause colours to flash." This appears to suggest
702 that the palette registers must be updated upon the flash counter - read and
703 written by OSBYTE &C1 (193) - reaching zero and that some way of changing the
704 colour pairs to be any combination of colours might be possible, instead of
705 having colour complements as pairs.
706
707 It is conceivable that the interrupt code responsible does the simple thing
708 and merely inverts the current values for any logical colours (LC) for which
709 the associated physical colour (as supplied as the second parameter to the VDU
710 19 call) has the top bit of its four bit value set. These top bits are not
711 recorded in the palette registers but are presumably recorded separately and
712 used to build bitmaps as follows:
713
714 LC 2 colour 4 colour 16 colour 4-bit value for inversion
715 -- -------- -------- --------- -------------------------
716 0 00010001 00010001 00010001 1, 1, 1
717 1 01000100 00100010 00010001 4, 2, 1
718 2 01000100 00100010 4, 2
719 3 10001000 00100010 8, 2
720 4 00010001 1
721 5 00010001 1
722 6 00100010 2
723 7 00100010 2
724 8 01000100 4
725 9 01000100 4
726 10 10001000 8
727 11 10001000 8
728 12 01000100 4
729 13 01000100 4
730 14 10001000 8
731 15 10001000 8
732
733 Inversion value calculation:
734
735 2 colour formula: 1 << (colour * 2)
736 4 colour formula: 1 << colour
737 16 colour formula: 1 << ((colour & 2) + ((colour & 8) * 2))
738
739 For example, where logical colour 0 has been mapped to a physical colour in
740 the range 8 to 15, a bitmap of 00010001 would be chosen as its contribution to
741 the inversion operation. (The lower three bits of the physical colour would be
742 used to set the underlying colour information affected by the inversion
743 operation.)
744
745 An operation in the interrupt code would then combine the bitmaps for all
746 logical colours in 2 and 4 colour modes, with the 16 colour bitmaps being
747 combined for groups of logical colours as follows:
748
749 Logical colours
750 ---------------
751 0, 2, 8, 10
752 4, 6, 12, 14
753 5, 7, 13, 15
754 1, 3, 9, 11
755
756 These combined bitmaps would be EORed with the existing palette register
757 values in order to perform the value inversion necessary to produce the
758 flashing effect.
759
760 Thus, in the VDU 19 operation, the appropriate inversion value would be
761 calculated for the logical colour, and this value would then be combined with
762 other inversion values in a dedicated memory location corresponding to the
763 colour's group as indicated above. Meanwhile, the palette channel values would
764 be derived from the lower three bits of the specified physical colour and
765 combined with other palette data in dedicated memory locations corresponding
766 to the palette registers.
767
768 Interestingly, although flashing colours on the BBC Micro are controlled by
769 toggling bit 0 of the &FE20 control register location for the Video ULA, the
770 actual colour inversion is done in hardware.
771
772 Enhancement: Palette Definition Lists
773 -------------------------------------
774
775 It can be useful to redefine the palette in order to change the colours
776 available for a particular region of the screen, particularly in modes where
777 the choice of colours is constrained, and if an increased colour depth were
778 available, palette redefinition would be useful to give the illusion of more
779 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
780 by using interrupt-driven timers, but a more efficient approach would involve
781 presenting lists of palette definitions to the ULA so that it can change the
782 palette at a particular display line.
783
784 One might define a palette redefinition list in a region of memory and then
785 communicate its contents to the ULA by writing the address and length of the
786 list, along with the display line at which the palette is to be changed, to
787 ULA registers such that the ULA buffers the list and performs the redefinition
788 at the appropriate time. Throughput/bandwidth considerations might impose
789 restrictions on the practical length of such a list, however.
790
791 Enhancement: Display Synchronisation Interrupts
792 -----------------------------------------------
793
794 When completing each scanline of the display, the ULA could trigger an
795 interrupt. Since this might impact system performance substantially, the
796 feature would probably need to be configurable, and it might be sufficient to
797 have an interrupt only after a certain number of display lines instead.
798 Permitting the CPU to take action after eight lines would allow palette
799 switching and other effects to occur on a character row basis.
800
801 The ULA provides an interrupt at the end of the display period, presumably so
802 that software can schedule updates to the screen, avoid flickering or tearing,
803 and so on. However, some applications might benefit from an interrupt at, or
804 just before, the start of the display period so that palette modifications or
805 similar effects could be scheduled.
806
807 Enhancement: Palette-Free Modes
808 -------------------------------
809
810 Palette-free modes might be defined where bit values directly correspond to
811 the red, green and blue channels, although this would mostly make sense only
812 for modes with depths greater than the standard 4 bits per pixel, and such
813 modes would require more memory than MODE 2 if they were to have an acceptable
814 resolution.
815
816 Enhancement: Display Suspend
817 ----------------------------
818
819 Especially when writing to the screen memory, it could be beneficial to be
820 able to suspend the ULA's access to the memory, instead producing blank values
821 for all screen pixels until a program is ready to reveal the screen. This is
822 different from palette blanking since with a blank palette, the ULA is still
823 reading screen memory and translating its contents into pixel values that end
824 up being blank.
825
826 This function is reminiscent of a capability of the ZX81, albeit necessary on
827 that hardware to reduce the load on the system CPU which was responsible for
828 producing the video output. By allowing display suspend on the Electron, the
829 performance benefit would be derived from giving the CPU full access to the
830 memory bandwidth.
831
832 The region blanking feature mentioned above could be implemented using this
833 enhancement instead of employing palette blanking for the affected lines of
834 the display.
835
836 Enhancement: Memory Filling
837 ---------------------------
838
839 A capability that could be given to an enhanced ULA is that of permitting the
840 ULA to write to screen memory as well being able to read from it. Although
841 such a capability would probably not be useful in conjunction with the
842 existing read operations when producing a screen display, and insufficient
843 bandwidth would exist to do so in high-bandwidth screen modes anyway, the
844 capability could be offered during a display suspend period (as described
845 above), permitting a more efficient mechanism to rapidly fill memory with a
846 predetermined value.
847
848 This capability could also support block filling, where the limits of the
849 filled memory would be defined by the position and size of a screen area,
850 although this would demand the provision of additional registers in the ULA to
851 retain the details of such areas and additional logic to control the fill
852 operation.
853
854 Enhancement: Region Filling
855 ---------------------------
856
857 An alternative to memory writing might involve indicating regions using
858 additional registers or memory where the ULA fills regions of the screen with
859 content instead of reading from memory. Unlike hardware sprites which should
860 realistically provide varied content, region filling could employ single
861 colours or patterns, and one advantage of doing so would be that the ULA need
862 not access memory at all within a particular region.
863
864 Regions would be defined on a row-by-row basis. Instead of reading memory and
865 blitting a direct representation to the screen, the ULA would read region
866 definitions containing a start column, region width and colour details. There
867 might be a certain number of definitions allowed per row, or the ULA might
868 just traverse an ordered list of such definitions with each one indicating the
869 row, start column, region width and colour details.
870
871 One could even compress this information further by requiring only the row,
872 start column and colour details with each subsequent definition terminating
873 the effect of the previous one. However, one would also need to consider the
874 convenience of preparing such definitions and whether efficient access to
875 definitions for a particular row might be desirable. It might also be
876 desirable to avoid having to prepare definitions for "empty" areas of the
877 screen, effectively making the definition of the screen contents employ
878 run-length encoding and employ only colour plus length information.
879
880 One application of region filling is that of simple 2D and 3D shape rendering.
881 Although it is entirely possible to plot such shapes to the screen and have
882 the ULA blit the memory contents to the screen, such operations consume
883 bandwidth both in the initial plotting and in the final transfer to the
884 screen. Region filling would reduce such bandwidth usage substantially.
885
886 This way of representing screen images would make certain kinds of images
887 unfeasible to represent - consider alternating single pixel values which could
888 easily occur in some character bitmaps - even if an internal queue of regions
889 were to be supported such that the ULA could read ahead and buffer such
890 "bandwidth intensive" areas. Thus, the ULA might be better served providing
891 this feature for certain areas of the display only as some kind of special
892 graphics window.
893
894 Enhancement: Hardware Sprites
895 -----------------------------
896
897 An enhanced ULA might provide hardware sprites, but this would be done in an
898 way that is incompatible with the standard ULA, since no &FE*X locations are
899 available for allocation. To keep the facility simple, hardware sprites would
900 have a standard byte width and height.
901
902 The specification of sprites could involve the reservation of 16 locations
903 (for example, &FE20-F) specifying a fixed number of eight sprites, with each
904 location pair referring to the sprite data. By limiting the ULA to dealing
905 with a fixed number of sprites, the work required inside the ULA would be
906 reduced since it would avoid having to deal with arbitrary numbers of sprites.
907
908 The principal limitation on providing hardware sprites is that of having to
909 obtain sprite data, given that the ULA is usually required to retrieve screen
910 data, and given the lack of memory bandwidth available to retrieve sprite data
911 (particularly from multiple sprites supposedly at the same position) and
912 screen data simultaneously. Although the ULA could potentially read sprite
913 data and screen data in alternate memory accesses in screen modes where the
914 bandwidth is not already fully utilised, this would result in a degradation of
915 performance.
916
917 Enhancement: Additional Screen Mode Configurations
918 --------------------------------------------------
919
920 Alternative screen mode configurations could be supported. The ULA has to
921 produce 640 pixel values across the screen, with pixel doubling or quadrupling
922 employed to fill the screen width:
923
924 Screen width Columns Scaling Depth Bytes
925 ------------ ------- ------- ----- -----
926 640 80 x1 1 80
927 320 40 x2 1, 2 40, 80
928 160 20 x4 2, 4 40, 80
929
930 It must also use at most 80 byte-sized memory accesses to provide the
931 information for the display. Given that characters must occupy an 8x8 pixel
932 array, if a configuration featuring anything other than 20, 40 or 80 character
933 columns is to be supported, compromises must be made such as the introduction
934 of blank pixels either between characters (such as occurs between rows in MODE
935 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
936 in MODE 3 and 6). Consider the following configuration:
937
938 Screen width Columns Scaling Depth Bytes Blank
939 ------------ ------- ------- ----- ------ -----
940 208 26 x3 1, 2 26, 52 16
941
942 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
943 colours could be provided, with 16 blank pixel values (out of a total of 640)
944 generated either at the start or end (or split between the start and end) of
945 each scanline.
946
947 Enhancement: Character Attributes
948 ---------------------------------
949
950 The BBC Micro MODE 7 employs something resembling character attributes to
951 support teletext displays, but depends on circuitry providing a character
952 generator. The ZX Spectrum, on the other hand, provides character attributes
953 as a means of colouring bitmapped graphics. Although such a feature is very
954 limiting as the sole means of providing multicolour graphics, in situations
955 where the choice is between low resolution multicolour graphics or high
956 resolution monochrome graphics, character attributes provide a potentially
957 useful compromise.
958
959 For each byte read, the ULA must deliver 8 pixel values (out of a total of
960 640) to the video output, doing so by either emptying its pixel buffer on a
961 pixel per cycle basis, or by multiplying pixels and thus holding them for more
962 than one cycle. For example for a screen mode having 640 pixels in width:
963
964 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
965 Reads: B B
966 Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
967
968 And for a screen mode having 320 pixels in width:
969
970 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
971 Reads: B
972 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
973
974 However, in modes where less than 80 bytes are required to generate the pixel
975 values, an enhanced ULA might be able to read additional bytes between those
976 providing the bitmapped graphics data:
977
978 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
979 Reads: B A
980 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
981
982 These additional bytes could provide colour information for the bitmapped data
983 in the following character column (of 8 pixels). Since it would be desirable
984 to apply attribute data to the first column, the initial 8 cycles might be
985 configured to not produce pixel values.
986
987 For an entire character, attribute data need only be read for the first row of
988 pixels for a character. The subsequent rows would have attribute information
989 applied to them, although this would require the attribute data to be stored
990 in some kind of buffer. Thus, the following access pattern would be observed:
991
992 Cycle: A B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ...
993
994 A whole byte used for colour information for a whole character would result in
995 a choice of 256 colours, and this might be somewhat excessive. By only reading
996 attribute bytes at every other opportunity, a choice of 16 colours could be
997 applied individually to two characters.
998
999 Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
1000 Reads: B A B -
1001 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
1002
1003 Further reductions in attribute data access, offering 4 colours for every
1004 character in a four character block, for example, might also be worth
1005 considering.
1006
1007 Consider the following configurations for screen modes with a colour depth of
1008 1 bit per pixel for bitmap information:
1009
1010 Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
1011 ------------ ------- ------- --------- --------- ------- ------------
1012 320 40 x2 40 40 256 &5300
1013 320 40 x2 40 20 16 &5580 -> &5500
1014 320 40 x2 40 10 4 &56C0 -> &5600
1015 208 26 x3 26 26 256 &62C0 -> &6200
1016 208 26 x3 26 13 16 &6460 -> &6400
1017
1018 Enhancement: MODE 7 Emulation using Character Attributes
1019 --------------------------------------------------------
1020
1021 If the scheme of applying attributes to character regions were employed to
1022 emulate MODE 7, in conjunction with the MODE 6 display technique, the
1023 following configuration would be required:
1024
1025 Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
1026 ------------ ------- ---- --------- --------- ------- ------------
1027 320 40 25 40 20 16 &5ECC -> &5E00
1028 320 40 25 40 10 4 &5FC6 -> &5F00
1029
1030 Although this requires much more memory than MODE 7 (8500 bytes versus MODE
1031 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
1032 at least make a limited 40-column multicolour mode available as a substitute
1033 for MODE 7.
1034
1035 Enhancement: High Resolution Graphics
1036 -------------------------------------
1037
1038 Screen modes with higher resolutions and larger colour depths might be
1039 possible, but this would in most cases involve the allocation of more screen
1040 memory, and the ULA would probably then be obliged to page in such memory for
1041 the CPU to be able to sensibly access it all.
1042
1043 Enhancement: Genlock Support
1044 ----------------------------
1045
1046 The ULA generates a video signal in conjunction with circuitry producing the
1047 output features necessary for the correct display of the screen image.
1048 However, it appears that the ULA drives the video synchronisation mechanism
1049 instead of reacting to an existing signal. Genlock support might be possible
1050 if the ULA were made to be responsive to such external signals, resetting its
1051 address generators upon receiving synchronisation events.
1052
1053 Enhancement: Improved Sound
1054 ---------------------------
1055
1056 The standard ULA reserves &FE*6 for sound generation and cassette input/output
1057 (with bits 1 and 2 of &FE*7 being used to select either sound generation or
1058 cassette I/O), thus making it impossible to support multiple channels within
1059 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
1060 and an enhanced ULA could adopt this interface.
1061
1062 The BBC Micro uses the SN76489 chip to produce sound, and the entire
1063 functionality of this chip could be emulated for enhanced sound, with a subset
1064 of the functionality exposed via the &FE*6 interface.
1065
1066 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
1067 See: http://www.smspower.org/Development/SN76489
1068
1069 Enhancement: Waveform Upload
1070 ----------------------------
1071
1072 As with a hardware sprite function, waveforms could be uploaded or referenced
1073 using locations as registers referencing memory regions.
1074
1075 Enhancement: Sound Input/Output
1076 -------------------------------
1077
1078 Since the ULA already controls audio input/output for cassette-based data, it
1079 would have been interesting to entertain the idea of sampling and output of
1080 sounds through the cassette interface. However, a significant amount of
1081 circuitry is employed to process the input signal for use by the ULA and to
1082 process the output signal for recording.
1083
1084 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw_03.htm#3.11
1085
1086 Enhancement: BBC ULA Compatibility
1087 ----------------------------------
1088
1089 Although some new ULA functions could be defined in a way that is also
1090 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
1091 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
1092 map, but controls various functions specific to the 6845 video controller;
1093 &FE08-F is reserved for the serial controller. It therefore becomes possible
1094 to disregard compatibility where compatibility is already disregarded for a
1095 particular area of functionality.
1096
1097 &FE20-F maps to video ULA functionality on the BBC Micro which provides
1098 control over the palette (using address &FE21, compared to &FE07-F on the
1099 Electron) and other system-specific functions. Since the location usage is
1100 generally incompatible, this region could be reused for other purposes.
1101
1102 Enhancement: Increased RAM, ULA and CPU Performance
1103 ---------------------------------------------------
1104
1105 More modern implementations of the hardware might feature faster RAM coupled
1106 with an increased ULA clock frequency in order to increase the bandwidth
1107 available to the ULA and to the CPU in situations where the ULA is not needed
1108 to perform work. A ULA employing a 32MHz clock would be able to complete the
1109 retrieval of a byte from RAM in only 250ns and thus be able to enable the CPU
1110 to access the RAM for the following 250ns even in display modes requiring the
1111 retrieval of a byte for the display every 500ns. The CPU could, subject to
1112 timing issues, run at 2MHz even in MODE 0, 1 and 2.
1113
1114 A scheme such as that described above would have a similar effect to the
1115 scheme employed in the BBC Micro, although the latter made use of RAM with a
1116 wider bandwidth in order to complete memory transfers within 250ns and thus
1117 permit the CPU to run continuously at 2MHz.
1118
1119 Higher bandwidth could potentially be used to implement exotic features such
1120 as RAM-resident hardware sprites or indeed any feature demanding RAM access
1121 concurrent with the production of the display image.
1122
1123 Enhancement: Multiple CPU Stacks and Zero Pages
1124 -----------------------------------------------
1125
1126 The 6502 maintains a stack for subroutine calls and register storage in page
1127 &01. Although the stack register can be manipulated using the TSX and TXS
1128 instructions, thereby permitting the maintenance of multiple stack regions and
1129 thus the potential coexistence of multiple programs each using a separate
1130 region, only programs that make little use of the stack (perhaps avoiding
1131 deeply-nested subroutine invocations and significant register storage) would
1132 be able to coexist without overwriting each other's stacks.
1133
1134 One way that this issue could be alleviated would involve the provision of a
1135 facility to redirect accesses to page &01 to other areas of memory. The ULA
1136 would provide a register that defines a physical page for the use of the CPU's
1137 "logical" page &01, and upon any access to page &01 by the CPU, the ULA would
1138 change the asserted address lines to redirect the access to the appropriate
1139 physical region.
1140
1141 By providing an 8-bit register, mapping to the most significant byte (MSB) of
1142 a 16-bit address, the ULA could then replace any MSB equal to &01 with the
1143 register value before the access is made. Where multiple programs coexist,
1144 upon switching programs, the register would be updated to point the ULA to the
1145 appropriate stack location, thus providing a simple memory management unit
1146 (MMU) capability.
1147
1148 In a similar fashion, zero page accesses could also be redirected so that code
1149 could run from sideways RAM and have zero page operations redirected to "upper
1150 memory" - for example, to page &BE (with stack accesses redirected to page
1151 &BF, perhaps) - thereby permitting most CPU operations to occur without
1152 inadvertent accesses to "lower memory" (the RAM) which would risk stalling the
1153 CPU as it contends with the ULA for memory access.
1154
1155 Such facilities could also be provided by a separate circuit between the CPU
1156 and ULA in a fashion similar to that employed by a "turbo" board, but unlike
1157 such boards, no additional RAM would be provided: all memory accesses would
1158 occur as normal through the ULA, albeit redirected when configured
1159 appropriately.
1160
1161 ULA Pin Functions
1162 -----------------
1163
1164 The functions of the ULA pins are described in the Electron Service Manual. Of
1165 interest to video processing are the following:
1166
1167 CSYNC (low during horizontal or vertical synchronisation periods, high
1168 otherwise)
1169
1170 HS (low during horizontal synchronisation periods, high otherwise)
1171
1172 RED, GREEN, BLUE (pixel colour outputs)
1173
1174 CLOCK IN (a 16MHz clock input, 4V peak to peak)
1175
1176 PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
1177
1178 More general memory access pins:
1179
1180 RAM0...RAM3 (data lines to/from the RAM)
1181
1182 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
1183
1184 RAS (row address strobe setting the row address on a negative edge - see the
1185 timing notes)
1186
1187 CAS (column address strobe setting the column address on a negative edge -
1188 see the timing notes)
1189
1190 WE (sets write enable with logic 0, read with logic 1)
1191
1192 ROM (select data access from ROM)
1193
1194 CPU-oriented memory access pins:
1195
1196 A0...A15 (CPU address lines)
1197
1198 PD0...PD7 (CPU data lines)
1199
1200 R/W (indicates CPU write with logic 0, CPU read with logic 1)
1201
1202 Interrupt-related pins:
1203
1204 NMI (CPU request for uninterrupted 1MHz access to memory)
1205
1206 IRQ (signal event to CPU)
1207
1208 POR (power-on reset, resetting the ULA on a positive edge and asserting the
1209 CPU's RST pin)
1210
1211 RST (master reset for the CPU signalled on power-up and by the Break key)
1212
1213 Keyboard-related pins:
1214
1215 KBD0...KBD3 (keyboard inputs)
1216
1217 CAPS LOCK (control status LED)
1218
1219 Sound-related pins:
1220
1221 SOUND O/P (sound output using internal oscillator)
1222
1223 Cassette-related pins:
1224
1225 CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
1226
1227 CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
1228
1229 CAS RC (detect high tone)
1230
1231 CAS MO (motor relay output)
1232
1233 ÷13 IN (~1200 baud clock input)
1234
1235 ULA Socket
1236 ----------
1237
1238 The socket used for the ULA is a 3M/TexTool 268-5400 68-pin socket.
1239
1240 References
1241 ----------
1242
1243 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw.htm
1244
1245 About this Document
1246 -------------------
1247
1248 The most recent version of this document and accompanying distribution should
1249 be available from the following location:
1250
1251 http://hgweb.boddie.org.uk/ULA
1252
1253 Copyright and licence information can be found in the docs directory of this
1254 distribution - see docs/COPYING.txt for more information.