1 The Acorn Electron ULA
2 ======================
3
4 Principal Design and Feature Constraints
5 ----------------------------------------
6
7 The features of the ULA are limited by the amount of time and resources that
8 can be allocated to each activity necessary to support such features given the
9 fundamental obligations of the unit. Maintaining a screen display based on the
10 contents of RAM itself requires the ULA to have exclusive access to such
11 hardware resources for a significant period of time. Whilst other elements of
12 the ULA can in principle run in parallel with this activity, they cannot also
13 access the RAM. Consequently, other features that might use the RAM must
14 accept a reduced allocation of that resource in comparison to a hypothetical
15 architecture where concurrent RAM access is possible.
16
17 Thus, the principal constraint for many features is bandwidth. The duration of
18 access to hardware resources is one aspect of this; the rate at which such
19 resources can be accessed is another. For example, the RAM is not fast enough
20 to support access more frequently than one byte per 2MHz cycle, and for screen
21 modes involving 80 bytes of screen data per scanline, there are no free cycles
22 for anything other than the production of pixel output during the active
23 scanline periods.
24
25 Timing
26 ------
27
28 According to 15.3.2 in the Advanced User Guide, there are 312 scanlines, 256
29 of which are used to generate pixel data. At 50Hz, this means that 128 cycles
30 are spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
31 312 ~= 128 cycles). This is consistent with the observation that each scanline
32 requires at most 80 bytes of data, and that the ULA is apparently busy for 40
33 out of 64 microseconds in each scanline.
34
35 (In fact, since the ULA is seeking to provide an image for an interlaced
36 625-line display, there are in fact two "fields" involved, one providing 312
37 scanlines and one providing 313 scanlines. See below for a description of the
38 video system.)
39
40 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
41 each providing two bits of each byte) using two cycles within the 500ns period
42 of the 2MHz clock to complete each access operation. Since the CPU and ULA
43 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
44 effectively run at 1MHz (since every other 500ns period involves the ULA
45 accessing RAM). The CPU is driven by an external clock (IC8) whose 16MHz
46 frequency is divided by the ULA (IC1) depending on the screen mode in use.
47
48 Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
49 patterns corresponding to 16MHz cycles are required:
50
51 Time (ns): 0-------------- 500------------ ...
52 2 MHz cycle: 0 1 ...
53 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
54 ~RAS: 0 1 0 1 ...
55 ~CAS: 0 1 0 1 0 1 0 1 ...
56 A B C A B C ...
57 F S F S ...
58 a b c a b c ...
59
60 Here, "A" and "B" respectively indicate the row and first column addresses
61 being latched into the RAM (on a negative edge for ~RAS and ~CAS
62 respectively), and "C" indicates the second column address being latched into
63 the RAM. Presumably, the first and second half-bytes can be read at "F" and
64 "S" respectively, and the row and column addresses must be made available at
65 "a" and "b" (and "c") respectively at the latest.
66
67 The TM4164EC4-15 has a row address access time of 150ns (maximum) and a column
68 address access time of 90ns (maximum), which appears to mean that
69 approximately two 16MHz cycles after the row address is latched, and one and a
70 half cycles after the column address is latched, the data becomes available.
71
72 Note that the Service Manual refers to the negative edge of RAS and CAS, but
73 the datasheet for the similar TM4164EC4 product shows latching on the negative
74 edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
75 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
76 "page mode" provides the appropriate behaviour for that particular product.
77
78 The CPU, when accessing the RAM alone, apparently does not make use of the
79 vacated "slot" that the ULA would otherwise use (when interleaving accesses in
80 MODE 4, 5 and 6). It only employs a full 2MHz access frequency to memory when
81 accessing ROM (and potentially sideways RAM).
82
83 See: Acorn Electron Advanced User Guide
84 See: Acorn Electron Service Manual
85 http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
86 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
87 See: http://stardot.org.uk/forums/viewtopic.php?p=120438#p120438
88
89 Bandwidth Figures
90 -----------------
91
92 Using an observation of 128 2MHz cycles per scanline, 256 active lines and 312
93 total lines, with 80 cycles occurring in the active periods of display
94 scanlines, the following bandwidth calculations can be performed:
95
96 Total theoretical maximum:
97 128 cycles * 312 lines
98 = 39936 bytes
99
100 MODE 0, 1, 2:
101 ULA: 80 cycles * 256 lines
102 = 20480 bytes
103 CPU: 48 cycles / 2 * 256 lines
104 + 128 cycles / 2 * (312 - 256) lines
105 = 9728 bytes
106
107 MODE 3:
108 ULA: 80 cycles * 24 rows * 8 lines
109 = 15360 bytes
110 CPU: 48 cycles / 2 * 24 rows * 8 lines
111 + 128 cycles / 2 * (312 - (24 rows * 8 lines))
112 = 12288 bytes
113
114 MODE 4, 5:
115 ULA: 40 cycles * 256 lines
116 = 10240 bytes
117 CPU: (40 cycles + 48 cycles / 2) * 256 lines
118 + 128 cycles / 2 * (312 - 256) lines
119 = 19968 bytes
120
121 MODE 6:
122 ULA: 40 cycles * 24 rows * 8 lines
123 = 7680 bytes
124 CPU: (40 cycles + 48 cycles / 2) * 24 rows * 8 lines
125 + 128 cycles / 2 * (312 - (24 rows * 8 lines))
126 = 19968 bytes
127
128 Here, the division of 2 for CPU accesses is performed to indicate that the CPU
129 only uses every other access opportunity even in uncontended periods. See the
130 2MHz RAM Access enhancement below for bandwidth calculations that consider
131 this limitation removed.
132
133 Video Timing
134 ------------
135
136 According to 8.7 in the Service Manual, and the PAL Wikipedia page,
137 approximately 4.7µs is used for the sync pulse, 5.7µs for the "back porch"
138 (including the "colour burst"), and 1.65µs for the "front porch", totalling
139 12.05µs and thus leaving 51.95µs for the active video signal for each
140 scanline. As the Service Manual suggests in the oscilloscope traces, the
141 display information is transmitted more or less centred within the active
142 video period since the ULA will only be providing pixel data for 40µs in each
143 scanline.
144
145 Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that
146 each scanline can be divided into 1024 cycles, although only 640 at most are
147 actively used to provide pixel data. Pixel data production should only occur
148 within a certain period on each scanline, approximately 262 cycles after the
149 start of hsync:
150
151 active video period = 51.95µs
152 pixel data period = 40µs
153 total silent period = 51.95µs - 40µs = 11.95µs
154 silent periods (before and after) = 11.95µs / 2 = 5.975µs
155 hsync and back porch period = 4.7µs + 5.7µs = 10.4µs
156 time before pixel data period = 10.4µs + 5.975µs = 16.375µs
157 pixel data period start cycle = 16.375µs / 62.5ns = 262
158
159 By choosing a number divisible by 8, the RAM access mechanism can be
160 synchronised with the pixel production. Thus, 256 is a more appropriate start
161 cycle, where the HS (horizontal sync) signal corresponding to the 4µs sync
162 pulse (or "normal sync" pulse as described by the "PAL TV timing and voltages"
163 document) occurs at cycle 0.
164
165 To summarise:
166
167 HS signal starts at cycle 0 on each horizontal scanline
168 HS signal ends approximately 4µs later at cycle 64
169 Pixel data starts approximately 12µs later at cycle 256
170
171 "Re: Electron Memory Contention" provides measurements that appear consistent
172 with these calculations.
173
174 The "vertical blanking period", meaning the period before picture information
175 in each field is 25 lines out of 312 (or 313) and thus lasts for 1.6ms. Of
176 this, 2.5 lines occur before the vsync (field sync) which also lasts for 2.5
177 lines. Thus, the first visible scanline on the first field of a frame occurs
178 half way through the 23rd scanline period measured from the start of vsync
179 (indicated by "V" in the diagrams below):
180
181 10 20 23
182 Line in frame: 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
183 Line from 1: 0 22 3
184 Line on screen: .:::::VVVVV::::: 12233445566
185 |_________________________________________________|
186 25 line vertical blanking period
187
188 In the second field of a frame, the first visible scanline coincides with the
189 24th scanline period measured from the start of line 313 in the frame:
190
191 310 336
192 Line in frame: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
193 Line from 313: 0 23 4
194 Line on screen: 88:::::VVVVV:::: 11223344
195 288 | |
196 |_________________________________________________|
197 25 line vertical blanking period
198
199 In order to consider only full lines, we might consider the start of each
200 frame to occur 23 lines after the start of vsync.
201
202 Again, it is likely that pixel data production should only occur on scanlines
203 within a certain period on each frame. The "625/50" document indicates that
204 only a certain region is "safe" to use, suggesting a vertically centred region
205 with approximately 15 blank lines above and below the picture. However, the
206 "PAL TV timing and voltages" document suggests 28 blank lines above and below
207 the picture. This would centre the 256 lines within the 312 lines of each
208 field and thus provide a start of picture approximately 5.5 or 5 lines after
209 the end of the blanking period or 28 or 27.5 lines after the start of vsync.
210
211 To summarise:
212
213 CSYNC signal starts at cycle 0
214 CSYNC signal ends approximately 160µs (2.5 lines) later at cycle 2560
215 Start of line occurs approximately 1632µs (5.5 lines) later at cycle 28672
216
217 See: http://en.wikipedia.org/wiki/PAL
218 See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal
219 See: The 625/50 PAL Video Signal and TV Compatible Graphics Modes
220 http://lipas.uwasa.fi/~f76998/video/modes/
221 See: PAL TV timing and voltages
222 http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
223 See: Line Standards
224 http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html
225 See: Horizontal Blanking Interval of 405-, 525-, 625- and 819-Line Standards
226 http://www.pembers.freeserve.co.uk/World-TV-Standards/HBI.pdf
227 See: Re: Electron Memory Contention
228 http://www.stardot.org.uk/forums/viewtopic.php?p=134109#p134109
229
230 RAM Integrated Circuits
231 -----------------------
232
233 Unicorn Electronics appears to offer 4164 RAM chips (as well as 6502 series
234 CPUs such as the 6502, 6502A, 6502B and 65C02). These 4164 devices are
235 available in 100ns (4164-100), 120ns (4164-120) and 150ns (4164-150) variants,
236 have 16 pins and address 65536 bits through a 1-bit wide channel. Similarly,
237 ByteDelight.com sell 4164 devices primarily for the ZX Spectrum.
238
239 The documentation for the Electron mentions 4164-15 RAM chips for IC4-7, and
240 the Samsung-produced KM41464 series is apparently equivalent to the Texas
241 Instruments 4164 chips presumably used in the Electron.
242
243 The TM4164EC4 series combines 4 64K x 1b units into a single package and
244 appears similar to the TM4164EA4 featured on the Electron's circuit diagram
245 (in the Advanced User Guide but not the Service Manual), and it also has 22
246 pins providing 3 additional inputs and 3 additional outputs over the 16 pins
247 of the individual 4164-15 modules, presumably allowing concurrent access to
248 the packaged memory units.
249
250 As far as currently available replacements are concerned, the NTE4164 is a
251 potential candidate: according to the Vetco Electronics entry, it is
252 supposedly a replacement for the TMS4164-15 amongst many other parts. Similar
253 parts include the NTE2164 and the NTE6664, both of which appear to have
254 largely the same performance and connection characteristics. Meanwhile, the
255 NTE21256 appears to be a 16-pin replacement with four times the capacity that
256 maintains the single data input and output pins. Using the NTE21256 as a
257 replacement for all ICs combined would be difficult because of the single bit
258 output.
259
260 Another device equivalent to the 4164-15 appears to be available under the
261 code 41662 from Jameco Electronics as the Siemens HYB 4164-2. The Jameco Web
262 site lists data sheets for other devices on the same page, but these are
263 different and actually appear to be provided under the 41574 product code (but
264 are listed under 41464-10) and appear to be replacements for the TM4164EC4:
265 the Samsung KM41464A-15 and NEC µPD41464 employ 18 pins, eliminating 4 pins by
266 employing 4 pins for both input and output.
267
268 Pins I/O pins Row access Column access
269 ---- -------- ---------- -------------
270 TM4164EC4 22 4 + 4 150ns (15) 90ns (15)
271 KM41464AP 18 4 150ns (15) 75ns (15)
272 NTE21256 16 1 + 1 150ns 75ns
273 HYB 4164-2 16 1 + 1 150ns 100ns
274 µPD41464 18 4 120ns (12) 60ns (12)
275
276 See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module
277 http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
278 See: Dynamic RAMS
279 http://www.unicornelectronics.com/IC/DYNAMIC.html
280 See: New old stock 8x 4164 chips
281 http://www.bytedelight.com/?product=8x-4164-chips-new-old-stock
282 See: KM4164B 64K x 1 Bit Dynamic RAM with Page Mode
283 http://images.ihscontent.net/vipimages/VipMasterIC/IC/SAMS/SAMSD020/SAMSD020-45.pdf
284 See: NTE2164 Integrated Circuit 65,536 X 1 Bit Dynamic Random Access Memory
285 http://www.vetco.net/catalog/product_info.php?products_id=2806
286 See: NTE4164 - IC-NMOS 64K DRAM 150NS
287 http://www.vetco.net/catalog/product_info.php?products_id=3680
288 See: NTE21256 - IC-256K DRAM 150NS
289 http://www.vetco.net/catalog/product_info.php?products_id=2799
290 See: NTE21256 262,144-Bit Dynamic Random Access Memory (DRAM)
291 http://www.nteinc.com/specs/21000to21999/pdf/nte21256.pdf
292 See: NTE6664 - IC-MOS 64K DRAM 150NS
293 http://www.vetco.net/catalog/product_info.php?products_id=5213
294 See: NTE6664 Integrated Circuit 64K-Bit Dynamic RAM
295 http://www.nteinc.com/specs/6600to6699/pdf/nte6664.pdf
296 See: 4164-150: MAJOR BRANDS
297 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41662_-1
298 See: HYB 4164-1, HYB 4164-2, HYB 4164-3 65,536-Bit Dynamic Random Access Memory (RAM)
299 http://www.jameco.com/Jameco/Products/ProdDS/41662SIEMENS.pdf
300 See: KM41464A NMOS DRAM 64K x 4 Bit Dynamic RAM with Page Mode
301 http://www.jameco.com/Jameco/Products/ProdDS/41662SAM.pdf
302 See: NEC µ41464 65,536 x 4-Bit Dynamic NMOS RAM
303 http://www.jameco.com/Jameco/Products/ProdDS/41662NEC.pdf
304 See: 41464-10: MAJOR BRANDS
305 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41574_-1
306
307 Interrupts
308 ----------
309
310 The ULA generates IRQs (maskable interrupts) according to certain conditions
311 and these conditions are controlled by location &FE00:
312
313 * Vertical sync (bottom of displayed screen)
314 * 50MHz real time clock
315 * Transmit data empty
316 * Receive data full
317 * High tone detect
318
319 The ULA is also used to clear interrupt conditions through location &FE05. Of
320 particular significance is bit 7, which must be set if an NMI (non-maskable
321 interrupt) has occurred and has thus suspended ULA access to memory, restoring
322 the normal function of the ULA.
323
324 ROM Paging
325 ----------
326
327 Accessing different ROMs involves bits 0 to 3 of &FE05. Some special ROM
328 mappings exist:
329
330 8 keyboard
331 9 keyboard (duplicate)
332 10 BASIC ROM
333 11 BASIC ROM (duplicate)
334
335 Paging in a ROM involves the following procedure:
336
337 1. Assert ROM page enable (bit 3) together with a ROM number n in bits 0 to
338 2, corresponding to ROM number 8+n, such that one of ROMs 12 to 15 is
339 selected.
340 2. Where a ROM numbered from 0 to 7 is to be selected, set bit 3 to zero
341 whilst writing the desired ROM number n in bits 0 to 2.
342
343 See: http://stardot.org.uk/forums/viewtopic.php?p=136686#p136686
344
345 Shadow/Expanded Memory
346 ----------------------
347
348 The Electron exposes all sixteen address lines and all eight data lines
349 through the expansion bus. Using such lines, it is possible to provide
350 additional memory - typically sideways ROM and RAM - on expansion cards and
351 through cartridges, although the official cartridge specification provides
352 fewer address lines and only seeks to provide access to memory in 16K units.
353
354 Various modifications and upgrades were developed to offer "turbo"
355 capabilities to the Electron, permitting the CPU to access a separate 8K of
356 RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
357 the ULA through additional logic. However, an enhanced ULA might support
358 independent CPU access to memory over the expansion bus by allowing itself to
359 be discharged from providing access to memory, potentially for a range of
360 addresses, and for the CPU to communicate with external memory uninterrupted.
361
362 Sideways RAM/ROM and Upper Memory Access
363 ----------------------------------------
364
365 Although the ULA controls the CPU clock, effectively slowing or stopping the
366 CPU when the ULA needs to access screen memory, it is apparently able to allow
367 the CPU to access addresses of &8000 and above - the upper region of memory -
368 at 2MHz independently of any access to RAM that the ULA might be performing,
369 only blocking the CPU if it attempts to access addresses of &7FFF and below
370 during any ULA memory access - the lower region of memory - by stopping or
371 stalling its clock.
372
373 Thus, the ULA remains aware of the level of the A15 line, only inhibiting the
374 CPU clock if the line goes low, when the CPU is attempting to access the lower
375 region of memory.
376
377 Hardware Scrolling (and Enhancement)
378 ------------------------------------
379
380 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
381 the least significant 5 bits being zero, thus limiting the scrolling
382 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
383 using the same layout of these addresses.
384
385 |--&FE02--------------| |--&FE03--------------|
386 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
387
388 XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
389
390 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
391 memory to pixel locations is character oriented. A change in 8 bytes would
392 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
393 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
394 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
395 Guide).
396
397 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
398 of changing the screen address by 2 bytes is the change in the number of lines
399 from the initial and final character rows that need reading by the ULA, which
400 would need to maintain this state information (although this is a relatively
401 trivial change). Another pitfall is the complication that might be introduced
402 to software writing bitmaps of character height to the screen.
403
404 See: http://pastraiser.com/computers/acornelectron/acornelectron.html
405
406 Enhancement: Mode Layouts
407 -------------------------
408
409 Merely changing the screen memory mappings in order to have Archimedes-style
410 row-oriented screen addresses (instead of character-oriented addresses) could
411 be done for the existing modes, but this might not be sufficiently beneficial,
412 especially since accessing regions of the screen would involve incrementing
413 pointers by amounts that are inconvenient on an 8-bit CPU.
414
415 However, instead of using a Archimedes-style mapping, column-oriented screen
416 addresses could be more feasibly employed: incrementing the address would
417 reference the vertical screen location below the currently-referenced location
418 (just as occurs within characters using the existing ULA); instead of
419 returning to the top of the character row and referencing the next horizontal
420 location after eight bytes, the address would reference the next character row
421 and continue to reference locations downwards over the height of the screen
422 until reaching the bottom; at the bottom, the next location would be the next
423 horizontal location at the top of the screen.
424
425 In other words, the memory layout for the screen would resemble the following
426 (for MODE 2):
427
428 &3000 &3100 ... &7F00
429 &3001 &3101
430 ... ...
431 &3007
432 &3008
433 ...
434 ... ...
435 &30FF ... &7FFF
436
437 Since there are 256 pixel rows, each column of locations would be addressable
438 using the low byte of the address. Meanwhile, the high byte would be
439 incremented to address different columns. Thus, addressing screen locations
440 would become a lot more convenient and potentially much more efficient for
441 certain kinds of graphical output.
442
443 One potential complication with this simplified addressing scheme arises with
444 hardware scrolling. Vertical hardware scrolling by one pixel row (not supported
445 with the existing ULA) would be achieved by incrementing or decrementing the
446 screen start address; by one character row, it would involve adding or
447 subtracting 8. However, the ULA only supports multiples of 64 when changing the
448 screen start address. Thus, if such a scheme were to be adopted, three
449 additional bits would need to be supported in the screen start register (see
450 "Hardware Scrolling (and Enhancement)" for more details). However, horizontal
451 scrolling would be much improved even under the severe constraints of the
452 existing ULA: only adjustments of 256 to the screen start address would be
453 required to produce single-location scrolling of as few as two pixels in MODE 2
454 (four pixels in MODEs 1 and 5, eight pixels otherwise).
455
456 More disruptive is the effect of this alternative layout on software.
457 Presumably, compatibility with the BBC Micro was the primary goal of the
458 Electron's hardware design. With the character-oriented screen layout in
459 place, system software (and application software accessing the screen
460 directly) would be relying on this layout to run on the Electron with little
461 or no modification. Although it might have been possible to change the system
462 software to use this column-oriented layout instead, this would have incurred
463 a development cost and caused additional work porting things like games to the
464 Electron. Moreover, a separate branch of the software from that supporting the
465 BBC Micro and closer derivatives would then have needed maintaining.
466
467 The decision to use the character-oriented layout in the BBC Micro may have
468 been related to the choice of circuitry and to facilitate a convenient
469 hardware implementation, and by the time the Electron was planned, it was too
470 late to do anything about this somewhat unfortunate choice.
471
472 Enhancement: The Missing MODE 4
473 -------------------------------
474
475 The Electron inherits its screen mode selection from the BBC Micro, where MODE
476 3 is a text version of MODE 0, and where MODE 6 is a text version of MODE 4.
477 Neither MODE 3 nor MODE 6 is a genuine character-based text mode like MODE 7,
478 however, and they are merely implemented by skipping two scanlines in every
479 ten after the eight required to produce a character line. Thus, such modes
480 provide a 24-row display.
481
482 In principle, nothing prevents this "text mode" effect being applied to other
483 modes. The 20-column modes are not well-suited to displaying text, which
484 leaves MODE 1 which, unlike MODEs 3 and 6, can display 4 colours rather than
485 2. Although the need for a non-monochrome 40-column text mode is addressed by
486 MODE 7 on the BBC Micro, the Electron lacks such a mode.
487
488 If the 4-colour, 24-row variant of MODE 1 were to be provided, logically it
489 would occupy MODE 4 instead of the current MODE 4:
490
491 Screen mode Size (kilobytes) Colours Rows Resolution
492 ----------- ---------------- ------- ---- ----------
493 0 20 2 32 640x256
494 1 20 4 32 320x256
495 2 20 16 32 160x256
496 3 16 2 24 640x256
497 4 (new) 16 4 24 320x256
498 4 (old) 10 2 32 320x256
499 5 10 4 32 160x256
500 6 8 2 24 320x256
501
502 Thus, for increasing mode numbers, the size of each mode would be the same or
503 less than the preceding mode.
504
505 Enhancement: 2MHz RAM Access
506 ----------------------------
507
508 Given that the CPU and ULA both access RAM at 2MHz, but given that the CPU
509 when not competing with the ULA only accesses RAM every other 2MHz cycle (as
510 if the ULA still needed to access the RAM), one useful enhancement would be a
511 mechanism to let the CPU take over the ULA cycles outside the ULA's period of
512 activity comparable to the way the ULA takes over the CPU cycles in MODE 0 to
513 3.
514
515 Thus, the RAM access cycles would resemble the following in MODE 0 to 3:
516
517 Upon a transition from display cycles: UUUUCCCC (instead of UUUUC_C_)
518 On a non-display line: CCCCCCCC (instead of C_C_C_C_)
519
520 In MODE 4 to 6:
521
522 Upon a transition from display cycles: CUCUCCCC (instead of CUCUC_C_)
523 On a non-display line: CCCCCCCC (instead of C_C_C_C_)
524
525 This would improve CPU bandwidth as follows:
526
527 Standard ULA Enhanced ULA
528 MODE 0, 1, 2 9728 bytes 19456 bytes
529 MODE 3 12288 bytes 24576 bytes
530 MODE 4, 5 19968 bytes 29696 bytes
531 MODE 6 19968 bytes 32256 bytes
532
533 With such an enhancement, MODE 0 to 3 experience a doubling of CPU bandwidth
534 because all access opportunities to RAM are doubled. Meanwhile, in the other
535 modes, some CPU accesses occur alongside ULA accesses and thus cannot be
536 doubled, but the CPU bandwidth increase is still significant.
537
538 Enhancement: Region Blanking
539 ----------------------------
540
541 The problem of permitting character-oriented blitting in programs whilst
542 scrolling the screen by sub-character amounts could be mitigated by permitting
543 a region of the display to be blank, such as the final lines of the display.
544 Consider the following vertical scrolling by 2 bytes that would cause an
545 initial character row of 6 lines and a final character row of 2 lines:
546
547 6 lines - initial, partial character row
548 248 lines - 31 complete rows
549 2 lines - final, partial character row
550
551 If a routine were in use that wrote 8 line bitmaps to the partial character
552 row now split in two, it would be advisable to hide one of the regions in
553 order to prevent content appearing in the wrong place on screen (such as
554 content meant to appear at the top "leaking" onto the bottom). Blanking 6
555 lines would be sufficient, as can be seen from the following cases.
556
557 Scrolling up by 2 lines:
558
559 6 lines - initial, partial character row
560 240 lines - 30 complete rows
561 4 lines - part of 1 complete row
562 -----------------------------------------------------------------
563 4 lines - part of 1 complete row (hidden to maintain 250 lines)
564 2 lines - final, partial character row (hidden)
565
566 Scrolling down by 2 lines:
567
568 2 lines - initial, partial character row
569 248 lines - 31 complete rows
570 ----------------------------------------------------------
571 6 lines - final, partial character row (hidden)
572
573 Thus, in this case, region blanking would impose a 250 line display with the
574 bottom 6 lines blank.
575
576 See the description of the display suspend enhancement for a more efficient
577 way of blanking lines than merely blanking the palette whilst allowing the CPU
578 to perform useful work during the blanking period.
579
580 To control the blanking or suspending of lines at the top and bottom of the
581 display, a memory location could be dedicated to the task: the upper 4 bits
582 could define a blanking region of up to 16 lines at the top of the screen,
583 whereas the lower 4 bits could define such a region at the bottom of the
584 screen. If more lines were required, two locations could be employed, allowing
585 the top and bottom regions to occupy the entire screen.
586
587 Enhancement: Screen Height Adjustment
588 -------------------------------------
589
590 The height of the screen could be configurable in order to reduce screen
591 memory consumption. This is not quite done in MODE 3 and 6 since the start of
592 the screen appears to be rounded down to the nearest page, but by reducing the
593 height by amounts more than a page, savings would be possible. For example:
594
595 Screen width Depth Height Bytes per line Saving in bytes Start address
596 ------------ ----- ------ -------------- --------------- -------------
597 640 1 252 80 320 &3140 -> &3100
598 640 1 248 80 640 &3280 -> &3200
599 320 1 240 40 640 &5A80 -> &5A00
600 320 2 240 80 1280 &3500
601
602 Screen Mode Selection
603 ---------------------
604
605 Bits 3, 4 and 5 of address &FE*7 control the selected screen mode. For a wider
606 range of modes, the other bits of &FE*7 (related to sound, cassette
607 input/output and the Caps Lock LED) would need to be reassigned and bit 0
608 potentially being made available for use.
609
610 Enhancement: Palette Definition
611 -------------------------------
612
613 Since all memory accesses go via the ULA, an enhanced ULA could employ more
614 specific addresses than &FE*X to perform enhanced functions. For example, the
615 palette control is done using &FE*8-F and merely involves selecting predefined
616 colours, whereas an enhanced ULA could support the redefinition of all 16
617 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
618 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
619 specifications similar to those used on the Archimedes.
620
621 The principal limitation here is actually the hardware: the Electron has only
622 a single output line for each of the red, green and blue channels, and if
623 those outputs are strictly digital and can only be set to a "high" and "low"
624 value, then only the existing eight colours are possible. If a modern ULA were
625 able to output analogue values (or values at well-defined points between the
626 high and low values, such as the half-on value supported by the Amstrad CPC
627 series), it would still need to be assessed whether the circuitry could
628 successfully handle and propagate such values. Various sources indicate that
629 only "TTL levels" are supported by the RGB output circuit, and since there are
630 74LS08 AND logic gates involved in the RGB component outputs from the ULA, it
631 is likely that the ULA is expected to provide only "high" or "low" values.
632
633 Short of adding extra outputs from the ULA (either additional red, green and
634 blue outputs or a combined intensity output), another approach might involve
635 some kind of modulation where an output value might be encoded in multiple
636 pulses at a higher frequency than the pixel frequency. However, this would
637 demand additional circuitry outside the ULA, and component RGB monitors would
638 probably not be able to take advantage of this feature; only UHF and composite
639 video devices (the latter with the composite video colour support enabled on
640 the Electron's circuit board) would potentially benefit.
641
642 Flashing Colours
643 ----------------
644
645 According to the Advanced User Guide, "The cursor and flashing colours are
646 entirely generated in software: This means that all of the logical to physical
647 colour map must be changed to cause colours to flash." This appears to suggest
648 that the palette registers must be updated upon the flash counter - read and
649 written by OSBYTE &C1 (193) - reaching zero and that some way of changing the
650 colour pairs to be any combination of colours might be possible, instead of
651 having colour complements as pairs.
652
653 It is conceivable that the interrupt code responsible does the simple thing
654 and merely inverts the current values for any logical colours (LC) for which
655 the associated physical colour (as supplied as the second parameter to the VDU
656 19 call) has the top bit of its four bit value set. These top bits are not
657 recorded in the palette registers but are presumably recorded separately and
658 used to build bitmaps as follows:
659
660 LC 2 colour 4 colour 16 colour 4-bit value for inversion
661 -- -------- -------- --------- -------------------------
662 0 00010001 00010001 00010001 1, 1, 1
663 1 01000100 00100010 00010001 4, 2, 1
664 2 01000100 00100010 4, 2
665 3 10001000 00100010 8, 2
666 4 00010001 1
667 5 00010001 1
668 6 00100010 2
669 7 00100010 2
670 8 01000100 4
671 9 01000100 4
672 10 10001000 8
673 11 10001000 8
674 12 01000100 4
675 13 01000100 4
676 14 10001000 8
677 15 10001000 8
678
679 Inversion value calculation:
680
681 2 colour formula: 1 << (colour * 2)
682 4 colour formula: 1 << colour
683 16 colour formula: 1 << ((colour & 2) + ((colour & 8) * 2))
684
685 For example, where logical colour 0 has been mapped to a physical colour in
686 the range 8 to 15, a bitmap of 00010001 would be chosen as its contribution to
687 the inversion operation. (The lower three bits of the physical colour would be
688 used to set the underlying colour information affected by the inversion
689 operation.)
690
691 An operation in the interrupt code would then combine the bitmaps for all
692 logical colours in 2 and 4 colour modes, with the 16 colour bitmaps being
693 combined for groups of logical colours as follows:
694
695 Logical colours
696 ---------------
697 0, 2, 8, 10
698 4, 6, 12, 14
699 5, 7, 13, 15
700 1, 3, 9, 11
701
702 These combined bitmaps would be EORed with the existing palette register
703 values in order to perform the value inversion necessary to produce the
704 flashing effect.
705
706 Thus, in the VDU 19 operation, the appropriate inversion value would be
707 calculated for the logical colour, and this value would then be combined with
708 other inversion values in a dedicated memory location corresponding to the
709 colour's group as indicated above. Meanwhile, the palette channel values would
710 be derived from the lower three bits of the specified physical colour and
711 combined with other palette data in dedicated memory locations corresponding
712 to the palette registers.
713
714 Interestingly, although flashing colours on the BBC Micro are controlled by
715 toggling bit 0 of the &FE20 control register location for the Video ULA, the
716 actual colour inversion is done in hardware.
717
718 Enhancement: Palette Definition Lists
719 -------------------------------------
720
721 It can be useful to redefine the palette in order to change the colours
722 available for a particular region of the screen, particularly in modes where
723 the choice of colours is constrained, and if an increased colour depth were
724 available, palette redefinition would be useful to give the illusion of more
725 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
726 by using interrupt-driven timers, but a more efficient approach would involve
727 presenting lists of palette definitions to the ULA so that it can change the
728 palette at a particular display line.
729
730 One might define a palette redefinition list in a region of memory and then
731 communicate its contents to the ULA by writing the address and length of the
732 list, along with the display line at which the palette is to be changed, to
733 ULA registers such that the ULA buffers the list and performs the redefinition
734 at the appropriate time. Throughput/bandwidth considerations might impose
735 restrictions on the practical length of such a list, however.
736
737 Enhancement: Display Synchronisation Interrupts
738 -----------------------------------------------
739
740 When completing each scanline of the display, the ULA could trigger an
741 interrupt. Since this might impact system performance substantially, the
742 feature would probably need to be configurable, and it might be sufficient to
743 have an interrupt only after a certain number of display lines instead.
744 Permitting the CPU to take action after eight lines would allow palette
745 switching and other effects to occur on a character row basis.
746
747 The ULA provides an interrupt at the end of the display period, presumably so
748 that software can schedule updates to the screen, avoid flickering or tearing,
749 and so on. However, some applications might benefit from an interrupt at, or
750 just before, the start of the display period so that palette modifications or
751 similar effects could be scheduled.
752
753 Enhancement: Palette-Free Modes
754 -------------------------------
755
756 Palette-free modes might be defined where bit values directly correspond to
757 the red, green and blue channels, although this would mostly make sense only
758 for modes with depths greater than the standard 4 bits per pixel, and such
759 modes would require more memory than MODE 2 if they were to have an acceptable
760 resolution.
761
762 Enhancement: Display Suspend
763 ----------------------------
764
765 Especially when writing to the screen memory, it could be beneficial to be
766 able to suspend the ULA's access to the memory, instead producing blank values
767 for all screen pixels until a program is ready to reveal the screen. This is
768 different from palette blanking since with a blank palette, the ULA is still
769 reading screen memory and translating its contents into pixel values that end
770 up being blank.
771
772 This function is reminiscent of a capability of the ZX81, albeit necessary on
773 that hardware to reduce the load on the system CPU which was responsible for
774 producing the video output. By allowing display suspend on the Electron, the
775 performance benefit would be derived from giving the CPU full access to the
776 memory bandwidth.
777
778 The region blanking feature mentioned above could be implemented using this
779 enhancement instead of employing palette blanking for the affected lines of
780 the display.
781
782 Enhancement: Memory Filling
783 ---------------------------
784
785 A capability that could be given to an enhanced ULA is that of permitting the
786 ULA to write to screen memory as well being able to read from it. Although
787 such a capability would probably not be useful in conjunction with the
788 existing read operations when producing a screen display, and insufficient
789 bandwidth would exist to do so in high-bandwidth screen modes anyway, the
790 capability could be offered during a display suspend period (as described
791 above), permitting a more efficient mechanism to rapidly fill memory with a
792 predetermined value.
793
794 This capability could also support block filling, where the limits of the
795 filled memory would be defined by the position and size of a screen area,
796 although this would demand the provision of additional registers in the ULA to
797 retain the details of such areas and additional logic to control the fill
798 operation.
799
800 Enhancement: Region Filling
801 ---------------------------
802
803 An alternative to memory writing might involve indicating regions using
804 additional registers or memory where the ULA fills regions of the screen with
805 content instead of reading from memory. Unlike hardware sprites which should
806 realistically provide varied content, region filling could employ single
807 colours or patterns, and one advantage of doing so would be that the ULA need
808 not access memory at all within a particular region.
809
810 Regions would be defined on a row-by-row basis. Instead of reading memory and
811 blitting a direct representation to the screen, the ULA would read region
812 definitions containing a start column, region width and colour details. There
813 might be a certain number of definitions allowed per row, or the ULA might
814 just traverse an ordered list of such definitions with each one indicating the
815 row, start column, region width and colour details.
816
817 One could even compress this information further by requiring only the row,
818 start column and colour details with each subsequent definition terminating
819 the effect of the previous one. However, one would also need to consider the
820 convenience of preparing such definitions and whether efficient access to
821 definitions for a particular row might be desirable. It might also be
822 desirable to avoid having to prepare definitions for "empty" areas of the
823 screen, effectively making the definition of the screen contents employ
824 run-length encoding and employ only colour plus length information.
825
826 One application of region filling is that of simple 2D and 3D shape rendering.
827 Although it is entirely possible to plot such shapes to the screen and have
828 the ULA blit the memory contents to the screen, such operations consume
829 bandwidth both in the initial plotting and in the final transfer to the
830 screen. Region filling would reduce such bandwidth usage substantially.
831
832 This way of representing screen images would make certain kinds of images
833 unfeasible to represent - consider alternating single pixel values which could
834 easily occur in some character bitmaps - even if an internal queue of regions
835 were to be supported such that the ULA could read ahead and buffer such
836 "bandwidth intensive" areas. Thus, the ULA might be better served providing
837 this feature for certain areas of the display only as some kind of special
838 graphics window.
839
840 Enhancement: Hardware Sprites
841 -----------------------------
842
843 An enhanced ULA might provide hardware sprites, but this would be done in an
844 way that is incompatible with the standard ULA, since no &FE*X locations are
845 available for allocation. To keep the facility simple, hardware sprites would
846 have a standard byte width and height.
847
848 The specification of sprites could involve the reservation of 16 locations
849 (for example, &FE20-F) specifying a fixed number of eight sprites, with each
850 location pair referring to the sprite data. By limiting the ULA to dealing
851 with a fixed number of sprites, the work required inside the ULA would be
852 reduced since it would avoid having to deal with arbitrary numbers of sprites.
853
854 The principal limitation on providing hardware sprites is that of having to
855 obtain sprite data, given that the ULA is usually required to retrieve screen
856 data, and given the lack of memory bandwidth available to retrieve sprite data
857 (particularly from multiple sprites supposedly at the same position) and
858 screen data simultaneously. Although the ULA could potentially read sprite
859 data and screen data in alternate memory accesses in screen modes where the
860 bandwidth is not already fully utilised, this would result in a degradation of
861 performance.
862
863 Enhancement: Additional Screen Mode Configurations
864 --------------------------------------------------
865
866 Alternative screen mode configurations could be supported. The ULA has to
867 produce 640 pixel values across the screen, with pixel doubling or quadrupling
868 employed to fill the screen width:
869
870 Screen width Columns Scaling Depth Bytes
871 ------------ ------- ------- ----- -----
872 640 80 x1 1 80
873 320 40 x2 1, 2 40, 80
874 160 20 x4 2, 4 40, 80
875
876 It must also use at most 80 byte-sized memory accesses to provide the
877 information for the display. Given that characters must occupy an 8x8 pixel
878 array, if a configuration featuring anything other than 20, 40 or 80 character
879 columns is to be supported, compromises must be made such as the introduction
880 of blank pixels either between characters (such as occurs between rows in MODE
881 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
882 in MODE 3 and 6). Consider the following configuration:
883
884 Screen width Columns Scaling Depth Bytes Blank
885 ------------ ------- ------- ----- ------ -----
886 208 26 x3 1, 2 26, 52 16
887
888 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
889 colours could be provided, with 16 blank pixel values (out of a total of 640)
890 generated either at the start or end (or split between the start and end) of
891 each scanline.
892
893 Enhancement: Character Attributes
894 ---------------------------------
895
896 The BBC Micro MODE 7 employs something resembling character attributes to
897 support teletext displays, but depends on circuitry providing a character
898 generator. The ZX Spectrum, on the other hand, provides character attributes
899 as a means of colouring bitmapped graphics. Although such a feature is very
900 limiting as the sole means of providing multicolour graphics, in situations
901 where the choice is between low resolution multicolour graphics or high
902 resolution monochrome graphics, character attributes provide a potentially
903 useful compromise.
904
905 For each byte read, the ULA must deliver 8 pixel values (out of a total of
906 640) to the video output, doing so by either emptying its pixel buffer on a
907 pixel per cycle basis, or by multiplying pixels and thus holding them for more
908 than one cycle. For example for a screen mode having 640 pixels in width:
909
910 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
911 Reads: B B
912 Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
913
914 And for a screen mode having 320 pixels in width:
915
916 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
917 Reads: B
918 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
919
920 However, in modes where less than 80 bytes are required to generate the pixel
921 values, an enhanced ULA might be able to read additional bytes between those
922 providing the bitmapped graphics data:
923
924 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
925 Reads: B A
926 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
927
928 These additional bytes could provide colour information for the bitmapped data
929 in the following character column (of 8 pixels). Since it would be desirable
930 to apply attribute data to the first column, the initial 8 cycles might be
931 configured to not produce pixel values.
932
933 For an entire character, attribute data need only be read for the first row of
934 pixels for a character. The subsequent rows would have attribute information
935 applied to them, although this would require the attribute data to be stored
936 in some kind of buffer. Thus, the following access pattern would be observed:
937
938 Cycle: A B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ...
939
940 A whole byte used for colour information for a whole character would result in
941 a choice of 256 colours, and this might be somewhat excessive. By only reading
942 attribute bytes at every other opportunity, a choice of 16 colours could be
943 applied individually to two characters.
944
945 Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
946 Reads: B A B -
947 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
948
949 Further reductions in attribute data access, offering 4 colours for every
950 character in a four character block, for example, might also be worth
951 considering.
952
953 Consider the following configurations for screen modes with a colour depth of
954 1 bit per pixel for bitmap information:
955
956 Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
957 ------------ ------- ------- --------- --------- ------- ------------
958 320 40 x2 40 40 256 &5300
959 320 40 x2 40 20 16 &5580 -> &5500
960 320 40 x2 40 10 4 &56C0 -> &5600
961 208 26 x3 26 26 256 &62C0 -> &6200
962 208 26 x3 26 13 16 &6460 -> &6400
963
964 Enhancement: MODE 7 Emulation using Character Attributes
965 --------------------------------------------------------
966
967 If the scheme of applying attributes to character regions were employed to
968 emulate MODE 7, in conjunction with the MODE 6 display technique, the
969 following configuration would be required:
970
971 Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
972 ------------ ------- ---- --------- --------- ------- ------------
973 320 40 25 40 20 16 &5ECC -> &5E00
974 320 40 25 40 10 4 &5FC6 -> &5F00
975
976 Although this requires much more memory than MODE 7 (8500 bytes versus MODE
977 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
978 at least make a limited 40-column multicolour mode available as a substitute
979 for MODE 7.
980
981 Enhancement: High Resolution Graphics
982 -------------------------------------
983
984 Screen modes with higher resolutions and larger colour depths might be
985 possible, but this would in most cases involve the allocation of more screen
986 memory, and the ULA would probably then be obliged to page in such memory for
987 the CPU to be able to sensibly access it all.
988
989 Enhancement: Genlock Support
990 ----------------------------
991
992 The ULA generates a video signal in conjunction with circuitry producing the
993 output features necessary for the correct display of the screen image.
994 However, it appears that the ULA drives the video synchronisation mechanism
995 instead of reacting to an existing signal. Genlock support might be possible
996 if the ULA were made to be responsive to such external signals, resetting its
997 address generators upon receiving synchronisation events.
998
999 Enhancement: Improved Sound
1000 ---------------------------
1001
1002 The standard ULA reserves &FE*6 for sound generation and cassette input/output
1003 (with bits 1 and 2 of &FE*7 being used to select either sound generation or
1004 cassette I/O), thus making it impossible to support multiple channels within
1005 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
1006 and an enhanced ULA could adopt this interface.
1007
1008 The BBC Micro uses the SN76489 chip to produce sound, and the entire
1009 functionality of this chip could be emulated for enhanced sound, with a subset
1010 of the functionality exposed via the &FE*6 interface.
1011
1012 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
1013 See: http://www.smspower.org/Development/SN76489
1014
1015 Enhancement: Waveform Upload
1016 ----------------------------
1017
1018 As with a hardware sprite function, waveforms could be uploaded or referenced
1019 using locations as registers referencing memory regions.
1020
1021 Enhancement: Sound Input/Output
1022 -------------------------------
1023
1024 Since the ULA already controls audio input/output for cassette-based data, it
1025 would have been interesting to entertain the idea of sampling and output of
1026 sounds through the cassette interface. However, a significant amount of
1027 circuitry is employed to process the input signal for use by the ULA and to
1028 process the output signal for recording.
1029
1030 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw_03.htm#3.11
1031
1032 Enhancement: BBC ULA Compatibility
1033 ----------------------------------
1034
1035 Although some new ULA functions could be defined in a way that is also
1036 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
1037 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
1038 map, but controls various functions specific to the 6845 video controller;
1039 &FE08-F is reserved for the serial controller. It therefore becomes possible
1040 to disregard compatibility where compatibility is already disregarded for a
1041 particular area of functionality.
1042
1043 &FE20-F maps to video ULA functionality on the BBC Micro which provides
1044 control over the palette (using address &FE21, compared to &FE07-F on the
1045 Electron) and other system-specific functions. Since the location usage is
1046 generally incompatible, this region could be reused for other purposes.
1047
1048 Enhancement: Increased RAM, ULA and CPU Performance
1049 ---------------------------------------------------
1050
1051 More modern implementations of the hardware might feature faster RAM coupled
1052 with an increased ULA clock frequency in order to increase the bandwidth
1053 available to the ULA and to the CPU in situations where the ULA is not needed
1054 to perform work. A ULA employing a 32MHz clock would be able to complete the
1055 retrieval of a byte from RAM in only 250ns and thus be able to enable the CPU
1056 to access the RAM for the following 250ns even in display modes requiring the
1057 retrieval of a byte for the display every 500ns. The CPU could, subject to
1058 timing issues, run at 2MHz even in MODE 0, 1 and 2.
1059
1060 A scheme such as that described above would have a similar effect to the
1061 scheme employed in the BBC Micro, although the latter made use of RAM with a
1062 wider bandwidth in order to complete memory transfers within 250ns and thus
1063 permit the CPU to run continuously at 2MHz.
1064
1065 Higher bandwidth could potentially be used to implement exotic features such
1066 as RAM-resident hardware sprites or indeed any feature demanding RAM access
1067 concurrent with the production of the display image.
1068
1069 Enhancement: Multiple CPU Stacks and Zero Pages
1070 -----------------------------------------------
1071
1072 The 6502 maintains a stack for subroutine calls and register storage in page
1073 &01. Although the stack register can be manipulated using the TSX and TXS
1074 instructions, thereby permitting the maintenance of multiple stack regions and
1075 thus the potential coexistence of multiple programs each using a separate
1076 region, only programs that make little use of the stack (perhaps avoiding
1077 deeply-nested subroutine invocations and significant register storage) would
1078 be able to coexist without overwriting each other's stacks.
1079
1080 One way that this issue could be alleviated would involve the provision of a
1081 facility to redirect accesses to page &01 to other areas of memory. The ULA
1082 would provide a register that defines a physical page for the use of the CPU's
1083 "logical" page &01, and upon any access to page &01 by the CPU, the ULA would
1084 change the asserted address lines to redirect the access to the appropriate
1085 physical region.
1086
1087 By providing an 8-bit register, mapping to the most significant byte (MSB) of
1088 a 16-bit address, the ULA could then replace any MSB equal to &01 with the
1089 register value before the access is made. Where multiple programs coexist,
1090 upon switching programs, the register would be updated to point the ULA to the
1091 appropriate stack location, thus providing a simple memory management unit
1092 (MMU) capability.
1093
1094 In a similar fashion, zero page accesses could also be redirected so that code
1095 could run from sideways RAM and have zero page operations redirected to "upper
1096 memory" - for example, to page &BE (with stack accesses redirected to page
1097 &BF, perhaps) - thereby permitting most CPU operations to occur without
1098 inadvertent accesses to "lower memory" (the RAM) which would risk stalling the
1099 CPU as it contends with the ULA for memory access.
1100
1101 Such facilities could also be provided by a separate circuit between the CPU
1102 and ULA in a fashion similar to that employed by a "turbo" board, but unlike
1103 such boards, no additional RAM would be provided: all memory accesses would
1104 occur as normal through the ULA, albeit redirected when configured
1105 appropriately.
1106
1107 ULA Pin Functions
1108 -----------------
1109
1110 The functions of the ULA pins are described in the Electron Service Manual. Of
1111 interest to video processing are the following:
1112
1113 CSYNC (low during horizontal or vertical synchronisation periods, high
1114 otherwise)
1115
1116 HS (low during horizontal synchronisation periods, high otherwise)
1117
1118 RED, GREEN, BLUE (pixel colour outputs)
1119
1120 CLOCK IN (a 16MHz clock input, 4V peak to peak)
1121
1122 PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
1123
1124 More general memory access pins:
1125
1126 RAM0...RAM3 (data lines to/from the RAM)
1127
1128 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
1129
1130 RAS (row address strobe setting the row address on a negative edge - see the
1131 timing notes)
1132
1133 CAS (column address strobe setting the column address on a negative edge -
1134 see the timing notes)
1135
1136 WE (sets write enable with logic 0, read with logic 1)
1137
1138 ROM (select data access from ROM)
1139
1140 CPU-oriented memory access pins:
1141
1142 A0...A15 (CPU address lines)
1143
1144 PD0...PD7 (CPU data lines)
1145
1146 R/W (indicates CPU write with logic 0, CPU read with logic 1)
1147
1148 Interrupt-related pins:
1149
1150 NMI (CPU request for uninterrupted 1MHz access to memory)
1151
1152 IRQ (signal event to CPU)
1153
1154 POR (power-on reset, resetting the ULA on a positive edge and asserting the
1155 CPU's RST pin)
1156
1157 RST (master reset for the CPU signalled on power-up and by the Break key)
1158
1159 Keyboard-related pins:
1160
1161 KBD0...KBD3 (keyboard inputs)
1162
1163 CAPS LOCK (control status LED)
1164
1165 Sound-related pins:
1166
1167 SOUND O/P (sound output using internal oscillator)
1168
1169 Cassette-related pins:
1170
1171 CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
1172
1173 CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
1174
1175 CAS RC (detect high tone)
1176
1177 CAS MO (motor relay output)
1178
1179 ÷13 IN (~1200 baud clock input)
1180
1181 ULA Socket
1182 ----------
1183
1184 The socket used for the ULA is a 3M/TexTool 268-5400 68-pin socket.
1185
1186 References
1187 ----------
1188
1189 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw.htm
1190
1191 About this Document
1192 -------------------
1193
1194 The most recent version of this document and accompanying distribution should
1195 be available from the following location:
1196
1197 http://hgweb.boddie.org.uk/ULA
1198
1199 Copyright and licence information can be found in the docs directory of this
1200 distribution - see docs/COPYING.txt for more information.