1 #!/usr/bin/env python 2 3 """ 4 Acorn Electron ULA simulation. 5 6 Copyright (C) 2011, 2012, 2013, 2014, 2016 Paul Boddie <paul@boddie.org.uk> 7 8 This program is free software; you can redistribute it and/or modify it under 9 the terms of the GNU General Public License as published by the Free Software 10 Foundation; either version 3 of the License, or (at your option) any later 11 version. 12 13 This program is distributed in the hope that it will be useful, but WITHOUT ANY 14 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A 15 PARTICULAR PURPOSE. See the GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License along 18 with this program. If not, see <http://www.gnu.org/licenses/>. 19 """ 20 21 from array import array 22 from itertools import repeat 23 24 LINES_PER_ROW = 8 # the number of pixel lines per character row 25 MAX_HEIGHT = 256 # the height of the screen in pixels 26 MAX_WIDTH = 640 # the width of the screen in pixels 27 28 MAX_CSYNC = 2 # the scanline during which vsync ends 29 MIN_PIXELLINE = 28 # the first scanline involving pixel generation 30 MAX_SCANLINE = 312 # the number of scanlines in each frame 31 32 MAX_PIXELLINE = MIN_PIXELLINE + MAX_HEIGHT 33 34 MAX_HSYNC = 64 # the number of cycles in each hsync period 35 MIN_PIXELPOS = 256 # the first cycle involving pixel generation 36 MAX_SCANPOS = 1024 # the number of cycles in each scanline 37 38 MAX_PIXELPOS = MIN_PIXELPOS + MAX_WIDTH 39 40 SCREEN_LIMIT = 0x8000 # the first address after the screen memory 41 MAX_MEMORY = 0x10000 # the number of addressable memory locations 42 MAX_RAM = 0x10000 # the number of addressable RAM locations (64Kb in each IC) 43 BLANK = (0, 0, 0) 44 45 def update(ula): 46 47 """ 48 Update the 'ula' for one frame. Return the resulting screen. 49 """ 50 51 video = ula.video 52 53 i = 0 54 limit = MAX_SCANLINE * MAX_SCANPOS 55 while i < limit: 56 ula.posedge() 57 video.update() 58 ula.negedge() 59 i += 1 60 61 return video.screen 62 63 class Video: 64 65 """ 66 A class representing the video circuitry. 67 """ 68 69 def __init__(self): 70 self.screen = array("B", repeat(0, MAX_WIDTH * 3 * MAX_HEIGHT)) 71 self.colour = BLANK 72 self.csync = 1 73 self.hs = 1 74 self.x = 0 75 self.y = 0 76 77 def set_csync(self, value): 78 if self.csync and not value: 79 self.y = 0 80 self.pos = 0 81 self.csync = value 82 83 def set_hs(self, value): 84 if self.hs and not value: 85 self.x = 0 86 self.y += 1 87 self.hs = value 88 89 def update(self): 90 if MIN_PIXELLINE <= self.y < MAX_PIXELLINE: 91 if MIN_PIXELPOS + 8 <= self.x < MAX_PIXELPOS + 8: 92 self.screen[self.pos] = self.colour[0]; self.pos += 1 93 self.screen[self.pos] = self.colour[1]; self.pos += 1 94 self.screen[self.pos] = self.colour[2]; self.pos += 1 95 self.x += 1 96 97 class RAM: 98 99 """ 100 A class representing the RAM circuits (IC4 to IC7). Each circuit 101 traditionally holds 64 kilobits, with each access obtaining 1 bit from each 102 IC, and thus two accesses being required to obtain a whole byte. Here, we 103 model the circuits with a list of 65536 half-bytes with each bit in a 104 half-byte representing a bit stored on a separate IC. 105 """ 106 107 def __init__(self): 108 109 "Initialise the RAM circuits." 110 111 self.memory = [0] * MAX_RAM 112 self.row_address = 0 113 self.column_address = 0 114 self.data = 0 115 self.read_not_write = 1 116 117 def row_select(self, address): 118 119 "The operation of asserting a row 'address' via RA0...RA7." 120 121 self.row_address = address 122 123 def row_deselect(self): 124 pass 125 126 def column_select(self, address): 127 128 "The operation of asserting a column 'address' via RA0...RA7." 129 130 self.column_address = address 131 132 # Read the data. 133 134 if self.read_not_write: 135 self.data = self.memory[self.row_address << 8 | self.column_address] 136 else: 137 self.memory[self.row_address << 8 | self.column_address] = self.data 138 139 def column_deselect(self): 140 pass 141 142 def read_select(self): 143 self.read_not_write = 1 144 145 def write_select(self): 146 self.read_not_write = 0 147 148 # Convenience methods. 149 150 def fill(self, start, end, value): 151 for i in xrange(start, end): 152 self.memory[i << 1] = value >> 4 153 self.memory[i << 1 | 0x1] = value & 0xf 154 155 class CPU: 156 157 "A CPU abstraction." 158 159 def __init__(self): 160 self.address = 0x1000 161 self.data = 0 162 self.read_not_write = 1 163 164 class ULA: 165 166 """ 167 A class providing the ULA functionality. Instances of this class refer to 168 the system memory, maintain internal state (such as information about the 169 current screen mode), and provide outputs (such as the current pixel 170 colour). 171 """ 172 173 modes = [ 174 (640, 1, 32), (320, 2, 32), (160, 4, 32), # (width, depth, rows) 175 (640, 1, 25), (320, 1, 32), (160, 2, 32), 176 (320, 1, 25) 177 ] 178 179 def __init__(self, cpu, ram, video): 180 181 "Initialise the ULA with the given 'cpu', 'ram' and 'video' instances." 182 183 self.cpu = cpu 184 self.ram = ram 185 self.video = video 186 self.set_mode(6) 187 self.palette = map(get_physical_colour, range(0, 8) * 2) 188 189 self.reset() 190 191 def reset(self): 192 193 "Reset the ULA." 194 195 # General state. 196 197 self.nmi = 0 # no NMI asserted initially 198 self.irq_vsync = 0 # no IRQ asserted initially 199 self.cpu_clock = 0 # drive the CPU clock low 200 201 # Communication. 202 203 self.ram_address = 0 # address given to the RAM via RA0...RA7 204 self.data = 0 # data read from the RAM via RAM0...RAM3 205 self.cpu_address = 0 # address selected by the CPU via A0...A15 206 self.cpu_read = 0 # data read/write by the CPU selected using R/W 207 208 # Internal state. 209 210 self.have_pixels = 0 # whether pixel data has been read 211 self.pdata = 0 # decoded RAM data for pixel output 212 self.cycle = 1 # 8-state counter within each 2MHz period 213 self.pcycle = 0 # 8/4/2-state pixel output counter 214 215 self.next_frame() 216 217 def set_mode(self, mode): 218 219 """ 220 For the given 'mode', initialise the... 221 222 * width in pixels 223 * colour depth in bits per pixel 224 * number of character rows 225 * character row size in bytes 226 * screen size in bytes 227 * default screen start address 228 * horizontal pixel scaling factor 229 * row height in pixels 230 * display height in pixels 231 232 The ULA should be reset after a mode switch in order to cleanly display 233 a full screen. 234 """ 235 236 width, self.depth, rows = self.modes[mode] 237 238 columns = (width * self.depth) / 8 # bits read -> bytes read 239 self.access_frequency = 80 / columns # cycle frequency for reading bytes 240 row_size = columns * LINES_PER_ROW 241 242 # Memory access configuration. 243 # Note the limitation on positioning the screen start. 244 245 screen_size = row_size * rows 246 self.screen_start = (SCREEN_LIMIT - screen_size) & 0xff00 247 self.screen_size = SCREEN_LIMIT - self.screen_start 248 249 # Scanline configuration. 250 251 self.xscale = MAX_WIDTH / width # pixel width in display pixels 252 self.row_height = MAX_HEIGHT / rows # row height in display pixels 253 self.display_height = rows * self.row_height # display height in pixels 254 255 def vsync(self, value=0): 256 257 "Signal the start of a frame." 258 259 self.csync = value 260 self.video.set_csync(value) 261 262 def hsync(self, value=0): 263 264 "Signal the end of a scanline." 265 266 self.hs = value 267 self.video.set_hs(value) 268 269 def next_frame(self): 270 271 "Signal the start of a frame." 272 273 self.line_start = self.pixel_address = self.screen_start 274 self.line = self.line_start % LINES_PER_ROW 275 self.y = 0 276 self.x = 0 277 278 def next_horizontal(self): 279 280 "Visit the next horizontal position." 281 282 self.pixel_address += LINES_PER_ROW 283 self.wrap_address() 284 285 def next_vertical(self): 286 287 "Reset horizontal state within the active region of the frame." 288 289 self.y += 1 290 self.x = 0 291 292 if self.inside_frame(): 293 self.line += 1 294 295 # At the end of a row... 296 297 if self.line == self.row_height: 298 299 # After the end of the last line in a row, the address should already 300 # have been positioned on the last line of the next column. 301 302 self.pixel_address -= LINES_PER_ROW - 1 303 self.wrap_address() 304 self.line = 0 305 306 # Record the position of the start of the pixel row. 307 308 self.line_start = self.pixel_address 309 310 # Before any spacing between character rows... 311 312 elif self.in_line(): 313 314 # If not on a row boundary, move to the next line. Here, the address 315 # needs bringing back to the previous character row. 316 317 self.pixel_address = self.line_start + 1 318 self.wrap_address() 319 320 # Record the position of the start of the pixel row. 321 322 self.line_start = self.pixel_address 323 324 def access_cycle(self): return (self.x / 8) % self.access_frequency == 0 325 def would_access_ram(self): return self.access_cycle() and self.read_pixels() and self.in_line() 326 def access_ram(self): return not self.nmi and self.would_access_ram() 327 def in_line(self): return self.line < LINES_PER_ROW 328 def in_frame(self): return MIN_PIXELLINE <= self.y < (MIN_PIXELLINE + self.display_height) 329 def inside_frame(self): return MIN_PIXELLINE < self.y < (MIN_PIXELLINE + self.display_height) 330 def read_pixels(self): return MIN_PIXELPOS <= self.x < MAX_PIXELPOS and self.in_frame() 331 def write_pixels(self): return self.pcycle != 0 332 def next_pixel(self): return self.xscale == 1 or (self.xscale == 2 and self.cycle & 0b01010101) or (self.xscale == 4 and self.cycle & 0b00010001) 333 334 def posedge(self): 335 336 "Update the state of the ULA for each clock cycle." 337 338 self.posedge_ram() 339 self.posedge_pixel() 340 341 def posedge_ram(self): 342 343 """ 344 RAM signalling. 345 346 States handled: * _ * * _ * * _ 347 """ 348 349 # Clock management. 350 351 # Read 4 bits (for RAM access only). 352 353 if self.cycle == 1: 354 355 # Reset addresses. 356 357 self.ram.column_deselect() 358 self.ram.row_deselect() 359 360 # Either read from a required address or transfer CPU data. 361 362 if self.have_pixels: 363 self.data = (self.data & 0xf0) | self.ram.data 364 else: 365 self.cpu_update_clock() 366 self.cpu_transfer_low() 367 368 # Latch row address. 369 370 elif self.cycle == 4: 371 372 # Select an address needed by the ULA or CPU. 373 374 self.ram.row_select(self.ram_address) 375 376 # Latch column address. 377 378 elif self.cycle == 8: 379 380 # Select an address needed by the ULA or CPU. 381 382 self.ram.column_select(self.ram_address) 383 384 # Assert the RAM write enable if appropriate. 385 386 if self.access_ram(): 387 self.ram.read_select() 388 else: 389 self.cpu_transfer_select() 390 391 # Read 4 bits (for RAM access only). 392 393 elif self.cycle == 32: 394 395 # Prepare to latch column address. 396 397 self.ram.column_deselect() 398 399 # Either read from a required address or transfer CPU data. 400 401 if self.access_ram(): 402 self.data = self.ram.data << 4 403 else: 404 self.cpu_transfer_high() 405 406 # Latch column address. 407 408 elif self.cycle == 64: 409 410 # Select an address needed by the ULA or CPU. 411 412 self.ram.column_select(self.ram_address) 413 414 def posedge_pixel(self): 415 416 "Pixel production." 417 418 # For pixels within the frame, obtain and output the value. 419 420 if self.write_pixels(): 421 self.output_colour_value() 422 423 # Scale pixels horizontally, only accessing the next pixel value 424 # after the required number of scan positions. 425 426 if self.next_pixel(): 427 self.next_pixel_value() 428 429 # Detect spacing between character rows. 430 431 else: 432 self.video.colour = BLANK 433 434 def negedge(self): 435 436 """ 437 Update the state of the device on the negative edge of each clock cycle. 438 """ 439 440 self.negedge_video() 441 self.negedge_ram() 442 443 def negedge_video(self): 444 445 "Video signalling." 446 447 # Detect the end of the scanline. 448 449 if self.x == MAX_SCANPOS: 450 self.next_vertical() 451 452 # Detect the end of the frame. 453 454 if self.y == MAX_SCANLINE: 455 self.next_frame() 456 457 # Detect any sync conditions. 458 459 if self.x == 0: 460 self.hsync() 461 if self.y == 0: 462 self.vsync() 463 self.irq_vsync = 0 464 elif self.y == MAX_PIXELLINE: 465 self.irq_vsync = 1 466 467 # Detect the end of hsync. 468 469 elif self.x == MAX_HSYNC: 470 self.hsync(1) 471 472 # Detect the end of vsync. 473 474 elif self.y == MAX_CSYNC and self.x == MAX_SCANPOS / 2: 475 self.vsync(1) 476 477 def negedge_ram(self): 478 479 """ 480 Prepare addresses and pixel data. 481 482 States handled: * * * _ _ * _ * 483 """ 484 485 # Clock management. 486 487 # Initialise the pixel buffer if appropriate. Output starts after 488 # this cycle. 489 490 if self.cycle == 1 and self.have_pixels: 491 self.pdata = decode(self.data, self.depth) 492 self.pcycle = 1 493 self.have_pixels = 0 494 495 # Set row address (for RAM access only). 496 497 elif self.cycle == 2: 498 499 # Either assert a required address or propagate the CPU address. 500 501 if self.access_ram(): 502 self.init_row_address(self.pixel_address) 503 else: 504 self.init_row_address(self.cpu_address) 505 506 # Latch row address, set column address (for RAM access only). 507 508 elif self.cycle == 4: 509 510 # Either assert a required address or propagate the CPU address. 511 512 if self.access_ram(): 513 self.init_column_address(self.pixel_address, 0) 514 else: 515 self.init_column_address(self.cpu_address, 0) 516 517 # Set column address (for RAM access only). 518 519 elif self.cycle == 32: 520 521 # Either assert a required address or propagate the CPU address. 522 523 if self.access_ram(): 524 self.init_column_address(self.pixel_address, 1) 525 else: 526 self.init_column_address(self.cpu_address, 1) 527 528 # Update addresses. 529 530 elif self.cycle == 128: 531 532 # Advance to the next column even if an NMI is asserted. 533 534 if self.would_access_ram(): 535 self.next_horizontal() 536 537 # If the ULA accessed RAM, indicate that a read needs completing. 538 539 if self.access_ram(): 540 self.have_pixels = 1 541 542 # Start a new cycle. 543 544 self.cycle = rotate(self.cycle, 1) 545 self.x += 1 546 547 def output_colour_value(self): 548 549 """ 550 Output the colour value for the current pixel by translating memory 551 content for the current mode. 552 """ 553 554 value = value_of_bits(self.pdata, self.depth) 555 self.video.colour = self.palette[value] 556 557 def next_pixel_value(self): 558 self.pdata = rotate(self.pdata, self.depth) 559 self.pcycle = rotate(self.pcycle, self.depth, zero=True) 560 561 def wrap_address(self): 562 if self.pixel_address >= SCREEN_LIMIT: 563 self.pixel_address -= self.screen_size 564 565 def init_row_address(self, address): 566 self.ram_address = (address & 0xff80) >> 7 567 568 def init_column_address(self, address, offset): 569 self.ram_address = (address & 0x7f) << 1 | offset 570 571 def cpu_transfer_high(self): 572 if self.cpu_read: 573 self.cpu_data = self.ram.data << 4 574 else: 575 self.ram.data = self.cpu_data >> 4 576 577 def cpu_transfer_low(self): 578 if self.cpu_read: 579 self.cpu_data = self.data | self.ram.data 580 else: 581 self.ram.data = self.cpu_data & 0b00001111 582 583 def cpu_read_address(self): 584 self.cpu_address = self.cpu.address 585 586 def cpu_transfer_data(self): 587 if self.cpu_read: 588 self.cpu.data = self.cpu_data 589 else: 590 self.cpu_data = self.cpu.data 591 592 def cpu_update_clock(self): 593 self.cpu_clock = not self.cpu_clock 594 if self.cpu_clock: 595 self.cpu_transfer_data() 596 else: 597 self.cpu_read_address() 598 599 def cpu_transfer_select(self): 600 self.cpu_read = self.cpu.read_not_write 601 if self.cpu_read: 602 self.ram.read_select() 603 else: 604 self.ram.write_select() 605 606 def rotate(value, depth, width=8, zero=False): 607 608 """ 609 Return 'value' rotated left by the number of bits given by 'depth', doing so 610 within a value 'width' given in bits. If 'zero' is true, rotate zero bits 611 into the lower bits when rotating. 612 """ 613 614 field = width - depth 615 top = value >> field 616 mask = 2 ** (width - depth) - 1 617 rest = value & mask 618 return (rest << depth) | (not zero and top or 0) 619 620 def value_of_bits(value, depth): 621 622 """ 623 Convert the upper bits of 'value' to a result, using 'depth' to indicate the 624 number of bits involved. 625 """ 626 627 return value >> (8 - depth) 628 629 def get_physical_colour(value): 630 631 """ 632 Return the physical colour as an RGB triple for the given 'value'. 633 """ 634 635 return value & 1, value >> 1 & 1, value >> 2 & 1 636 637 def decode(value, depth): 638 639 """ 640 Decode the given byte 'value' according to the 'depth' in bits per pixel, 641 returning a sequence of pixel values. 642 """ 643 644 if depth == 1: 645 return value 646 elif depth == 2: 647 return ((value & 128) | ((value & 8) << 3) | ((value & 64) >> 1) | ((value & 4) << 2) | 648 ((value & 32) >> 2) | ((value & 2) << 1) | ((value & 16) >> 3) | (value & 1)) 649 elif depth == 4: 650 return ((value & 128) | ((value & 32) << 1) | ((value & 8) << 2) | ((value & 2) << 3) | 651 ((value & 64) >> 3) | ((value & 16) >> 2) | ((value & 4) >> 1) | (value & 1)) 652 else: 653 raise ValueError, "Only depths of 1, 2 and 4 are supported, not %d." % depth 654 655 # Convenience functions. 656 657 def encode(values, depth): 658 659 """ 660 Encode the given 'values' according to the 'depth' in bits per pixel, 661 returning a byte value for the pixels. 662 """ 663 664 result = 0 665 666 if depth == 1: 667 for value in values: 668 result = result << 1 | (value & 1) 669 elif depth == 2: 670 for value in values: 671 result = result << 1 | (value & 2) << 3 | (value & 1) 672 elif depth == 4: 673 for value in values: 674 result = result << 1 | (value & 8) << 3 | (value & 4) << 2 | (value & 2) << 1 | (value & 1) 675 else: 676 raise ValueError, "Only depths of 1, 2 and 4 are supported, not %d." % depth 677 678 return result 679 680 def get_ula(): 681 682 "Return a ULA initialised with a memory array and video." 683 684 return ULA(get_cpu(), get_ram(), get_video()) 685 686 def get_video(): 687 688 "Return a video circuit." 689 690 return Video() 691 692 def get_ram(): 693 694 "Return an instance representing the computer's RAM hardware." 695 696 return RAM() 697 698 def get_cpu(): 699 700 "Return an instance representing the CPU." 701 702 return CPU() 703 704 # Test program providing coverage (necessary for compilers like Shedskin). 705 706 if __name__ == "__main__": 707 ula = get_ula() 708 ula.set_mode(2) 709 ula.reset() 710 ula.ram.fill(0x5800 - 320, 0x8000, encode((2, 7), 4)) 711 712 # Make a simple two-dimensional array of tuples (three-dimensional in pygame 713 # terminology). 714 715 a = update(ula) 716 717 # vim: tabstop=4 expandtab shiftwidth=4