1 The Acorn Electron ULA
2 ======================
3
4 Principal Design and Feature Constraints
5 ----------------------------------------
6
7 The features of the ULA are limited in sophistication by the amount of time
8 and resources that can be allocated to each activity supporting the
9 fundamental features and obligations of the unit. Maintaining a screen display
10 based on the contents of RAM itself requires the ULA to have exclusive access
11 to various hardware resources for a significant period of time.
12
13 Whilst other elements of the ULA can in principle run in parallel with the
14 display refresh activity, they cannot also access the RAM at the same time.
15 Consequently, other features that might use the RAM must accept a reduced
16 allocation of that resource in comparison to a hypothetical architecture where
17 concurrent RAM access is possible at all times.
18
19 Thus, the principal constraint for many features is bandwidth. The duration of
20 access to hardware resources is one aspect of this; the rate at which such
21 resources can be accessed is another. For example, the RAM is not fast enough
22 to support access more frequently than one byte per 2MHz cycle, and for screen
23 modes involving 80 bytes of screen data per scanline, there are no free cycles
24 for anything other than the production of pixel output during the active
25 scanline periods.
26
27 Another constraint is imposed by the method of RAM access provided by the ULA.
28 The ULA is able to access RAM by fetching 4 bits at a time and thus managing
29 to transfer 8 bits within a single 2MHz cycle, this being sufficient to
30 provide display data for the most demanding screen modes. However, this
31 mechanism's timing requirements are beyond the capabilities of the CPU when
32 running at 2MHz.
33
34 Consequently, the CPU will only ever be able to access RAM via the ULA at
35 1MHz, even when the ULA is not accessing the RAM. Fortunately, when needing to
36 refresh the display, the ULA is still able to make use of the idle part of
37 each 1MHz cycle (or, rather, the idle 2MHz cycle unused by the CPU) to itself
38 access the RAM at a rate of 1 byte per 1MHz cycle (or 1 byte every other 2MHz
39 cycle), thus supporting the less demanding screen modes.
40
41 Timing
42 ------
43
44 According to 15.3.2 in the Advanced User Guide, there are 312 scanlines, 256
45 of which are used to generate pixel data. At 50Hz, this means that 128 cycles
46 are spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
47 312 ~= 128 cycles). This is consistent with the observation that each scanline
48 requires at most 80 bytes of data, and that the ULA is apparently busy for 40
49 out of 64 microseconds in each scanline.
50
51 (In fact, since the ULA is seeking to provide an image for an interlaced
52 625-line display, there are in fact two "fields" involved, one providing 312
53 scanlines and one providing 313 scanlines. See below for a description of the
54 video system.)
55
56 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
57 each providing two bits of each byte) using two cycles within the 500ns period
58 of the 2MHz clock to complete each access operation. Since the CPU and ULA
59 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
60 effectively run at 1MHz (since every other 500ns period involves the ULA
61 accessing RAM) during transfers of screen data.
62
63 The CPU is driven by an external clock (IC8) whose 16MHz frequency is divided
64 by the ULA (IC1) depending on the screen mode in use. Each 16MHz cycle is
65 approximately 62.5ns. To access the memory, the following patterns
66 corresponding to 16MHz cycles are required:
67
68 Time (ns): 0-------------- 500------------- ...
69 2 MHz cycle: 0 1 ...
70 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
71 /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ ...
72 ~RAS: /---\___________/---\___________ ...
73 ~CAS: /-----\___/-\___/-----\___/-\___ ...
74 Address events: A B C A B C ...
75 Data events: F S F S ...
76
77 ~RAS ops: 1 0 1 0 ...
78 ~CAS ops: 1 0 1 0 1 0 1 0 ...
79
80 Address ops: a b c a b c ...
81 Data ops: s f s f ...
82
83 ~WE: ......W ...
84 PHI OUT: \_______________/--------------- ...
85 CPU (RAM): L D ...
86 RnW: R ...
87
88 PHI OUT: \_______/-------\_______/------- ...
89 CPU (ROM): L D L D ...
90 RnW: R R ...
91
92 ~RAS must be high for 100ns, ~CAS must be high for 50ns.
93 ~RAS must be low for 150ns, ~CAS must be low for 90ns.
94 Data is available 150ns after ~RAS goes low, 90ns after ~CAS goes low.
95
96 Here, "A" and "B" respectively indicate the row and first column addresses
97 being latched into the RAM (on a negative edge for ~RAS and ~CAS
98 respectively), and "C" indicates the second column address being latched into
99 the RAM. Presumably, the first and second half-bytes can be read at "F" and
100 "S" respectively, and the row and column addresses must be made available at
101 "a" and "b" (and "c") respectively at the latest. Data can be read at "f" and
102 "s" for the first and second half-bytes respectively.
103
104 For the CPU, "L" indicates the point at which an address is taken from the CPU
105 address bus, on a negative edge of PHI OUT, with "D" being the point at which
106 data may either be read or be asserted for writing, on a positive edge of PHI
107 OUT. Here, PHI OUT is driven at 1MHz. Given that ~WE needs to be driven low
108 for writing or high for reading, and thus propagates RnW from the CPU, this
109 would need to be done before data would be retrieved and, according to the
110 TM4164EC4 datasheet, even as late as the column address is presented and ~CAS
111 brought low.
112
113 The TM4164EC4-15 has a row address access time of 150ns (maximum) and a column
114 address access time of 90ns (maximum), which appears to mean that ~RAS must be
115 held low for at least 150ns and that ~CAS must be held low for at least 90ns
116 before data becomes available. 150ns is 2.4 cycles (at 16MHz) and 90ns is 1.44
117 cycles. Thus, "A" to "F" is 2.5 cycles, "B" to "F" is 1.5 cycles, "C" to "S"
118 is 1.5 cycles.
119
120 Note that the Service Manual refers to the negative edge of RAS and CAS, but
121 the datasheet for the similar TM4164EC4 product shows latching on the negative
122 edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
123 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
124 "page mode" provides the appropriate behaviour for that particular product.
125
126 The CPU, when accessing the RAM alone, apparently does not make use of the
127 vacated "slot" that the ULA would otherwise use (when interleaving accesses in
128 MODE 4, 5 and 6). It only employs a full 2MHz access frequency to memory when
129 accessing ROM (and potentially sideways RAM). The principal limitation is the
130 amount of time needed between issuing an address and receiving an entire byte
131 from the RAM, which is approximately 7 cycles (at 16MHz): much longer than the
132 4 cycles that would be required for 2MHz operation.
133
134 See: Acorn Electron Advanced User Guide
135 See: Acorn Electron Service Manual
136 http://chrisacorns.computinghistory.org.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
137 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
138 See: http://stardot.org.uk/forums/viewtopic.php?p=120438#p120438
139
140 A Note on 8-Bit Wide RAM Access
141 -------------------------------
142
143 It is worth considering the timing when 8 bits of data can be obtained at once
144 from the RAM chips:
145
146 Time (ns): 0-------------- 500------------- ...
147 2 MHz cycle: 0 1 ...
148 8 MHz cycle: 0 1 2 3 0 1 2 3 ...
149 /-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_ ...
150 ~RAS: /---\___________/---\___________ ...
151 ~CAS: /-------\_______/-------\_______ ...
152 Address events: A B A B ...
153 Data events: F F ...
154
155 ~RAS ops: 1 0 1 0 ...
156 ~CAS ops: 1 0 1 0 ...
157
158 Address ops: a b a b ...
159 Data ops: f s f ...
160
161 ~WE: ........W ...
162 PHI OUT: \_______/-------\_______/------- ...
163 CPU: L D L D ...
164 RnW: R R ...
165
166 Since only one fetch is required per 2MHz cycle, instead of two fetches for
167 the 4-bit wide RAM arrangement, it seems likely that longer 8MHz cycles could
168 be used to coordinate the necessary signalling.
169
170 CPU Clock Notes
171 ---------------
172
173 "The 6502 receives an external square-wave clock input signal on pin 37, which
174 is usually labeled PHI0. [...] This clock input is processed within the 6502
175 to form two clock outputs: PHI1 and PHI2 (pins 3 and 39, respectively). PHI2
176 is essentially a copy of PHI0; more specifically, PHI2 is PHI0 after it's been
177 through two inverters and a push-pull amplifier. The same network of
178 transistors within the 6502 which generates PHI2 is also tied to PHI1, and
179 generates PHI1 as the inverse of PHI0. The reason why PHI1 and PHI2 are made
180 available to external devices is so that they know when they can access the
181 CPU. When PHI1 is high, this means that external devices can read from the
182 address bus or data bus; when PHI2 is high, this means that external devices
183 can write to the data bus."
184
185 See: http://lateblt.livejournal.com/88105.html
186
187 "The 6502 has a synchronous memory bus where the master clock is divided into
188 two phases (Phase 1 and Phase 2). The address is always generated during Phase
189 1 and all memory accesses take place during Phase 2."
190
191 See: http://www.jmargolin.com/vgens/vgens.htm
192
193 Thus, the inverse of PHI OUT provides the "other phase" of the clock. "During
194 Phase 1" means when PHI0 - really PHI2 - is high and "during Phase 2" means
195 when PHI1 is high.
196
197 Bandwidth Figures
198 -----------------
199
200 Using an observation of 128 2MHz cycles per scanline, 256 active lines and 312
201 total lines, with 80 cycles occurring in the active periods of display
202 scanlines, the following bandwidth calculations can be performed:
203
204 Total theoretical maximum:
205 128 cycles * 312 lines
206 = 39936 bytes
207
208 MODE 0, 1, 2:
209 ULA: 80 cycles * 256 lines
210 = 20480 bytes
211 CPU: 48 cycles / 2 * 256 lines
212 + 128 cycles / 2 * (312 - 256) lines
213 = 9728 bytes
214
215 MODE 3:
216 ULA: 80 cycles * 24 rows * 8 lines
217 = 15360 bytes
218 CPU: 48 cycles / 2 * 24 rows * 8 lines
219 + 128 cycles / 2 * (312 - (24 rows * 8 lines))
220 = 12288 bytes
221
222 MODE 4, 5:
223 ULA: 40 cycles * 256 lines
224 = 10240 bytes
225 CPU: (40 cycles + 48 cycles / 2) * 256 lines
226 + 128 cycles / 2 * (312 - 256) lines
227 = 19968 bytes
228
229 MODE 6:
230 ULA: 40 cycles * 24 rows * 8 lines
231 = 7680 bytes
232 CPU: (40 cycles + 48 cycles / 2) * 24 rows * 8 lines
233 + 128 cycles / 2 * (312 - (24 rows * 8 lines))
234 = 19968 bytes
235
236 Here, the division of 2 for CPU accesses is performed to indicate that the CPU
237 only uses every other access opportunity even in uncontended periods. See the
238 2MHz RAM Access enhancement below for bandwidth calculations that consider
239 this limitation removed.
240
241 Video Timing
242 ------------
243
244 According to 8.7 in the Service Manual, and the PAL Wikipedia page,
245 approximately 4.7µs is used for the sync pulse, 5.7µs for the "back porch"
246 (including the "colour burst"), and 1.65µs for the "front porch", totalling
247 12.05µs and thus leaving 51.95µs for the active video signal for each
248 scanline. As the Service Manual suggests in the oscilloscope traces, the
249 display information is transmitted more or less centred within the active
250 video period since the ULA will only be providing pixel data for 40µs in each
251 scanline.
252
253 Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that
254 each scanline can be divided into 1024 cycles, although only 640 at most are
255 actively used to provide pixel data. Pixel data production should only occur
256 within a certain period on each scanline, approximately 262 cycles after the
257 start of hsync:
258
259 active video period = 51.95µs
260 pixel data period = 40µs
261 total silent period = 51.95µs - 40µs = 11.95µs
262 silent periods (before and after) = 11.95µs / 2 = 5.975µs
263 hsync and back porch period = 4.7µs + 5.7µs = 10.4µs
264 time before pixel data period = 10.4µs + 5.975µs = 16.375µs
265 pixel data period start cycle = 16.375µs / 62.5ns = 262
266
267 By choosing a number divisible by 8, the RAM access mechanism can be
268 synchronised with the pixel production. Thus, 256 is a more appropriate start
269 cycle, where the HS (horizontal sync) signal corresponding to the 4µs sync
270 pulse (or "normal sync" pulse as described by the "PAL TV timing and voltages"
271 document) occurs at cycle 0.
272
273 To summarise:
274
275 HS signal starts at cycle 0 on each horizontal scanline
276 HS signal ends approximately 4µs later at cycle 64
277 Pixel data starts approximately 12µs later at cycle 256
278
279 "Re: Electron Memory Contention" provides measurements that appear consistent
280 with these calculations.
281
282 The "vertical blanking period", meaning the period before picture information
283 in each field is 25 lines out of 312 (or 313) and thus lasts for 1.6ms. Of
284 this, 2.5 lines occur before the vsync (field sync) which also lasts for 2.5
285 lines. Thus, the first visible scanline on the first field of a frame occurs
286 half way through the 23rd scanline period measured from the start of vsync
287 (indicated by "V" in the diagrams below):
288
289 10 20 23
290 Line in frame: 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
291 Line from 1: 0 22 3
292 Line on screen: .:::::VVVVV::::: 12233445566
293 |_________________________________________________|
294 25 line vertical blanking period
295
296 In the second field of a frame, the first visible scanline coincides with the
297 24th scanline period measured from the start of line 313 in the frame:
298
299 310 336
300 Line in frame: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
301 Line from 313: 0 23 4
302 Line on screen: 88:::::VVVVV:::: 11223344
303 288 | |
304 |_________________________________________________|
305 25 line vertical blanking period
306
307 In order to consider only full lines, we might consider the start of each
308 frame to occur 23 lines after the start of vsync.
309
310 Again, it is likely that pixel data production should only occur on scanlines
311 within a certain period on each frame. The "625/50" document indicates that
312 only a certain region is "safe" to use, suggesting a vertically centred region
313 with approximately 15 blank lines above and below the picture. However, the
314 "PAL TV timing and voltages" document suggests 28 blank lines above and below
315 the picture. This would centre the 256 lines within the 312 lines of each
316 field and thus provide a start of picture approximately 5.5 or 5 lines after
317 the end of the blanking period or 28 or 27.5 lines after the start of vsync.
318
319 To summarise:
320
321 CSYNC signal starts at cycle 0
322 CSYNC signal ends approximately 160µs (2.5 lines) later at cycle 2560
323 Start of line occurs approximately 1632µs (5.5 lines) later at cycle 28672
324
325 See: http://en.wikipedia.org/wiki/PAL
326 See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal
327 See: The 625/50 PAL Video Signal and TV Compatible Graphics Modes
328 http://lipas.uwasa.fi/~f76998/video/modes/
329 See: PAL TV timing and voltages
330 http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
331 See: Line Standards
332 http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html
333 See: Horizontal Blanking Interval of 405-, 525-, 625- and 819-Line Standards
334 http://www.pembers.freeserve.co.uk/World-TV-Standards/HBI.pdf
335 See: Re: Electron Memory Contention
336 http://www.stardot.org.uk/forums/viewtopic.php?p=134109#p134109
337
338 RAM Integrated Circuits
339 -----------------------
340
341 Unicorn Electronics appears to offer 4164 RAM chips (as well as 6502 series
342 CPUs such as the 6502, 6502A, 6502B and 65C02). These 4164 devices are
343 available in 100ns (4164-100), 120ns (4164-120) and 150ns (4164-150) variants,
344 have 16 pins and address 65536 bits through a 1-bit wide channel. Similarly,
345 ByteDelight.com sell 4164 devices primarily for the ZX Spectrum.
346
347 The documentation for the Electron mentions 4164-15 RAM chips for IC4-7, and
348 the Samsung-produced KM41464 series is apparently equivalent to the Texas
349 Instruments 4164 chips presumably used in the Electron.
350
351 The TM4164EC4 series combines 4 64K x 1b units into a single package and
352 appears similar to the TM4164EA4 featured on the Electron's circuit diagram
353 (in the Advanced User Guide but not the Service Manual), and it also has 22
354 pins providing 3 additional inputs and 3 additional outputs over the 16 pins
355 of the individual 4164-15 modules, presumably allowing concurrent access to
356 the packaged memory units.
357
358 As far as currently available replacements are concerned, the NTE4164 is a
359 potential candidate: according to the Vetco Electronics entry, it is
360 supposedly a replacement for the TMS4164-15 amongst many other parts. Similar
361 parts include the NTE2164 and the NTE6664, both of which appear to have
362 largely the same performance and connection characteristics. Meanwhile, the
363 NTE21256 appears to be a 16-pin replacement with four times the capacity that
364 maintains the single data input and output pins. Using the NTE21256 as a
365 replacement for all ICs combined would be difficult because of the single bit
366 output.
367
368 Another device equivalent to the 4164-15 appears to be available under the
369 code 41662 from Jameco Electronics as the Siemens HYB 4164-2. The Jameco Web
370 site lists data sheets for other devices on the same page, but these are
371 different and actually appear to be provided under the 41574 product code (but
372 are listed under 41464-10) and appear to be replacements for the TM4164EC4:
373 the Samsung KM41464A-15 and NEC µPD41464 employ 18 pins, eliminating 4 pins by
374 employing 4 pins for both input and output.
375
376 Pins I/O pins Row access Column access
377 ---- -------- ---------- -------------
378 TM4164EC4 22 4 + 4 150ns (15) 90ns (15)
379 KM41464AP 18 4 150ns (15) 75ns (15)
380 NTE21256 16 1 + 1 150ns 75ns
381 HYB 4164-2 16 1 + 1 150ns 100ns
382 µPD41464 18 4 120ns (12) 60ns (12)
383
384 See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module
385 http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
386 See: Dynamic RAMS
387 http://www.unicornelectronics.com/IC/DYNAMIC.html
388 See: New old stock 8x 4164 chips
389 http://www.bytedelight.com/?product=8x-4164-chips-new-old-stock
390 See: KM4164B 64K x 1 Bit Dynamic RAM with Page Mode
391 http://images.ihscontent.net/vipimages/VipMasterIC/IC/SAMS/SAMSD020/SAMSD020-45.pdf
392 See: NTE2164 Integrated Circuit 65,536 X 1 Bit Dynamic Random Access Memory
393 http://www.vetco.net/catalog/product_info.php?products_id=2806
394 See: NTE4164 - IC-NMOS 64K DRAM 150NS
395 http://www.vetco.net/catalog/product_info.php?products_id=3680
396 See: NTE21256 - IC-256K DRAM 150NS
397 http://www.vetco.net/catalog/product_info.php?products_id=2799
398 See: NTE21256 262,144-Bit Dynamic Random Access Memory (DRAM)
399 http://www.nteinc.com/specs/21000to21999/pdf/nte21256.pdf
400 See: NTE6664 - IC-MOS 64K DRAM 150NS
401 http://www.vetco.net/catalog/product_info.php?products_id=5213
402 See: NTE6664 Integrated Circuit 64K-Bit Dynamic RAM
403 http://www.nteinc.com/specs/6600to6699/pdf/nte6664.pdf
404 See: 4164-150: MAJOR BRANDS
405 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41662_-1
406 See: HYB 4164-1, HYB 4164-2, HYB 4164-3 65,536-Bit Dynamic Random Access Memory (RAM)
407 http://www.jameco.com/Jameco/Products/ProdDS/41662SIEMENS.pdf
408 See: KM41464A NMOS DRAM 64K x 4 Bit Dynamic RAM with Page Mode
409 http://www.jameco.com/Jameco/Products/ProdDS/41662SAM.pdf
410 See: NEC µ41464 65,536 x 4-Bit Dynamic NMOS RAM
411 http://www.jameco.com/Jameco/Products/ProdDS/41662NEC.pdf
412 See: 41464-10: MAJOR BRANDS
413 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41574_-1
414
415 Interrupts
416 ----------
417
418 The ULA generates IRQs (maskable interrupts) according to certain conditions
419 and these conditions are controlled by location &FE00:
420
421 * Vertical sync (bottom of displayed screen)
422 * 50MHz real time clock
423 * Transmit data empty
424 * Receive data full
425 * High tone detect
426
427 The ULA is also used to clear interrupt conditions through location &FE05. Of
428 particular significance is bit 7, which must be set if an NMI (non-maskable
429 interrupt) has occurred and has thus suspended ULA access to memory, restoring
430 the normal function of the ULA.
431
432 ROM Paging
433 ----------
434
435 Accessing different ROMs involves bits 0 to 3 of &FE05. Some special ROM
436 mappings exist:
437
438 8 keyboard
439 9 keyboard (duplicate)
440 10 BASIC ROM
441 11 BASIC ROM (duplicate)
442
443 Paging in a ROM involves the following procedure:
444
445 1. Assert ROM page enable (bit 3) together with a ROM number n in bits 0 to
446 2, corresponding to ROM number 8+n, such that one of ROMs 12 to 15 is
447 selected.
448 2. Where a ROM numbered from 0 to 7 is to be selected, set bit 3 to zero
449 whilst writing the desired ROM number n in bits 0 to 2.
450
451 See: http://stardot.org.uk/forums/viewtopic.php?p=136686#p136686
452
453 Keyboard Access
454 ---------------
455
456 The keyboard pages appear to be accessed at 1MHz just like the RAM.
457
458 See: https://stardot.org.uk/forums/viewtopic.php?p=254155#p254155
459
460 Shadow/Expanded Memory
461 ----------------------
462
463 The Electron exposes all sixteen address lines and all eight data lines
464 through the expansion bus. Using such lines, it is possible to provide
465 additional memory - typically sideways ROM and RAM - on expansion cards and
466 through cartridges, although the official cartridge specification provides
467 fewer address lines and only seeks to provide access to memory in 16K units.
468
469 Various modifications and upgrades were developed to offer "turbo"
470 capabilities to the Electron, permitting the CPU to access a separate 8K of
471 RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
472 the ULA through additional logic. However, an enhanced ULA might support
473 independent CPU access to memory over the expansion bus by allowing itself to
474 be discharged from providing access to memory, potentially for a range of
475 addresses, and for the CPU to communicate with external memory uninterrupted.
476
477 Sideways RAM/ROM and Upper Memory Access
478 ----------------------------------------
479
480 Although the ULA controls the CPU clock, effectively slowing or stopping the
481 CPU when the ULA needs to access screen memory, it is apparently able to allow
482 the CPU to access addresses of &8000 and above - the upper region of memory -
483 at 2MHz independently of any access to RAM that the ULA might be performing,
484 only blocking the CPU if it attempts to access addresses of &7FFF and below
485 during any ULA memory access - the lower region of memory - by stopping or
486 stalling its clock.
487
488 Thus, the ULA remains aware of the level of the A15 line, only inhibiting the
489 CPU clock if the line goes low, when the CPU is attempting to access the lower
490 region of memory.
491
492 Hardware Scrolling (and Enhancement)
493 ------------------------------------
494
495 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
496 the least significant 5 bits being zero, thus limiting the scrolling
497 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
498 using the same layout of these addresses.
499
500 |--&FE02--------------| |--&FE03--------------|
501 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
502
503 XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
504
505 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
506 memory to pixel locations is character oriented. A change in 8 bytes would
507 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
508 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
509 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
510 Guide).
511
512 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
513 of changing the screen address by 2 bytes is the change in the number of lines
514 from the initial and final character rows that need reading by the ULA, which
515 would need to maintain this state information (although this is a relatively
516 trivial change). Another pitfall is the complication that might be introduced
517 to software writing bitmaps of character height to the screen.
518
519 See: http://pastraiser.com/computers/acornelectron/acornelectron.html
520
521 Enhancement: Mode Layouts
522 -------------------------
523
524 Merely changing the screen memory mappings in order to have Archimedes-style
525 row-oriented screen addresses (instead of character-oriented addresses) could
526 be done for the existing modes, but this might not be sufficiently beneficial,
527 especially since accessing regions of the screen would involve incrementing
528 pointers by amounts that are inconvenient on an 8-bit CPU.
529
530 However, instead of using a Archimedes-style mapping, column-oriented screen
531 addresses could be more feasibly employed: incrementing the address would
532 reference the vertical screen location below the currently-referenced location
533 (just as occurs within characters using the existing ULA); instead of
534 returning to the top of the character row and referencing the next horizontal
535 location after eight bytes, the address would reference the next character row
536 and continue to reference locations downwards over the height of the screen
537 until reaching the bottom; at the bottom, the next location would be the next
538 horizontal location at the top of the screen.
539
540 In other words, the memory layout for the screen would resemble the following
541 (for MODE 2):
542
543 &3000 &3100 ... &7F00
544 &3001 &3101
545 ... ...
546 &3007
547 &3008
548 ...
549 ... ...
550 &30FF ... &7FFF
551
552 Since there are 256 pixel rows, each column of locations would be addressable
553 using the low byte of the address. Meanwhile, the high byte would be
554 incremented to address different columns. Thus, addressing screen locations
555 would become a lot more convenient and potentially much more efficient for
556 certain kinds of graphical output.
557
558 One potential complication with this simplified addressing scheme arises with
559 hardware scrolling. Vertical hardware scrolling by one pixel row (not supported
560 with the existing ULA) would be achieved by incrementing or decrementing the
561 screen start address; by one character row, it would involve adding or
562 subtracting 8. However, the ULA only supports multiples of 64 when changing the
563 screen start address. Thus, if such a scheme were to be adopted, three
564 additional bits would need to be supported in the screen start register (see
565 "Hardware Scrolling (and Enhancement)" for more details). However, horizontal
566 scrolling would be much improved even under the severe constraints of the
567 existing ULA: only adjustments of 256 to the screen start address would be
568 required to produce single-location scrolling of as few as two pixels in MODE 2
569 (four pixels in MODEs 1 and 5, eight pixels otherwise).
570
571 More disruptive is the effect of this alternative layout on software.
572 Presumably, compatibility with the BBC Micro was the primary goal of the
573 Electron's hardware design. With the character-oriented screen layout in
574 place, system software (and application software accessing the screen
575 directly) would be relying on this layout to run on the Electron with little
576 or no modification. Although it might have been possible to change the system
577 software to use this column-oriented layout instead, this would have incurred
578 a development cost and caused additional work porting things like games to the
579 Electron. Moreover, a separate branch of the software from that supporting the
580 BBC Micro and closer derivatives would then have needed maintaining.
581
582 The decision to use the character-oriented layout in the BBC Micro may have
583 been related to the choice of circuitry and to facilitate a convenient
584 hardware implementation, and by the time the Electron was planned, it was too
585 late to do anything about this somewhat unfortunate choice.
586
587 Pixel Layouts
588 -------------
589
590 The pixel layouts are as follows:
591
592 Modes Depth (bpp) Pixels (from bits)
593 ----- ----------- ------------------
594 0, 3, 4, 6 1 7 6 5 4 3 2 1 0
595 1, 5 2 73 62 51 40
596 2 4 7531 6420
597
598 Since the ULA reads a half-byte at a time, one might expect it to attempt to
599 produce pixels for every half-byte, as opposed to handling entire bytes.
600 However, the pixel layout is not conducive to producing pixels as soon as a
601 half-byte has been read for a given full-byte location: in 1bpp modes the
602 first four pixels can indeed be produced, but in 2bpp and 4bpp modes the pixel
603 data is spread across the entire byte in different ways.
604
605 An alternative arrangement might be as follows:
606
607 Modes Depth (bpp) Pixels (from bits)
608 ----- ----------- ------------------
609 0, 3, 4, 6 1 7 6 5 4 3 2 1 0
610 1, 5 2 76 54 32 10
611 2 4 7654 3210
612
613 Just as the mode layouts were presumably decided by compatibility with the BBC
614 Micro, the pixel layouts will have been maintained for similar reasons.
615 Unfortunately, this layout prevents any optimisation of the ULA for handling
616 half-byte pixel data generally.
617
618 Enhancement: The Missing MODE 4
619 -------------------------------
620
621 The Electron inherits its screen mode selection from the BBC Micro, where MODE
622 3 is a text version of MODE 0, and where MODE 6 is a text version of MODE 4.
623 Neither MODE 3 nor MODE 6 is a genuine character-based text mode like MODE 7,
624 however, and they are merely implemented by skipping two scanlines in every
625 ten after the eight required to produce a character line. Thus, such modes
626 provide a 24-row display.
627
628 In principle, nothing prevents this "text mode" effect being applied to other
629 modes. The 20-column modes are not well-suited to displaying text, which
630 leaves MODE 1 which, unlike MODEs 3 and 6, can display 4 colours rather than
631 2. Although the need for a non-monochrome 40-column text mode is addressed by
632 MODE 7 on the BBC Micro, the Electron lacks such a mode.
633
634 If the 4-colour, 24-row variant of MODE 1 were to be provided, logically it
635 would occupy MODE 4 instead of the current MODE 4:
636
637 Screen mode Size (kilobytes) Colours Rows Resolution
638 ----------- ---------------- ------- ---- ----------
639 0 20 2 32 640x256
640 1 20 4 32 320x256
641 2 20 16 32 160x256
642 3 16 2 24 640x256
643 4 (new) 16 4 24 320x256
644 4 (old) 10 2 32 320x256
645 5 10 4 32 160x256
646 6 8 2 24 320x256
647
648 Thus, for increasing mode numbers, the size of each mode would be the same or
649 less than the preceding mode.
650
651 Enhancement: 2MHz RAM Access
652 ----------------------------
653
654 Given that the CPU and ULA both access RAM at 2MHz, but given that the CPU
655 when not competing with the ULA only accesses RAM every other 2MHz cycle (as
656 if the ULA still needed to access the RAM), one useful enhancement would be a
657 mechanism to let the CPU take over the ULA cycles outside the ULA's period of
658 activity comparable to the way the ULA takes over the CPU cycles in MODE 0 to
659 3.
660
661 Thus, the RAM access cycles would resemble the following in MODE 0 to 3:
662
663 Upon a transition from display cycles: UUUUCCCC (instead of UUUUC_C_)
664 On a non-display line: CCCCCCCC (instead of C_C_C_C_)
665
666 In MODE 4 to 6:
667
668 Upon a transition from display cycles: CUCUCCCC (instead of CUCUC_C_)
669 On a non-display line: CCCCCCCC (instead of C_C_C_C_)
670
671 This would improve CPU bandwidth as follows:
672
673 Standard ULA Enhanced ULA % Total Bandwidth Speedup
674 MODE 0, 1, 2 9728 bytes 19456 bytes 24% -> 49% 2
675 MODE 3 12288 bytes 24576 bytes 31% -> 62% 2
676 MODE 4, 5 19968 bytes 29696 bytes 50% -> 74% 1.5
677 MODE 6 19968 bytes 32256 bytes 50% -> 81% 1.6
678
679 (Here, the uncontended total 2MHz bandwidth for a display period would be
680 39936 bytes, being 128 cycles per line over 312 lines.)
681
682 With such an enhancement, MODE 0 to 3 experience a doubling of CPU bandwidth
683 because all access opportunities to RAM are doubled. Meanwhile, in the other
684 modes, some CPU accesses occur alongside ULA accesses and thus cannot be
685 doubled, but the CPU bandwidth increase is still significant.
686
687 Unfortunately, the mechanism for accessing the RAM is too slow to provide data
688 within the time constraints of 2MHz operation. There is no time remaining in a
689 2MHz cycle for the CPU to receive and process any retrieved data once the
690 necessary signalling has been performed. The only way for the CPU to be able
691 to access the RAM quickly enough would be to do away with the double 4-bit
692 access mechanism and to have a single 8-bit channel to the memory. This would
693 require twice as many 1-bit RAM chips or a different kind of RAM chip, but it
694 would also potentially simplify the ULA.
695
696 Enhancement: Region Blanking
697 ----------------------------
698
699 The problem of permitting character-oriented blitting in programs whilst
700 scrolling the screen by sub-character amounts could be mitigated by permitting
701 a region of the display to be blank, such as the final lines of the display.
702 Consider the following vertical scrolling by 2 bytes that would cause an
703 initial character row of 6 lines and a final character row of 2 lines:
704
705 6 lines - initial, partial character row
706 248 lines - 31 complete rows
707 2 lines - final, partial character row
708
709 If a routine were in use that wrote 8 line bitmaps to the partial character
710 row now split in two, it would be advisable to hide one of the regions in
711 order to prevent content appearing in the wrong place on screen (such as
712 content meant to appear at the top "leaking" onto the bottom). Blanking 6
713 lines would be sufficient, as can be seen from the following cases.
714
715 Scrolling up by 2 lines:
716
717 6 lines - initial, partial character row
718 240 lines - 30 complete rows
719 4 lines - part of 1 complete row
720 -----------------------------------------------------------------
721 4 lines - part of 1 complete row (hidden to maintain 250 lines)
722 2 lines - final, partial character row (hidden)
723
724 Scrolling down by 2 lines:
725
726 2 lines - initial, partial character row
727 248 lines - 31 complete rows
728 ----------------------------------------------------------
729 6 lines - final, partial character row (hidden)
730
731 Thus, in this case, region blanking would impose a 250 line display with the
732 bottom 6 lines blank.
733
734 See the description of the display suspend enhancement for a more efficient
735 way of blanking lines than merely blanking the palette whilst allowing the CPU
736 to perform useful work during the blanking period.
737
738 To control the blanking or suspending of lines at the top and bottom of the
739 display, a memory location could be dedicated to the task: the upper 4 bits
740 could define a blanking region of up to 16 lines at the top of the screen,
741 whereas the lower 4 bits could define such a region at the bottom of the
742 screen. If more lines were required, two locations could be employed, allowing
743 the top and bottom regions to occupy the entire screen.
744
745 Enhancement: Screen Height Adjustment
746 -------------------------------------
747
748 The height of the screen could be configurable in order to reduce screen
749 memory consumption. This is not quite done in MODE 3 and 6 since the start of
750 the screen appears to be rounded down to the nearest page, but by reducing the
751 height by amounts more than a page, savings would be possible. For example:
752
753 Screen width Depth Height Bytes per line Saving in bytes Start address
754 ------------ ----- ------ -------------- --------------- -------------
755 640 1 252 80 320 &3140 -> &3100
756 640 1 248 80 640 &3280 -> &3200
757 320 1 240 40 640 &5A80 -> &5A00
758 320 2 240 80 1280 &3500
759
760 Screen Mode Selection
761 ---------------------
762
763 Bits 3, 4 and 5 of address &FE*7 control the selected screen mode. For a wider
764 range of modes, the other bits of &FE*7 (related to sound, cassette
765 input/output and the Caps Lock LED) would need to be reassigned and bit 0
766 potentially being made available for use.
767
768 Enhancement: Palette Definition
769 -------------------------------
770
771 Since all memory accesses go via the ULA, an enhanced ULA could employ more
772 specific addresses than &FE*X to perform enhanced functions. For example, the
773 palette control is done using &FE*8-F and merely involves selecting predefined
774 colours, whereas an enhanced ULA could support the redefinition of all 16
775 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
776 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
777 specifications similar to those used on the Archimedes.
778
779 The principal limitation here is actually the hardware: the Electron has only
780 a single output line for each of the red, green and blue channels, and if
781 those outputs are strictly digital and can only be set to a "high" and "low"
782 value, then only the existing eight colours are possible. If a modern ULA were
783 able to output analogue values (or values at well-defined points between the
784 high and low values, such as the half-on value supported by the Amstrad CPC
785 series), it would still need to be assessed whether the circuitry could
786 successfully handle and propagate such values. Various sources indicate that
787 only "TTL levels" are supported by the RGB output circuit, and since there are
788 74LS08 AND logic gates involved in the RGB component outputs from the ULA, it
789 is likely that the ULA is expected to provide only "high" or "low" values.
790
791 Short of adding extra outputs from the ULA (either additional red, green and
792 blue outputs or a combined intensity output), another approach might involve
793 some kind of modulation where an output value might be encoded in multiple
794 pulses at a higher frequency than the pixel frequency. However, this would
795 demand additional circuitry outside the ULA, and component RGB monitors would
796 probably not be able to take advantage of this feature; only UHF and composite
797 video devices (the latter with the composite video colour support enabled on
798 the Electron's circuit board) would potentially benefit.
799
800 Flashing Colours
801 ----------------
802
803 According to the Advanced User Guide, "The cursor and flashing colours are
804 entirely generated in software: This means that all of the logical to physical
805 colour map must be changed to cause colours to flash." This appears to suggest
806 that the palette registers must be updated upon the flash counter - read and
807 written by OSBYTE &C1 (193) - reaching zero and that some way of changing the
808 colour pairs to be any combination of colours might be possible, instead of
809 having colour complements as pairs.
810
811 It is conceivable that the interrupt code responsible does the simple thing
812 and merely inverts the current values for any logical colours (LC) for which
813 the associated physical colour (as supplied as the second parameter to the VDU
814 19 call) has the top bit of its four bit value set. These top bits are not
815 recorded in the palette registers but are presumably recorded separately and
816 used to build bitmaps as follows:
817
818 LC 2 colour 4 colour 16 colour 4-bit value for inversion
819 -- -------- -------- --------- -------------------------
820 0 00010001 00010001 00010001 1, 1, 1
821 1 01000100 00100010 00010001 4, 2, 1
822 2 01000100 00100010 4, 2
823 3 10001000 00100010 8, 2
824 4 00010001 1
825 5 00010001 1
826 6 00100010 2
827 7 00100010 2
828 8 01000100 4
829 9 01000100 4
830 10 10001000 8
831 11 10001000 8
832 12 01000100 4
833 13 01000100 4
834 14 10001000 8
835 15 10001000 8
836
837 Inversion value calculation:
838
839 2 colour formula: 1 << (colour * 2)
840 4 colour formula: 1 << colour
841 16 colour formula: 1 << ((colour & 2) + ((colour & 8) * 2))
842
843 For example, where logical colour 0 has been mapped to a physical colour in
844 the range 8 to 15, a bitmap of 00010001 would be chosen as its contribution to
845 the inversion operation. (The lower three bits of the physical colour would be
846 used to set the underlying colour information affected by the inversion
847 operation.)
848
849 An operation in the interrupt code would then combine the bitmaps for all
850 logical colours in 2 and 4 colour modes, with the 16 colour bitmaps being
851 combined for groups of logical colours as follows:
852
853 Logical colours
854 ---------------
855 0, 2, 8, 10
856 4, 6, 12, 14
857 5, 7, 13, 15
858 1, 3, 9, 11
859
860 These combined bitmaps would be EORed with the existing palette register
861 values in order to perform the value inversion necessary to produce the
862 flashing effect.
863
864 Thus, in the VDU 19 operation, the appropriate inversion value would be
865 calculated for the logical colour, and this value would then be combined with
866 other inversion values in a dedicated memory location corresponding to the
867 colour's group as indicated above. Meanwhile, the palette channel values would
868 be derived from the lower three bits of the specified physical colour and
869 combined with other palette data in dedicated memory locations corresponding
870 to the palette registers.
871
872 Interestingly, although flashing colours on the BBC Micro are controlled by
873 toggling bit 0 of the &FE20 control register location for the Video ULA, the
874 actual colour inversion is done in hardware.
875
876 Enhancement: Palette Definition Lists
877 -------------------------------------
878
879 It can be useful to redefine the palette in order to change the colours
880 available for a particular region of the screen, particularly in modes where
881 the choice of colours is constrained, and if an increased colour depth were
882 available, palette redefinition would be useful to give the illusion of more
883 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
884 by using interrupt-driven timers, but a more efficient approach would involve
885 presenting lists of palette definitions to the ULA so that it can change the
886 palette at a particular display line.
887
888 One might define a palette redefinition list in a region of memory and then
889 communicate its contents to the ULA by writing the address and length of the
890 list, along with the display line at which the palette is to be changed, to
891 ULA registers such that the ULA buffers the list and performs the redefinition
892 at the appropriate time. Throughput/bandwidth considerations might impose
893 restrictions on the practical length of such a list, however.
894
895 Enhancement: Display Synchronisation Interrupts
896 -----------------------------------------------
897
898 When completing each scanline of the display, the ULA could trigger an
899 interrupt. Since this might impact system performance substantially, the
900 feature would probably need to be configurable, and it might be sufficient to
901 have an interrupt only after a certain number of display lines instead.
902 Permitting the CPU to take action after eight lines would allow palette
903 switching and other effects to occur on a character row basis.
904
905 The ULA provides an interrupt at the end of the display period, presumably so
906 that software can schedule updates to the screen, avoid flickering or tearing,
907 and so on. However, some applications might benefit from an interrupt at, or
908 just before, the start of the display period so that palette modifications or
909 similar effects could be scheduled.
910
911 Enhancement: Palette-Free Modes
912 -------------------------------
913
914 Palette-free modes might be defined where bit values directly correspond to
915 the red, green and blue channels, although this would mostly make sense only
916 for modes with depths greater than the standard 4 bits per pixel, and such
917 modes would require more memory than MODE 2 if they were to have an acceptable
918 resolution.
919
920 Enhancement: Display Suspend
921 ----------------------------
922
923 Especially when writing to the screen memory, it could be beneficial to be
924 able to suspend the ULA's access to the memory, instead producing blank values
925 for all screen pixels until a program is ready to reveal the screen. This is
926 different from palette blanking since with a blank palette, the ULA is still
927 reading screen memory and translating its contents into pixel values that end
928 up being blank.
929
930 This function is reminiscent of a capability of the ZX81, albeit necessary on
931 that hardware to reduce the load on the system CPU which was responsible for
932 producing the video output. By allowing display suspend on the Electron, the
933 performance benefit would be derived from giving the CPU full access to the
934 memory bandwidth.
935
936 The region blanking feature mentioned above could be implemented using this
937 enhancement instead of employing palette blanking for the affected lines of
938 the display.
939
940 Enhancement: Memory Filling
941 ---------------------------
942
943 A capability that could be given to an enhanced ULA is that of permitting the
944 ULA to write to screen memory as well being able to read from it. Although
945 such a capability would probably not be useful in conjunction with the
946 existing read operations when producing a screen display, and insufficient
947 bandwidth would exist to do so in high-bandwidth screen modes anyway, the
948 capability could be offered during a display suspend period (as described
949 above), permitting a more efficient mechanism to rapidly fill memory with a
950 predetermined value.
951
952 This capability could also support block filling, where the limits of the
953 filled memory would be defined by the position and size of a screen area,
954 although this would demand the provision of additional registers in the ULA to
955 retain the details of such areas and additional logic to control the fill
956 operation.
957
958 Enhancement: Region Filling
959 ---------------------------
960
961 An alternative to memory writing might involve indicating regions using
962 additional registers or memory where the ULA fills regions of the screen with
963 content instead of reading from memory. Unlike hardware sprites which should
964 realistically provide varied content, region filling could employ single
965 colours or patterns, and one advantage of doing so would be that the ULA need
966 not access memory at all within a particular region.
967
968 Regions would be defined on a row-by-row basis. Instead of reading memory and
969 blitting a direct representation to the screen, the ULA would read region
970 definitions containing a start column, region width and colour details. There
971 might be a certain number of definitions allowed per row, or the ULA might
972 just traverse an ordered list of such definitions with each one indicating the
973 row, start column, region width and colour details.
974
975 One could even compress this information further by requiring only the row,
976 start column and colour details with each subsequent definition terminating
977 the effect of the previous one. However, one would also need to consider the
978 convenience of preparing such definitions and whether efficient access to
979 definitions for a particular row might be desirable. It might also be
980 desirable to avoid having to prepare definitions for "empty" areas of the
981 screen, effectively making the definition of the screen contents employ
982 run-length encoding and employ only colour plus length information.
983
984 One application of region filling is that of simple 2D and 3D shape rendering.
985 Although it is entirely possible to plot such shapes to the screen and have
986 the ULA blit the memory contents to the screen, such operations consume
987 bandwidth both in the initial plotting and in the final transfer to the
988 screen. Region filling would reduce such bandwidth usage substantially.
989
990 This way of representing screen images would make certain kinds of images
991 unfeasible to represent - consider alternating single pixel values which could
992 easily occur in some character bitmaps - even if an internal queue of regions
993 were to be supported such that the ULA could read ahead and buffer such
994 "bandwidth intensive" areas. Thus, the ULA might be better served providing
995 this feature for certain areas of the display only as some kind of special
996 graphics window.
997
998 Enhancement: Hardware Sprites
999 -----------------------------
1000
1001 An enhanced ULA might provide hardware sprites, but this would be done in an
1002 way that is incompatible with the standard ULA, since no &FE*X locations are
1003 available for allocation. To keep the facility simple, hardware sprites would
1004 have a standard byte width and height.
1005
1006 The specification of sprites could involve the reservation of 16 locations
1007 (for example, &FE20-F) specifying a fixed number of eight sprites, with each
1008 location pair referring to the sprite data. By limiting the ULA to dealing
1009 with a fixed number of sprites, the work required inside the ULA would be
1010 reduced since it would avoid having to deal with arbitrary numbers of sprites.
1011
1012 The principal limitation on providing hardware sprites is that of having to
1013 obtain sprite data, given that the ULA is usually required to retrieve screen
1014 data, and given the lack of memory bandwidth available to retrieve sprite data
1015 (particularly from multiple sprites supposedly at the same position) and
1016 screen data simultaneously. Although the ULA could potentially read sprite
1017 data and screen data in alternate memory accesses in screen modes where the
1018 bandwidth is not already fully utilised, this would result in a degradation of
1019 performance.
1020
1021 Enhancement: Additional Screen Mode Configurations
1022 --------------------------------------------------
1023
1024 Alternative screen mode configurations could be supported. The ULA has to
1025 produce 640 pixel values across the screen, with pixel doubling or quadrupling
1026 employed to fill the screen width:
1027
1028 Screen width Columns Scaling Depth Bytes
1029 ------------ ------- ------- ----- -----
1030 640 80 x1 1 80
1031 320 40 x2 1, 2 40, 80
1032 160 20 x4 2, 4 40, 80
1033
1034 It must also use at most 80 byte-sized memory accesses to provide the
1035 information for the display. Given that characters must occupy an 8x8 pixel
1036 array, if a configuration featuring anything other than 20, 40 or 80 character
1037 columns is to be supported, compromises must be made such as the introduction
1038 of blank pixels either between characters (such as occurs between rows in MODE
1039 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
1040 in MODE 3 and 6). Consider the following configuration:
1041
1042 Screen width Columns Scaling Depth Bytes Blank
1043 ------------ ------- ------- ----- ------ -----
1044 208 26 x3 1, 2 26, 52 16
1045
1046 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
1047 colours could be provided, with 16 blank pixel values (out of a total of 640)
1048 generated either at the start or end (or split between the start and end) of
1049 each scanline.
1050
1051 Enhancement: Character Attributes
1052 ---------------------------------
1053
1054 The BBC Micro MODE 7 employs something resembling character attributes to
1055 support teletext displays, but depends on circuitry providing a character
1056 generator. The ZX Spectrum, on the other hand, provides character attributes
1057 as a means of colouring bitmapped graphics. Although such a feature is very
1058 limiting as the sole means of providing multicolour graphics, in situations
1059 where the choice is between low resolution multicolour graphics or high
1060 resolution monochrome graphics, character attributes provide a potentially
1061 useful compromise.
1062
1063 For each byte read, the ULA must deliver 8 pixel values (out of a total of
1064 640) to the video output, doing so by either emptying its pixel buffer on a
1065 pixel per cycle basis, or by multiplying pixels and thus holding them for more
1066 than one cycle. For example for a screen mode having 640 pixels in width:
1067
1068 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1069 Reads: B B
1070 Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
1071
1072 And for a screen mode having 320 pixels in width:
1073
1074 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1075 Reads: B
1076 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
1077
1078 However, in modes where less than 80 bytes are required to generate the pixel
1079 values, an enhanced ULA might be able to read additional bytes between those
1080 providing the bitmapped graphics data:
1081
1082 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1083 Reads: B A
1084 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
1085
1086 These additional bytes could provide colour information for the bitmapped data
1087 in the following character column (of 8 pixels). Since it would be desirable
1088 to apply attribute data to the first column, the initial 8 cycles might be
1089 configured to not produce pixel values.
1090
1091 For an entire character, attribute data need only be read for the first row of
1092 pixels for a character. The subsequent rows would have attribute information
1093 applied to them, although this would require the attribute data to be stored
1094 in some kind of buffer. Thus, the following access pattern would be observed:
1095
1096 Reads: A B _ B _ B _ B _ B _ B _ B _ B ...
1097
1098 In modes 3 and 6, the blank display lines could be used to retrieve attribute
1099 data:
1100
1101 Reads (blank): A _ A _ A _ A _ A _ A _ A _ A _ ...
1102 Reads (active): B _ B _ B _ B _ B _ B _ B _ B _ ...
1103 Reads (active): B _ B _ B _ B _ B _ B _ B _ B _ ...
1104 ...
1105
1106 See below for a discussion of using this for character data as well.
1107
1108 A whole byte used for colour information for a whole character would result in
1109 a choice of 256 colours, and this might be somewhat excessive. By only reading
1110 attribute bytes at every other opportunity, a choice of 16 colours could be
1111 applied individually to two characters.
1112
1113 Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
1114 Reads: B A B -
1115 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
1116
1117 Further reductions in attribute data access, offering 4 colours for every
1118 character in a four character block, for example, might also be worth
1119 considering.
1120
1121 Consider the following configurations for screen modes with a colour depth of
1122 1 bit per pixel for bitmap information:
1123
1124 Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
1125 ------------ ------- ------- --------- --------- ------- ------------
1126 320 40 x2 40 40 256 &5300
1127 320 40 x2 40 20 16 &5580 -> &5500
1128 320 40 x2 40 10 4 &56C0 -> &5600
1129 208 26 x3 26 26 256 &62C0 -> &6200
1130 208 26 x3 26 13 16 &6460 -> &6400
1131
1132 Enhancement: Text-Only Modes using Character and Attribute Data
1133 ---------------------------------------------------------------
1134
1135 In modes 3 and 6, the blank display lines could be used to retrieve character
1136 and attribute data instead of trying to insert it between bitmap data accesses,
1137 but this data would then need to be retained:
1138
1139 Reads: A C A C A C A C A C A C A C A C ...
1140 Reads: B _ B _ B _ B _ B _ B _ B _ B _ ...
1141
1142 Only attribute (A) and character (C) reads would require screen memory
1143 storage. Bitmap data reads (B) would involve either accesses to memory to
1144 obtain character definition details or could, at the cost of special storage
1145 in the ULA, involve accesses within the ULA that would then free up the RAM.
1146 However, the CPU would not benefit from having any extra access slots due to
1147 the limitations of the RAM access mechanism.
1148
1149 A scheme without caching might be possible. The same line of memory addresses
1150 might be visited over and over again for eight display lines, with an index
1151 into the bitmap data being incremented from zero to seven. The access patterns
1152 would look like this:
1153
1154 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 0)
1155 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 1)
1156 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 2)
1157 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 3)
1158 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 4)
1159 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 5)
1160 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 6)
1161 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 7)
1162
1163 The bandwidth requirements would be the sum of the accesses to read the
1164 character values (repeatedly) and those to read the bitmap data to reproduce
1165 the characters on screen.
1166
1167 Enhancement: MODE 7 Emulation using Character Attributes
1168 --------------------------------------------------------
1169
1170 If the scheme of applying attributes to character regions were employed to
1171 emulate MODE 7, in conjunction with the MODE 6 display technique, the
1172 following configuration would be required:
1173
1174 Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
1175 ------------ ------- ---- --------- --------- ------- ------------
1176 320 40 25 40 20 16 &5ECC -> &5E00
1177 320 40 25 40 10 4 &5FC6 -> &5F00
1178
1179 Although this requires much more memory than MODE 7 (8500 bytes versus MODE
1180 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
1181 at least make a limited 40-column multicolour mode available as a substitute
1182 for MODE 7.
1183
1184 Using the text-only enhancement with caching of data or with repeated reads of
1185 the same character data line for eight display lines, the storage requirements
1186 would be diminished substantially:
1187
1188 Screen width Columns Rows Bytes (C) Bytes (A) Colours Screen start
1189 ------------ ------- ---- --------- --------- ------- ------------
1190 320 40 25 40 20 16 &7A94 -> &7A00
1191 320 40 25 40 10 4 &7B1E -> &7B00
1192 320 40 25 40 5 2 &7B9B -> &7B00
1193 320 40 25 40 0 (2) &7C18 -> &7C00
1194 640 80 25 80 40 16 &7448 -> &7400
1195 640 80 25 80 20 4 &763C -> &7600
1196 640 80 25 80 10 2 &7736 -> &7700
1197 640 80 25 80 0 (2) &7830 -> &7800
1198
1199 Note that the colours describe the locally defined attributes for each
1200 character. When no attribute information is provided, the colours are defined
1201 globally.
1202
1203 Enhancement: Compressed Character Data
1204 --------------------------------------
1205
1206 Another observation about text-only modes is that they only need to store a
1207 restricted set of bitmapped data values. Encoding this set of values in a
1208 smaller unit of storage than a byte could possibly help to reduce the amount
1209 of storage and bandwidth required to reproduce the characters on the display.
1210
1211 Enhancement: High Resolution Graphics
1212 -------------------------------------
1213
1214 Screen modes with higher resolutions and larger colour depths might be
1215 possible, but this would in most cases involve the allocation of more screen
1216 memory, and the ULA would probably then be obliged to page in such memory for
1217 the CPU to be able to sensibly access it all.
1218
1219 Enhancement: Genlock Support
1220 ----------------------------
1221
1222 The ULA generates a video signal in conjunction with circuitry producing the
1223 output features necessary for the correct display of the screen image.
1224 However, it appears that the ULA drives the video synchronisation mechanism
1225 instead of reacting to an existing signal. Genlock support might be possible
1226 if the ULA were made to be responsive to such external signals, resetting its
1227 address generators upon receiving synchronisation events.
1228
1229 Enhancement: Improved Sound
1230 ---------------------------
1231
1232 The standard ULA reserves &FE*6 for sound generation and cassette input/output
1233 (with bits 1 and 2 of &FE*7 being used to select either sound generation or
1234 cassette I/O), thus making it impossible to support multiple channels within
1235 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
1236 and an enhanced ULA could adopt this interface.
1237
1238 The BBC Micro uses the SN76489 chip to produce sound, and the entire
1239 functionality of this chip could be emulated for enhanced sound, with a subset
1240 of the functionality exposed via the &FE*6 interface.
1241
1242 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
1243 See: http://www.smspower.org/Development/SN76489
1244
1245 Enhancement: Waveform Upload
1246 ----------------------------
1247
1248 As with a hardware sprite function, waveforms could be uploaded or referenced
1249 using locations as registers referencing memory regions.
1250
1251 Enhancement: Sound Input/Output
1252 -------------------------------
1253
1254 Since the ULA already controls audio input/output for cassette-based data, it
1255 would have been interesting to entertain the idea of sampling and output of
1256 sounds through the cassette interface. However, a significant amount of
1257 circuitry is employed to process the input signal for use by the ULA and to
1258 process the output signal for recording.
1259
1260 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw_03.htm#3.11
1261
1262 Enhancement: BBC ULA Compatibility
1263 ----------------------------------
1264
1265 Although some new ULA functions could be defined in a way that is also
1266 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
1267 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
1268 map, but controls various functions specific to the 6845 video controller;
1269 &FE08-F is reserved for the serial controller. It therefore becomes possible
1270 to disregard compatibility where compatibility is already disregarded for a
1271 particular area of functionality.
1272
1273 &FE20-F maps to video ULA functionality on the BBC Micro which provides
1274 control over the palette (using address &FE21, compared to &FE07-F on the
1275 Electron) and other system-specific functions. Since the location usage is
1276 generally incompatible, this region could be reused for other purposes.
1277
1278 Enhancement: Increased RAM, ULA and CPU Performance
1279 ---------------------------------------------------
1280
1281 More modern implementations of the hardware might feature faster RAM coupled
1282 with an increased ULA clock frequency in order to increase the bandwidth
1283 available to the ULA and to the CPU in situations where the ULA is not needed
1284 to perform work. A ULA employing a 32MHz clock would be able to complete the
1285 retrieval of a byte from RAM in only 250ns and thus be able to enable the CPU
1286 to access the RAM for the following 250ns even in display modes requiring the
1287 retrieval of a byte for the display every 500ns. The CPU could, subject to
1288 timing issues, run at 2MHz even in MODE 0, 1 and 2.
1289
1290 A scheme such as that described above would have a similar effect to the
1291 scheme employed in the BBC Micro, although the latter made use of RAM with a
1292 wider bandwidth in order to complete memory transfers within 250ns and thus
1293 permit the CPU to run continuously at 2MHz.
1294
1295 Higher bandwidth could potentially be used to implement exotic features such
1296 as RAM-resident hardware sprites or indeed any feature demanding RAM access
1297 concurrent with the production of the display image.
1298
1299 Enhancement: Multiple CPU Stacks and Zero Pages
1300 -----------------------------------------------
1301
1302 The 6502 maintains a stack for subroutine calls and register storage in page
1303 &01. Although the stack register can be manipulated using the TSX and TXS
1304 instructions, thereby permitting the maintenance of multiple stack regions and
1305 thus the potential coexistence of multiple programs each using a separate
1306 region, only programs that make little use of the stack (perhaps avoiding
1307 deeply-nested subroutine invocations and significant register storage) would
1308 be able to coexist without overwriting each other's stacks.
1309
1310 One way that this issue could be alleviated would involve the provision of a
1311 facility to redirect accesses to page &01 to other areas of memory. The ULA
1312 would provide a register that defines a physical page for the use of the CPU's
1313 "logical" page &01, and upon any access to page &01 by the CPU, the ULA would
1314 change the asserted address lines to redirect the access to the appropriate
1315 physical region.
1316
1317 By providing an 8-bit register, mapping to the most significant byte (MSB) of
1318 a 16-bit address, the ULA could then replace any MSB equal to &01 with the
1319 register value before the access is made. Where multiple programs coexist,
1320 upon switching programs, the register would be updated to point the ULA to the
1321 appropriate stack location, thus providing a simple memory management unit
1322 (MMU) capability.
1323
1324 In a similar fashion, zero page accesses could also be redirected so that code
1325 could run from sideways RAM and have zero page operations redirected to "upper
1326 memory" - for example, to page &BE (with stack accesses redirected to page
1327 &BF, perhaps) - thereby permitting most CPU operations to occur without
1328 inadvertent accesses to "lower memory" (the RAM) which would risk stalling the
1329 CPU as it contends with the ULA for memory access.
1330
1331 Such facilities could also be provided by a separate circuit between the CPU
1332 and ULA in a fashion similar to that employed by a "turbo" board, but unlike
1333 such boards, no additional RAM would be provided: all memory accesses would
1334 occur as normal through the ULA, albeit redirected when configured
1335 appropriately.
1336
1337 ULA Pin Functions
1338 -----------------
1339
1340 The functions of the ULA pins are described in the Electron Service Manual. Of
1341 interest to video processing are the following:
1342
1343 CSYNC (low during horizontal or vertical synchronisation periods, high
1344 otherwise)
1345
1346 HS (low during horizontal synchronisation periods, high otherwise)
1347
1348 RED, GREEN, BLUE (pixel colour outputs)
1349
1350 CLOCK IN (a 16MHz clock input, 4V peak to peak)
1351
1352 PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
1353
1354 More general memory access pins:
1355
1356 RAM0...RAM3 (data lines to/from the RAM)
1357
1358 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
1359
1360 RAS (row address strobe setting the row address on a negative edge - see the
1361 timing notes)
1362
1363 CAS (column address strobe setting the column address on a negative edge -
1364 see the timing notes)
1365
1366 WE (sets write enable with logic 0, read with logic 1)
1367
1368 ROM (select data access from ROM)
1369
1370 CPU-oriented memory access pins:
1371
1372 A0...A15 (CPU address lines)
1373
1374 PD0...PD7 (CPU data lines)
1375
1376 R/W (indicates CPU write with logic 0, CPU read with logic 1)
1377
1378 Interrupt-related pins:
1379
1380 NMI (CPU request for uninterrupted 1MHz access to memory)
1381
1382 IRQ (signal event to CPU)
1383
1384 POR (power-on reset, resetting the ULA on a positive edge and asserting the
1385 CPU's RST pin)
1386
1387 RST (master reset for the CPU signalled on power-up and by the Break key)
1388
1389 Keyboard-related pins:
1390
1391 KBD0...KBD3 (keyboard inputs)
1392
1393 CAPS LOCK (control status LED)
1394
1395 Sound-related pins:
1396
1397 SOUND O/P (sound output using internal oscillator)
1398
1399 Cassette-related pins:
1400
1401 CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
1402
1403 CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
1404
1405 CAS RC (detect high tone)
1406
1407 CAS MO (motor relay output)
1408
1409 ÷13 IN (~1200 baud clock input)
1410
1411 ULA Socket
1412 ----------
1413
1414 The socket used for the ULA is a 3M/TexTool 268-5400 68-pin socket.
1415
1416 References
1417 ----------
1418
1419 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw.htm
1420
1421 About this Document
1422 -------------------
1423
1424 The most recent version of this document and accompanying distribution should
1425 be available from the following location:
1426
1427 http://hgweb.boddie.org.uk/ULA
1428
1429 Copyright and licence information can be found in the docs directory of this
1430 distribution - see docs/COPYING.txt for more information.