1 The Acorn Electron ULA
2 ======================
3
4 Principal Design and Feature Constraints
5 ----------------------------------------
6
7 The features of the ULA are limited by the amount of time and resources that
8 can be allocated to each activity necessary to support such features given the
9 fundamental obligations of the unit. Maintaining a screen display based on the
10 contents of RAM itself requires the ULA to have exclusive access to such
11 hardware resources for a significant period of time. Whilst other elements of
12 the ULA can in principle run in parallel with this activity, they cannot also
13 access the RAM. Consequently, other features that might use the RAM must
14 accept a reduced allocation of that resource in comparison to a hypothetical
15 architecture where concurrent RAM access is possible.
16
17 Thus, the principal constraint for many features is bandwidth. The duration of
18 access to hardware resources is one aspect of this; the rate at which such
19 resources can be accessed is another. For example, the RAM is not fast enough
20 to support access more frequently than one byte per 2MHz cycle, and for screen
21 modes involving 80 bytes of screen data per scanline, there are no free cycles
22 for anything other than the production of pixel output during the active
23 scanline periods.
24
25 Timing
26 ------
27
28 According to 15.3.2 in the Advanced User Guide, there are 312 scanlines, 256
29 of which are used to generate pixel data. At 50Hz, this means that 128 cycles
30 are spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
31 312 ~= 128 cycles). This is consistent with the observation that each scanline
32 requires at most 80 bytes of data, and that the ULA is apparently busy for 40
33 out of 64 microseconds in each scanline.
34
35 (In fact, since the ULA is seeking to provide an image for an interlaced
36 625-line display, there are in fact two "fields" involved, one providing 312
37 scanlines and one providing 313 scanlines. See below for a description of the
38 video system.)
39
40 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
41 each providing two bits of each byte) using two cycles within the 500ns period
42 of the 2MHz clock to complete each access operation. Since the CPU and ULA
43 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
44 effectively run at 1MHz (since every other 500ns period involves the ULA
45 accessing RAM). The CPU is driven by an external clock (IC8) whose 16MHz
46 frequency is divided by the ULA (IC1) depending on the screen mode in use.
47
48 Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
49 patterns corresponding to 16MHz cycles are required:
50
51 Time (ns): 0-------------- 500------------- ...
52 2 MHz cycle: 0 1 ...
53 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
54 /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ ...
55 ~RAS: /---\___________/---\___________ ...
56 ~CAS: /-----\___/-\___/-----\___/-\___ ...
57 Address events: A B C A B C ...
58 Data events: F S F S ...
59
60 ~RAS ops: 1 0 1 0 ...
61 ~CAS ops: 1 0 1 0 1 0 1 0 ...
62
63 Address ops: a b c a b c ...
64 Data ops: s f s f ...
65
66 ~WE: ......W ...
67 PHI OUT: \_______________/--------------- ...
68 CPU (RAM): L D ...
69 RnW: R ...
70
71 PHI OUT: \_______/-------\_______/------- ...
72 CPU (ROM): L D L D ...
73 RnW: R R ...
74
75 ~RAS must be high for 100ns, ~CAS must be high for 50ns.
76 ~RAS must be low for 150ns, ~CAS must be low for 90ns.
77 Data is available 150ns after ~RAS goes low, 90ns after ~CAS goes low.
78
79 Here, "A" and "B" respectively indicate the row and first column addresses
80 being latched into the RAM (on a negative edge for ~RAS and ~CAS
81 respectively), and "C" indicates the second column address being latched into
82 the RAM. Presumably, the first and second half-bytes can be read at "F" and
83 "S" respectively, and the row and column addresses must be made available at
84 "a" and "b" (and "c") respectively at the latest. Data can be read at "f" and
85 "s" for the first and second half-bytes respectively.
86
87 For the CPU, "L" indicates the point at which an address is taken from the CPU
88 address bus, on a negative edge of PHI OUT, with "D" being the point at which
89 data may either be read or be asserted for writing, on a positive edge of PHI
90 OUT. Here, PHI OUT is driven at 1MHz. Given that ~WE needs to be driven low
91 for writing or high for reading, and thus propagates RnW from the CPU, this
92 would need to be done before data would be retrieved and, according to the
93 TM4164EC4 datasheet, even as late as the column address is presented and ~CAS
94 brought low.
95
96 The TM4164EC4-15 has a row address access time of 150ns (maximum) and a column
97 address access time of 90ns (maximum), which appears to mean that ~RAS must be
98 held low for at least 150ns and that ~CAS must be held low for at least 90ns
99 before data becomes available. 150ns is 2.4 cycles (at 16MHz) and 90ns is 1.44
100 cycles. Thus, "A" to "F" is 2.5 cycles, "B" to "F" is 1.5 cycles, "C" to "S"
101 is 1.5 cycles.
102
103 Note that the Service Manual refers to the negative edge of RAS and CAS, but
104 the datasheet for the similar TM4164EC4 product shows latching on the negative
105 edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
106 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
107 "page mode" provides the appropriate behaviour for that particular product.
108
109 The CPU, when accessing the RAM alone, apparently does not make use of the
110 vacated "slot" that the ULA would otherwise use (when interleaving accesses in
111 MODE 4, 5 and 6). It only employs a full 2MHz access frequency to memory when
112 accessing ROM (and potentially sideways RAM).
113
114 See: Acorn Electron Advanced User Guide
115 See: Acorn Electron Service Manual
116 http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
117 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
118 See: http://stardot.org.uk/forums/viewtopic.php?p=120438#p120438
119
120 Bandwidth Figures
121 -----------------
122
123 Using an observation of 128 2MHz cycles per scanline, 256 active lines and 312
124 total lines, with 80 cycles occurring in the active periods of display
125 scanlines, the following bandwidth calculations can be performed:
126
127 Total theoretical maximum:
128 128 cycles * 312 lines
129 = 39936 bytes
130
131 MODE 0, 1, 2:
132 ULA: 80 cycles * 256 lines
133 = 20480 bytes
134 CPU: 48 cycles / 2 * 256 lines
135 + 128 cycles / 2 * (312 - 256) lines
136 = 9728 bytes
137
138 MODE 3:
139 ULA: 80 cycles * 24 rows * 8 lines
140 = 15360 bytes
141 CPU: 48 cycles / 2 * 24 rows * 8 lines
142 + 128 cycles / 2 * (312 - (24 rows * 8 lines))
143 = 12288 bytes
144
145 MODE 4, 5:
146 ULA: 40 cycles * 256 lines
147 = 10240 bytes
148 CPU: (40 cycles + 48 cycles / 2) * 256 lines
149 + 128 cycles / 2 * (312 - 256) lines
150 = 19968 bytes
151
152 MODE 6:
153 ULA: 40 cycles * 24 rows * 8 lines
154 = 7680 bytes
155 CPU: (40 cycles + 48 cycles / 2) * 24 rows * 8 lines
156 + 128 cycles / 2 * (312 - (24 rows * 8 lines))
157 = 19968 bytes
158
159 Here, the division of 2 for CPU accesses is performed to indicate that the CPU
160 only uses every other access opportunity even in uncontended periods. See the
161 2MHz RAM Access enhancement below for bandwidth calculations that consider
162 this limitation removed.
163
164 Video Timing
165 ------------
166
167 According to 8.7 in the Service Manual, and the PAL Wikipedia page,
168 approximately 4.7µs is used for the sync pulse, 5.7µs for the "back porch"
169 (including the "colour burst"), and 1.65µs for the "front porch", totalling
170 12.05µs and thus leaving 51.95µs for the active video signal for each
171 scanline. As the Service Manual suggests in the oscilloscope traces, the
172 display information is transmitted more or less centred within the active
173 video period since the ULA will only be providing pixel data for 40µs in each
174 scanline.
175
176 Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that
177 each scanline can be divided into 1024 cycles, although only 640 at most are
178 actively used to provide pixel data. Pixel data production should only occur
179 within a certain period on each scanline, approximately 262 cycles after the
180 start of hsync:
181
182 active video period = 51.95µs
183 pixel data period = 40µs
184 total silent period = 51.95µs - 40µs = 11.95µs
185 silent periods (before and after) = 11.95µs / 2 = 5.975µs
186 hsync and back porch period = 4.7µs + 5.7µs = 10.4µs
187 time before pixel data period = 10.4µs + 5.975µs = 16.375µs
188 pixel data period start cycle = 16.375µs / 62.5ns = 262
189
190 By choosing a number divisible by 8, the RAM access mechanism can be
191 synchronised with the pixel production. Thus, 256 is a more appropriate start
192 cycle, where the HS (horizontal sync) signal corresponding to the 4µs sync
193 pulse (or "normal sync" pulse as described by the "PAL TV timing and voltages"
194 document) occurs at cycle 0.
195
196 To summarise:
197
198 HS signal starts at cycle 0 on each horizontal scanline
199 HS signal ends approximately 4µs later at cycle 64
200 Pixel data starts approximately 12µs later at cycle 256
201
202 "Re: Electron Memory Contention" provides measurements that appear consistent
203 with these calculations.
204
205 The "vertical blanking period", meaning the period before picture information
206 in each field is 25 lines out of 312 (or 313) and thus lasts for 1.6ms. Of
207 this, 2.5 lines occur before the vsync (field sync) which also lasts for 2.5
208 lines. Thus, the first visible scanline on the first field of a frame occurs
209 half way through the 23rd scanline period measured from the start of vsync
210 (indicated by "V" in the diagrams below):
211
212 10 20 23
213 Line in frame: 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
214 Line from 1: 0 22 3
215 Line on screen: .:::::VVVVV::::: 12233445566
216 |_________________________________________________|
217 25 line vertical blanking period
218
219 In the second field of a frame, the first visible scanline coincides with the
220 24th scanline period measured from the start of line 313 in the frame:
221
222 310 336
223 Line in frame: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
224 Line from 313: 0 23 4
225 Line on screen: 88:::::VVVVV:::: 11223344
226 288 | |
227 |_________________________________________________|
228 25 line vertical blanking period
229
230 In order to consider only full lines, we might consider the start of each
231 frame to occur 23 lines after the start of vsync.
232
233 Again, it is likely that pixel data production should only occur on scanlines
234 within a certain period on each frame. The "625/50" document indicates that
235 only a certain region is "safe" to use, suggesting a vertically centred region
236 with approximately 15 blank lines above and below the picture. However, the
237 "PAL TV timing and voltages" document suggests 28 blank lines above and below
238 the picture. This would centre the 256 lines within the 312 lines of each
239 field and thus provide a start of picture approximately 5.5 or 5 lines after
240 the end of the blanking period or 28 or 27.5 lines after the start of vsync.
241
242 To summarise:
243
244 CSYNC signal starts at cycle 0
245 CSYNC signal ends approximately 160µs (2.5 lines) later at cycle 2560
246 Start of line occurs approximately 1632µs (5.5 lines) later at cycle 28672
247
248 See: http://en.wikipedia.org/wiki/PAL
249 See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal
250 See: The 625/50 PAL Video Signal and TV Compatible Graphics Modes
251 http://lipas.uwasa.fi/~f76998/video/modes/
252 See: PAL TV timing and voltages
253 http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
254 See: Line Standards
255 http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html
256 See: Horizontal Blanking Interval of 405-, 525-, 625- and 819-Line Standards
257 http://www.pembers.freeserve.co.uk/World-TV-Standards/HBI.pdf
258 See: Re: Electron Memory Contention
259 http://www.stardot.org.uk/forums/viewtopic.php?p=134109#p134109
260
261 RAM Integrated Circuits
262 -----------------------
263
264 Unicorn Electronics appears to offer 4164 RAM chips (as well as 6502 series
265 CPUs such as the 6502, 6502A, 6502B and 65C02). These 4164 devices are
266 available in 100ns (4164-100), 120ns (4164-120) and 150ns (4164-150) variants,
267 have 16 pins and address 65536 bits through a 1-bit wide channel. Similarly,
268 ByteDelight.com sell 4164 devices primarily for the ZX Spectrum.
269
270 The documentation for the Electron mentions 4164-15 RAM chips for IC4-7, and
271 the Samsung-produced KM41464 series is apparently equivalent to the Texas
272 Instruments 4164 chips presumably used in the Electron.
273
274 The TM4164EC4 series combines 4 64K x 1b units into a single package and
275 appears similar to the TM4164EA4 featured on the Electron's circuit diagram
276 (in the Advanced User Guide but not the Service Manual), and it also has 22
277 pins providing 3 additional inputs and 3 additional outputs over the 16 pins
278 of the individual 4164-15 modules, presumably allowing concurrent access to
279 the packaged memory units.
280
281 As far as currently available replacements are concerned, the NTE4164 is a
282 potential candidate: according to the Vetco Electronics entry, it is
283 supposedly a replacement for the TMS4164-15 amongst many other parts. Similar
284 parts include the NTE2164 and the NTE6664, both of which appear to have
285 largely the same performance and connection characteristics. Meanwhile, the
286 NTE21256 appears to be a 16-pin replacement with four times the capacity that
287 maintains the single data input and output pins. Using the NTE21256 as a
288 replacement for all ICs combined would be difficult because of the single bit
289 output.
290
291 Another device equivalent to the 4164-15 appears to be available under the
292 code 41662 from Jameco Electronics as the Siemens HYB 4164-2. The Jameco Web
293 site lists data sheets for other devices on the same page, but these are
294 different and actually appear to be provided under the 41574 product code (but
295 are listed under 41464-10) and appear to be replacements for the TM4164EC4:
296 the Samsung KM41464A-15 and NEC µPD41464 employ 18 pins, eliminating 4 pins by
297 employing 4 pins for both input and output.
298
299 Pins I/O pins Row access Column access
300 ---- -------- ---------- -------------
301 TM4164EC4 22 4 + 4 150ns (15) 90ns (15)
302 KM41464AP 18 4 150ns (15) 75ns (15)
303 NTE21256 16 1 + 1 150ns 75ns
304 HYB 4164-2 16 1 + 1 150ns 100ns
305 µPD41464 18 4 120ns (12) 60ns (12)
306
307 See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module
308 http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
309 See: Dynamic RAMS
310 http://www.unicornelectronics.com/IC/DYNAMIC.html
311 See: New old stock 8x 4164 chips
312 http://www.bytedelight.com/?product=8x-4164-chips-new-old-stock
313 See: KM4164B 64K x 1 Bit Dynamic RAM with Page Mode
314 http://images.ihscontent.net/vipimages/VipMasterIC/IC/SAMS/SAMSD020/SAMSD020-45.pdf
315 See: NTE2164 Integrated Circuit 65,536 X 1 Bit Dynamic Random Access Memory
316 http://www.vetco.net/catalog/product_info.php?products_id=2806
317 See: NTE4164 - IC-NMOS 64K DRAM 150NS
318 http://www.vetco.net/catalog/product_info.php?products_id=3680
319 See: NTE21256 - IC-256K DRAM 150NS
320 http://www.vetco.net/catalog/product_info.php?products_id=2799
321 See: NTE21256 262,144-Bit Dynamic Random Access Memory (DRAM)
322 http://www.nteinc.com/specs/21000to21999/pdf/nte21256.pdf
323 See: NTE6664 - IC-MOS 64K DRAM 150NS
324 http://www.vetco.net/catalog/product_info.php?products_id=5213
325 See: NTE6664 Integrated Circuit 64K-Bit Dynamic RAM
326 http://www.nteinc.com/specs/6600to6699/pdf/nte6664.pdf
327 See: 4164-150: MAJOR BRANDS
328 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41662_-1
329 See: HYB 4164-1, HYB 4164-2, HYB 4164-3 65,536-Bit Dynamic Random Access Memory (RAM)
330 http://www.jameco.com/Jameco/Products/ProdDS/41662SIEMENS.pdf
331 See: KM41464A NMOS DRAM 64K x 4 Bit Dynamic RAM with Page Mode
332 http://www.jameco.com/Jameco/Products/ProdDS/41662SAM.pdf
333 See: NEC µ41464 65,536 x 4-Bit Dynamic NMOS RAM
334 http://www.jameco.com/Jameco/Products/ProdDS/41662NEC.pdf
335 See: 41464-10: MAJOR BRANDS
336 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41574_-1
337
338 Interrupts
339 ----------
340
341 The ULA generates IRQs (maskable interrupts) according to certain conditions
342 and these conditions are controlled by location &FE00:
343
344 * Vertical sync (bottom of displayed screen)
345 * 50MHz real time clock
346 * Transmit data empty
347 * Receive data full
348 * High tone detect
349
350 The ULA is also used to clear interrupt conditions through location &FE05. Of
351 particular significance is bit 7, which must be set if an NMI (non-maskable
352 interrupt) has occurred and has thus suspended ULA access to memory, restoring
353 the normal function of the ULA.
354
355 ROM Paging
356 ----------
357
358 Accessing different ROMs involves bits 0 to 3 of &FE05. Some special ROM
359 mappings exist:
360
361 8 keyboard
362 9 keyboard (duplicate)
363 10 BASIC ROM
364 11 BASIC ROM (duplicate)
365
366 Paging in a ROM involves the following procedure:
367
368 1. Assert ROM page enable (bit 3) together with a ROM number n in bits 0 to
369 2, corresponding to ROM number 8+n, such that one of ROMs 12 to 15 is
370 selected.
371 2. Where a ROM numbered from 0 to 7 is to be selected, set bit 3 to zero
372 whilst writing the desired ROM number n in bits 0 to 2.
373
374 See: http://stardot.org.uk/forums/viewtopic.php?p=136686#p136686
375
376 Shadow/Expanded Memory
377 ----------------------
378
379 The Electron exposes all sixteen address lines and all eight data lines
380 through the expansion bus. Using such lines, it is possible to provide
381 additional memory - typically sideways ROM and RAM - on expansion cards and
382 through cartridges, although the official cartridge specification provides
383 fewer address lines and only seeks to provide access to memory in 16K units.
384
385 Various modifications and upgrades were developed to offer "turbo"
386 capabilities to the Electron, permitting the CPU to access a separate 8K of
387 RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
388 the ULA through additional logic. However, an enhanced ULA might support
389 independent CPU access to memory over the expansion bus by allowing itself to
390 be discharged from providing access to memory, potentially for a range of
391 addresses, and for the CPU to communicate with external memory uninterrupted.
392
393 Sideways RAM/ROM and Upper Memory Access
394 ----------------------------------------
395
396 Although the ULA controls the CPU clock, effectively slowing or stopping the
397 CPU when the ULA needs to access screen memory, it is apparently able to allow
398 the CPU to access addresses of &8000 and above - the upper region of memory -
399 at 2MHz independently of any access to RAM that the ULA might be performing,
400 only blocking the CPU if it attempts to access addresses of &7FFF and below
401 during any ULA memory access - the lower region of memory - by stopping or
402 stalling its clock.
403
404 Thus, the ULA remains aware of the level of the A15 line, only inhibiting the
405 CPU clock if the line goes low, when the CPU is attempting to access the lower
406 region of memory.
407
408 Hardware Scrolling (and Enhancement)
409 ------------------------------------
410
411 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
412 the least significant 5 bits being zero, thus limiting the scrolling
413 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
414 using the same layout of these addresses.
415
416 |--&FE02--------------| |--&FE03--------------|
417 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
418
419 XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
420
421 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
422 memory to pixel locations is character oriented. A change in 8 bytes would
423 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
424 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
425 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
426 Guide).
427
428 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
429 of changing the screen address by 2 bytes is the change in the number of lines
430 from the initial and final character rows that need reading by the ULA, which
431 would need to maintain this state information (although this is a relatively
432 trivial change). Another pitfall is the complication that might be introduced
433 to software writing bitmaps of character height to the screen.
434
435 See: http://pastraiser.com/computers/acornelectron/acornelectron.html
436
437 Enhancement: Mode Layouts
438 -------------------------
439
440 Merely changing the screen memory mappings in order to have Archimedes-style
441 row-oriented screen addresses (instead of character-oriented addresses) could
442 be done for the existing modes, but this might not be sufficiently beneficial,
443 especially since accessing regions of the screen would involve incrementing
444 pointers by amounts that are inconvenient on an 8-bit CPU.
445
446 However, instead of using a Archimedes-style mapping, column-oriented screen
447 addresses could be more feasibly employed: incrementing the address would
448 reference the vertical screen location below the currently-referenced location
449 (just as occurs within characters using the existing ULA); instead of
450 returning to the top of the character row and referencing the next horizontal
451 location after eight bytes, the address would reference the next character row
452 and continue to reference locations downwards over the height of the screen
453 until reaching the bottom; at the bottom, the next location would be the next
454 horizontal location at the top of the screen.
455
456 In other words, the memory layout for the screen would resemble the following
457 (for MODE 2):
458
459 &3000 &3100 ... &7F00
460 &3001 &3101
461 ... ...
462 &3007
463 &3008
464 ...
465 ... ...
466 &30FF ... &7FFF
467
468 Since there are 256 pixel rows, each column of locations would be addressable
469 using the low byte of the address. Meanwhile, the high byte would be
470 incremented to address different columns. Thus, addressing screen locations
471 would become a lot more convenient and potentially much more efficient for
472 certain kinds of graphical output.
473
474 One potential complication with this simplified addressing scheme arises with
475 hardware scrolling. Vertical hardware scrolling by one pixel row (not supported
476 with the existing ULA) would be achieved by incrementing or decrementing the
477 screen start address; by one character row, it would involve adding or
478 subtracting 8. However, the ULA only supports multiples of 64 when changing the
479 screen start address. Thus, if such a scheme were to be adopted, three
480 additional bits would need to be supported in the screen start register (see
481 "Hardware Scrolling (and Enhancement)" for more details). However, horizontal
482 scrolling would be much improved even under the severe constraints of the
483 existing ULA: only adjustments of 256 to the screen start address would be
484 required to produce single-location scrolling of as few as two pixels in MODE 2
485 (four pixels in MODEs 1 and 5, eight pixels otherwise).
486
487 More disruptive is the effect of this alternative layout on software.
488 Presumably, compatibility with the BBC Micro was the primary goal of the
489 Electron's hardware design. With the character-oriented screen layout in
490 place, system software (and application software accessing the screen
491 directly) would be relying on this layout to run on the Electron with little
492 or no modification. Although it might have been possible to change the system
493 software to use this column-oriented layout instead, this would have incurred
494 a development cost and caused additional work porting things like games to the
495 Electron. Moreover, a separate branch of the software from that supporting the
496 BBC Micro and closer derivatives would then have needed maintaining.
497
498 The decision to use the character-oriented layout in the BBC Micro may have
499 been related to the choice of circuitry and to facilitate a convenient
500 hardware implementation, and by the time the Electron was planned, it was too
501 late to do anything about this somewhat unfortunate choice.
502
503 Pixel Layouts
504 -------------
505
506 The pixel layouts are as follows:
507
508 Modes Depth (bpp) Pixels (from bits)
509 ----- ----------- ------------------
510 0, 3, 4, 6 1 7 6 5 4 3 2 1 0
511 1, 5 2 73 62 51 40
512 2 4 7531 6420
513
514 Since the ULA reads a half-byte at a time, one might expect it to attempt to
515 produce pixels for every half-byte, as opposed to handling entire bytes.
516 However, the pixel layout is not conducive to producing pixels as soon as a
517 half-byte has been read for a given full-byte location: in 1bpp modes the
518 first four pixels can indeed be produced, but in 2bpp and 4bpp modes the pixel
519 data is spread across the entire byte in different ways.
520
521 An alternative arrangement might be as follows:
522
523 Modes Depth (bpp) Pixels (from bits)
524 ----- ----------- ------------------
525 0, 3, 4, 6 1 7 6 5 4 3 2 1 0
526 1, 5 2 76 54 32 10
527 2 4 7654 3210
528
529 Just as the mode layouts were presumably decided by compatibility with the BBC
530 Micro, the pixel layouts will have been maintained for similar reasons.
531 Unfortunately, this layout prevents any optimisation of the ULA for handling
532 half-byte pixel data generally.
533
534 Enhancement: The Missing MODE 4
535 -------------------------------
536
537 The Electron inherits its screen mode selection from the BBC Micro, where MODE
538 3 is a text version of MODE 0, and where MODE 6 is a text version of MODE 4.
539 Neither MODE 3 nor MODE 6 is a genuine character-based text mode like MODE 7,
540 however, and they are merely implemented by skipping two scanlines in every
541 ten after the eight required to produce a character line. Thus, such modes
542 provide a 24-row display.
543
544 In principle, nothing prevents this "text mode" effect being applied to other
545 modes. The 20-column modes are not well-suited to displaying text, which
546 leaves MODE 1 which, unlike MODEs 3 and 6, can display 4 colours rather than
547 2. Although the need for a non-monochrome 40-column text mode is addressed by
548 MODE 7 on the BBC Micro, the Electron lacks such a mode.
549
550 If the 4-colour, 24-row variant of MODE 1 were to be provided, logically it
551 would occupy MODE 4 instead of the current MODE 4:
552
553 Screen mode Size (kilobytes) Colours Rows Resolution
554 ----------- ---------------- ------- ---- ----------
555 0 20 2 32 640x256
556 1 20 4 32 320x256
557 2 20 16 32 160x256
558 3 16 2 24 640x256
559 4 (new) 16 4 24 320x256
560 4 (old) 10 2 32 320x256
561 5 10 4 32 160x256
562 6 8 2 24 320x256
563
564 Thus, for increasing mode numbers, the size of each mode would be the same or
565 less than the preceding mode.
566
567 Enhancement: 2MHz RAM Access
568 ----------------------------
569
570 Given that the CPU and ULA both access RAM at 2MHz, but given that the CPU
571 when not competing with the ULA only accesses RAM every other 2MHz cycle (as
572 if the ULA still needed to access the RAM), one useful enhancement would be a
573 mechanism to let the CPU take over the ULA cycles outside the ULA's period of
574 activity comparable to the way the ULA takes over the CPU cycles in MODE 0 to
575 3.
576
577 Thus, the RAM access cycles would resemble the following in MODE 0 to 3:
578
579 Upon a transition from display cycles: UUUUCCCC (instead of UUUUC_C_)
580 On a non-display line: CCCCCCCC (instead of C_C_C_C_)
581
582 In MODE 4 to 6:
583
584 Upon a transition from display cycles: CUCUCCCC (instead of CUCUC_C_)
585 On a non-display line: CCCCCCCC (instead of C_C_C_C_)
586
587 This would improve CPU bandwidth as follows:
588
589 Standard ULA Enhanced ULA
590 MODE 0, 1, 2 9728 bytes 19456 bytes
591 MODE 3 12288 bytes 24576 bytes
592 MODE 4, 5 19968 bytes 29696 bytes
593 MODE 6 19968 bytes 32256 bytes
594
595 With such an enhancement, MODE 0 to 3 experience a doubling of CPU bandwidth
596 because all access opportunities to RAM are doubled. Meanwhile, in the other
597 modes, some CPU accesses occur alongside ULA accesses and thus cannot be
598 doubled, but the CPU bandwidth increase is still significant.
599
600 Enhancement: Region Blanking
601 ----------------------------
602
603 The problem of permitting character-oriented blitting in programs whilst
604 scrolling the screen by sub-character amounts could be mitigated by permitting
605 a region of the display to be blank, such as the final lines of the display.
606 Consider the following vertical scrolling by 2 bytes that would cause an
607 initial character row of 6 lines and a final character row of 2 lines:
608
609 6 lines - initial, partial character row
610 248 lines - 31 complete rows
611 2 lines - final, partial character row
612
613 If a routine were in use that wrote 8 line bitmaps to the partial character
614 row now split in two, it would be advisable to hide one of the regions in
615 order to prevent content appearing in the wrong place on screen (such as
616 content meant to appear at the top "leaking" onto the bottom). Blanking 6
617 lines would be sufficient, as can be seen from the following cases.
618
619 Scrolling up by 2 lines:
620
621 6 lines - initial, partial character row
622 240 lines - 30 complete rows
623 4 lines - part of 1 complete row
624 -----------------------------------------------------------------
625 4 lines - part of 1 complete row (hidden to maintain 250 lines)
626 2 lines - final, partial character row (hidden)
627
628 Scrolling down by 2 lines:
629
630 2 lines - initial, partial character row
631 248 lines - 31 complete rows
632 ----------------------------------------------------------
633 6 lines - final, partial character row (hidden)
634
635 Thus, in this case, region blanking would impose a 250 line display with the
636 bottom 6 lines blank.
637
638 See the description of the display suspend enhancement for a more efficient
639 way of blanking lines than merely blanking the palette whilst allowing the CPU
640 to perform useful work during the blanking period.
641
642 To control the blanking or suspending of lines at the top and bottom of the
643 display, a memory location could be dedicated to the task: the upper 4 bits
644 could define a blanking region of up to 16 lines at the top of the screen,
645 whereas the lower 4 bits could define such a region at the bottom of the
646 screen. If more lines were required, two locations could be employed, allowing
647 the top and bottom regions to occupy the entire screen.
648
649 Enhancement: Screen Height Adjustment
650 -------------------------------------
651
652 The height of the screen could be configurable in order to reduce screen
653 memory consumption. This is not quite done in MODE 3 and 6 since the start of
654 the screen appears to be rounded down to the nearest page, but by reducing the
655 height by amounts more than a page, savings would be possible. For example:
656
657 Screen width Depth Height Bytes per line Saving in bytes Start address
658 ------------ ----- ------ -------------- --------------- -------------
659 640 1 252 80 320 &3140 -> &3100
660 640 1 248 80 640 &3280 -> &3200
661 320 1 240 40 640 &5A80 -> &5A00
662 320 2 240 80 1280 &3500
663
664 Screen Mode Selection
665 ---------------------
666
667 Bits 3, 4 and 5 of address &FE*7 control the selected screen mode. For a wider
668 range of modes, the other bits of &FE*7 (related to sound, cassette
669 input/output and the Caps Lock LED) would need to be reassigned and bit 0
670 potentially being made available for use.
671
672 Enhancement: Palette Definition
673 -------------------------------
674
675 Since all memory accesses go via the ULA, an enhanced ULA could employ more
676 specific addresses than &FE*X to perform enhanced functions. For example, the
677 palette control is done using &FE*8-F and merely involves selecting predefined
678 colours, whereas an enhanced ULA could support the redefinition of all 16
679 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
680 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
681 specifications similar to those used on the Archimedes.
682
683 The principal limitation here is actually the hardware: the Electron has only
684 a single output line for each of the red, green and blue channels, and if
685 those outputs are strictly digital and can only be set to a "high" and "low"
686 value, then only the existing eight colours are possible. If a modern ULA were
687 able to output analogue values (or values at well-defined points between the
688 high and low values, such as the half-on value supported by the Amstrad CPC
689 series), it would still need to be assessed whether the circuitry could
690 successfully handle and propagate such values. Various sources indicate that
691 only "TTL levels" are supported by the RGB output circuit, and since there are
692 74LS08 AND logic gates involved in the RGB component outputs from the ULA, it
693 is likely that the ULA is expected to provide only "high" or "low" values.
694
695 Short of adding extra outputs from the ULA (either additional red, green and
696 blue outputs or a combined intensity output), another approach might involve
697 some kind of modulation where an output value might be encoded in multiple
698 pulses at a higher frequency than the pixel frequency. However, this would
699 demand additional circuitry outside the ULA, and component RGB monitors would
700 probably not be able to take advantage of this feature; only UHF and composite
701 video devices (the latter with the composite video colour support enabled on
702 the Electron's circuit board) would potentially benefit.
703
704 Flashing Colours
705 ----------------
706
707 According to the Advanced User Guide, "The cursor and flashing colours are
708 entirely generated in software: This means that all of the logical to physical
709 colour map must be changed to cause colours to flash." This appears to suggest
710 that the palette registers must be updated upon the flash counter - read and
711 written by OSBYTE &C1 (193) - reaching zero and that some way of changing the
712 colour pairs to be any combination of colours might be possible, instead of
713 having colour complements as pairs.
714
715 It is conceivable that the interrupt code responsible does the simple thing
716 and merely inverts the current values for any logical colours (LC) for which
717 the associated physical colour (as supplied as the second parameter to the VDU
718 19 call) has the top bit of its four bit value set. These top bits are not
719 recorded in the palette registers but are presumably recorded separately and
720 used to build bitmaps as follows:
721
722 LC 2 colour 4 colour 16 colour 4-bit value for inversion
723 -- -------- -------- --------- -------------------------
724 0 00010001 00010001 00010001 1, 1, 1
725 1 01000100 00100010 00010001 4, 2, 1
726 2 01000100 00100010 4, 2
727 3 10001000 00100010 8, 2
728 4 00010001 1
729 5 00010001 1
730 6 00100010 2
731 7 00100010 2
732 8 01000100 4
733 9 01000100 4
734 10 10001000 8
735 11 10001000 8
736 12 01000100 4
737 13 01000100 4
738 14 10001000 8
739 15 10001000 8
740
741 Inversion value calculation:
742
743 2 colour formula: 1 << (colour * 2)
744 4 colour formula: 1 << colour
745 16 colour formula: 1 << ((colour & 2) + ((colour & 8) * 2))
746
747 For example, where logical colour 0 has been mapped to a physical colour in
748 the range 8 to 15, a bitmap of 00010001 would be chosen as its contribution to
749 the inversion operation. (The lower three bits of the physical colour would be
750 used to set the underlying colour information affected by the inversion
751 operation.)
752
753 An operation in the interrupt code would then combine the bitmaps for all
754 logical colours in 2 and 4 colour modes, with the 16 colour bitmaps being
755 combined for groups of logical colours as follows:
756
757 Logical colours
758 ---------------
759 0, 2, 8, 10
760 4, 6, 12, 14
761 5, 7, 13, 15
762 1, 3, 9, 11
763
764 These combined bitmaps would be EORed with the existing palette register
765 values in order to perform the value inversion necessary to produce the
766 flashing effect.
767
768 Thus, in the VDU 19 operation, the appropriate inversion value would be
769 calculated for the logical colour, and this value would then be combined with
770 other inversion values in a dedicated memory location corresponding to the
771 colour's group as indicated above. Meanwhile, the palette channel values would
772 be derived from the lower three bits of the specified physical colour and
773 combined with other palette data in dedicated memory locations corresponding
774 to the palette registers.
775
776 Interestingly, although flashing colours on the BBC Micro are controlled by
777 toggling bit 0 of the &FE20 control register location for the Video ULA, the
778 actual colour inversion is done in hardware.
779
780 Enhancement: Palette Definition Lists
781 -------------------------------------
782
783 It can be useful to redefine the palette in order to change the colours
784 available for a particular region of the screen, particularly in modes where
785 the choice of colours is constrained, and if an increased colour depth were
786 available, palette redefinition would be useful to give the illusion of more
787 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
788 by using interrupt-driven timers, but a more efficient approach would involve
789 presenting lists of palette definitions to the ULA so that it can change the
790 palette at a particular display line.
791
792 One might define a palette redefinition list in a region of memory and then
793 communicate its contents to the ULA by writing the address and length of the
794 list, along with the display line at which the palette is to be changed, to
795 ULA registers such that the ULA buffers the list and performs the redefinition
796 at the appropriate time. Throughput/bandwidth considerations might impose
797 restrictions on the practical length of such a list, however.
798
799 Enhancement: Display Synchronisation Interrupts
800 -----------------------------------------------
801
802 When completing each scanline of the display, the ULA could trigger an
803 interrupt. Since this might impact system performance substantially, the
804 feature would probably need to be configurable, and it might be sufficient to
805 have an interrupt only after a certain number of display lines instead.
806 Permitting the CPU to take action after eight lines would allow palette
807 switching and other effects to occur on a character row basis.
808
809 The ULA provides an interrupt at the end of the display period, presumably so
810 that software can schedule updates to the screen, avoid flickering or tearing,
811 and so on. However, some applications might benefit from an interrupt at, or
812 just before, the start of the display period so that palette modifications or
813 similar effects could be scheduled.
814
815 Enhancement: Palette-Free Modes
816 -------------------------------
817
818 Palette-free modes might be defined where bit values directly correspond to
819 the red, green and blue channels, although this would mostly make sense only
820 for modes with depths greater than the standard 4 bits per pixel, and such
821 modes would require more memory than MODE 2 if they were to have an acceptable
822 resolution.
823
824 Enhancement: Display Suspend
825 ----------------------------
826
827 Especially when writing to the screen memory, it could be beneficial to be
828 able to suspend the ULA's access to the memory, instead producing blank values
829 for all screen pixels until a program is ready to reveal the screen. This is
830 different from palette blanking since with a blank palette, the ULA is still
831 reading screen memory and translating its contents into pixel values that end
832 up being blank.
833
834 This function is reminiscent of a capability of the ZX81, albeit necessary on
835 that hardware to reduce the load on the system CPU which was responsible for
836 producing the video output. By allowing display suspend on the Electron, the
837 performance benefit would be derived from giving the CPU full access to the
838 memory bandwidth.
839
840 The region blanking feature mentioned above could be implemented using this
841 enhancement instead of employing palette blanking for the affected lines of
842 the display.
843
844 Enhancement: Memory Filling
845 ---------------------------
846
847 A capability that could be given to an enhanced ULA is that of permitting the
848 ULA to write to screen memory as well being able to read from it. Although
849 such a capability would probably not be useful in conjunction with the
850 existing read operations when producing a screen display, and insufficient
851 bandwidth would exist to do so in high-bandwidth screen modes anyway, the
852 capability could be offered during a display suspend period (as described
853 above), permitting a more efficient mechanism to rapidly fill memory with a
854 predetermined value.
855
856 This capability could also support block filling, where the limits of the
857 filled memory would be defined by the position and size of a screen area,
858 although this would demand the provision of additional registers in the ULA to
859 retain the details of such areas and additional logic to control the fill
860 operation.
861
862 Enhancement: Region Filling
863 ---------------------------
864
865 An alternative to memory writing might involve indicating regions using
866 additional registers or memory where the ULA fills regions of the screen with
867 content instead of reading from memory. Unlike hardware sprites which should
868 realistically provide varied content, region filling could employ single
869 colours or patterns, and one advantage of doing so would be that the ULA need
870 not access memory at all within a particular region.
871
872 Regions would be defined on a row-by-row basis. Instead of reading memory and
873 blitting a direct representation to the screen, the ULA would read region
874 definitions containing a start column, region width and colour details. There
875 might be a certain number of definitions allowed per row, or the ULA might
876 just traverse an ordered list of such definitions with each one indicating the
877 row, start column, region width and colour details.
878
879 One could even compress this information further by requiring only the row,
880 start column and colour details with each subsequent definition terminating
881 the effect of the previous one. However, one would also need to consider the
882 convenience of preparing such definitions and whether efficient access to
883 definitions for a particular row might be desirable. It might also be
884 desirable to avoid having to prepare definitions for "empty" areas of the
885 screen, effectively making the definition of the screen contents employ
886 run-length encoding and employ only colour plus length information.
887
888 One application of region filling is that of simple 2D and 3D shape rendering.
889 Although it is entirely possible to plot such shapes to the screen and have
890 the ULA blit the memory contents to the screen, such operations consume
891 bandwidth both in the initial plotting and in the final transfer to the
892 screen. Region filling would reduce such bandwidth usage substantially.
893
894 This way of representing screen images would make certain kinds of images
895 unfeasible to represent - consider alternating single pixel values which could
896 easily occur in some character bitmaps - even if an internal queue of regions
897 were to be supported such that the ULA could read ahead and buffer such
898 "bandwidth intensive" areas. Thus, the ULA might be better served providing
899 this feature for certain areas of the display only as some kind of special
900 graphics window.
901
902 Enhancement: Hardware Sprites
903 -----------------------------
904
905 An enhanced ULA might provide hardware sprites, but this would be done in an
906 way that is incompatible with the standard ULA, since no &FE*X locations are
907 available for allocation. To keep the facility simple, hardware sprites would
908 have a standard byte width and height.
909
910 The specification of sprites could involve the reservation of 16 locations
911 (for example, &FE20-F) specifying a fixed number of eight sprites, with each
912 location pair referring to the sprite data. By limiting the ULA to dealing
913 with a fixed number of sprites, the work required inside the ULA would be
914 reduced since it would avoid having to deal with arbitrary numbers of sprites.
915
916 The principal limitation on providing hardware sprites is that of having to
917 obtain sprite data, given that the ULA is usually required to retrieve screen
918 data, and given the lack of memory bandwidth available to retrieve sprite data
919 (particularly from multiple sprites supposedly at the same position) and
920 screen data simultaneously. Although the ULA could potentially read sprite
921 data and screen data in alternate memory accesses in screen modes where the
922 bandwidth is not already fully utilised, this would result in a degradation of
923 performance.
924
925 Enhancement: Additional Screen Mode Configurations
926 --------------------------------------------------
927
928 Alternative screen mode configurations could be supported. The ULA has to
929 produce 640 pixel values across the screen, with pixel doubling or quadrupling
930 employed to fill the screen width:
931
932 Screen width Columns Scaling Depth Bytes
933 ------------ ------- ------- ----- -----
934 640 80 x1 1 80
935 320 40 x2 1, 2 40, 80
936 160 20 x4 2, 4 40, 80
937
938 It must also use at most 80 byte-sized memory accesses to provide the
939 information for the display. Given that characters must occupy an 8x8 pixel
940 array, if a configuration featuring anything other than 20, 40 or 80 character
941 columns is to be supported, compromises must be made such as the introduction
942 of blank pixels either between characters (such as occurs between rows in MODE
943 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
944 in MODE 3 and 6). Consider the following configuration:
945
946 Screen width Columns Scaling Depth Bytes Blank
947 ------------ ------- ------- ----- ------ -----
948 208 26 x3 1, 2 26, 52 16
949
950 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
951 colours could be provided, with 16 blank pixel values (out of a total of 640)
952 generated either at the start or end (or split between the start and end) of
953 each scanline.
954
955 Enhancement: Character Attributes
956 ---------------------------------
957
958 The BBC Micro MODE 7 employs something resembling character attributes to
959 support teletext displays, but depends on circuitry providing a character
960 generator. The ZX Spectrum, on the other hand, provides character attributes
961 as a means of colouring bitmapped graphics. Although such a feature is very
962 limiting as the sole means of providing multicolour graphics, in situations
963 where the choice is between low resolution multicolour graphics or high
964 resolution monochrome graphics, character attributes provide a potentially
965 useful compromise.
966
967 For each byte read, the ULA must deliver 8 pixel values (out of a total of
968 640) to the video output, doing so by either emptying its pixel buffer on a
969 pixel per cycle basis, or by multiplying pixels and thus holding them for more
970 than one cycle. For example for a screen mode having 640 pixels in width:
971
972 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
973 Reads: B B
974 Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
975
976 And for a screen mode having 320 pixels in width:
977
978 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
979 Reads: B
980 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
981
982 However, in modes where less than 80 bytes are required to generate the pixel
983 values, an enhanced ULA might be able to read additional bytes between those
984 providing the bitmapped graphics data:
985
986 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
987 Reads: B A
988 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
989
990 These additional bytes could provide colour information for the bitmapped data
991 in the following character column (of 8 pixels). Since it would be desirable
992 to apply attribute data to the first column, the initial 8 cycles might be
993 configured to not produce pixel values.
994
995 For an entire character, attribute data need only be read for the first row of
996 pixels for a character. The subsequent rows would have attribute information
997 applied to them, although this would require the attribute data to be stored
998 in some kind of buffer. Thus, the following access pattern would be observed:
999
1000 Cycle: A B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ...
1001
1002 A whole byte used for colour information for a whole character would result in
1003 a choice of 256 colours, and this might be somewhat excessive. By only reading
1004 attribute bytes at every other opportunity, a choice of 16 colours could be
1005 applied individually to two characters.
1006
1007 Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
1008 Reads: B A B -
1009 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
1010
1011 Further reductions in attribute data access, offering 4 colours for every
1012 character in a four character block, for example, might also be worth
1013 considering.
1014
1015 Consider the following configurations for screen modes with a colour depth of
1016 1 bit per pixel for bitmap information:
1017
1018 Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
1019 ------------ ------- ------- --------- --------- ------- ------------
1020 320 40 x2 40 40 256 &5300
1021 320 40 x2 40 20 16 &5580 -> &5500
1022 320 40 x2 40 10 4 &56C0 -> &5600
1023 208 26 x3 26 26 256 &62C0 -> &6200
1024 208 26 x3 26 13 16 &6460 -> &6400
1025
1026 Enhancement: MODE 7 Emulation using Character Attributes
1027 --------------------------------------------------------
1028
1029 If the scheme of applying attributes to character regions were employed to
1030 emulate MODE 7, in conjunction with the MODE 6 display technique, the
1031 following configuration would be required:
1032
1033 Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
1034 ------------ ------- ---- --------- --------- ------- ------------
1035 320 40 25 40 20 16 &5ECC -> &5E00
1036 320 40 25 40 10 4 &5FC6 -> &5F00
1037
1038 Although this requires much more memory than MODE 7 (8500 bytes versus MODE
1039 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
1040 at least make a limited 40-column multicolour mode available as a substitute
1041 for MODE 7.
1042
1043 Enhancement: High Resolution Graphics
1044 -------------------------------------
1045
1046 Screen modes with higher resolutions and larger colour depths might be
1047 possible, but this would in most cases involve the allocation of more screen
1048 memory, and the ULA would probably then be obliged to page in such memory for
1049 the CPU to be able to sensibly access it all.
1050
1051 Enhancement: Genlock Support
1052 ----------------------------
1053
1054 The ULA generates a video signal in conjunction with circuitry producing the
1055 output features necessary for the correct display of the screen image.
1056 However, it appears that the ULA drives the video synchronisation mechanism
1057 instead of reacting to an existing signal. Genlock support might be possible
1058 if the ULA were made to be responsive to such external signals, resetting its
1059 address generators upon receiving synchronisation events.
1060
1061 Enhancement: Improved Sound
1062 ---------------------------
1063
1064 The standard ULA reserves &FE*6 for sound generation and cassette input/output
1065 (with bits 1 and 2 of &FE*7 being used to select either sound generation or
1066 cassette I/O), thus making it impossible to support multiple channels within
1067 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
1068 and an enhanced ULA could adopt this interface.
1069
1070 The BBC Micro uses the SN76489 chip to produce sound, and the entire
1071 functionality of this chip could be emulated for enhanced sound, with a subset
1072 of the functionality exposed via the &FE*6 interface.
1073
1074 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
1075 See: http://www.smspower.org/Development/SN76489
1076
1077 Enhancement: Waveform Upload
1078 ----------------------------
1079
1080 As with a hardware sprite function, waveforms could be uploaded or referenced
1081 using locations as registers referencing memory regions.
1082
1083 Enhancement: Sound Input/Output
1084 -------------------------------
1085
1086 Since the ULA already controls audio input/output for cassette-based data, it
1087 would have been interesting to entertain the idea of sampling and output of
1088 sounds through the cassette interface. However, a significant amount of
1089 circuitry is employed to process the input signal for use by the ULA and to
1090 process the output signal for recording.
1091
1092 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw_03.htm#3.11
1093
1094 Enhancement: BBC ULA Compatibility
1095 ----------------------------------
1096
1097 Although some new ULA functions could be defined in a way that is also
1098 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
1099 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
1100 map, but controls various functions specific to the 6845 video controller;
1101 &FE08-F is reserved for the serial controller. It therefore becomes possible
1102 to disregard compatibility where compatibility is already disregarded for a
1103 particular area of functionality.
1104
1105 &FE20-F maps to video ULA functionality on the BBC Micro which provides
1106 control over the palette (using address &FE21, compared to &FE07-F on the
1107 Electron) and other system-specific functions. Since the location usage is
1108 generally incompatible, this region could be reused for other purposes.
1109
1110 Enhancement: Increased RAM, ULA and CPU Performance
1111 ---------------------------------------------------
1112
1113 More modern implementations of the hardware might feature faster RAM coupled
1114 with an increased ULA clock frequency in order to increase the bandwidth
1115 available to the ULA and to the CPU in situations where the ULA is not needed
1116 to perform work. A ULA employing a 32MHz clock would be able to complete the
1117 retrieval of a byte from RAM in only 250ns and thus be able to enable the CPU
1118 to access the RAM for the following 250ns even in display modes requiring the
1119 retrieval of a byte for the display every 500ns. The CPU could, subject to
1120 timing issues, run at 2MHz even in MODE 0, 1 and 2.
1121
1122 A scheme such as that described above would have a similar effect to the
1123 scheme employed in the BBC Micro, although the latter made use of RAM with a
1124 wider bandwidth in order to complete memory transfers within 250ns and thus
1125 permit the CPU to run continuously at 2MHz.
1126
1127 Higher bandwidth could potentially be used to implement exotic features such
1128 as RAM-resident hardware sprites or indeed any feature demanding RAM access
1129 concurrent with the production of the display image.
1130
1131 Enhancement: Multiple CPU Stacks and Zero Pages
1132 -----------------------------------------------
1133
1134 The 6502 maintains a stack for subroutine calls and register storage in page
1135 &01. Although the stack register can be manipulated using the TSX and TXS
1136 instructions, thereby permitting the maintenance of multiple stack regions and
1137 thus the potential coexistence of multiple programs each using a separate
1138 region, only programs that make little use of the stack (perhaps avoiding
1139 deeply-nested subroutine invocations and significant register storage) would
1140 be able to coexist without overwriting each other's stacks.
1141
1142 One way that this issue could be alleviated would involve the provision of a
1143 facility to redirect accesses to page &01 to other areas of memory. The ULA
1144 would provide a register that defines a physical page for the use of the CPU's
1145 "logical" page &01, and upon any access to page &01 by the CPU, the ULA would
1146 change the asserted address lines to redirect the access to the appropriate
1147 physical region.
1148
1149 By providing an 8-bit register, mapping to the most significant byte (MSB) of
1150 a 16-bit address, the ULA could then replace any MSB equal to &01 with the
1151 register value before the access is made. Where multiple programs coexist,
1152 upon switching programs, the register would be updated to point the ULA to the
1153 appropriate stack location, thus providing a simple memory management unit
1154 (MMU) capability.
1155
1156 In a similar fashion, zero page accesses could also be redirected so that code
1157 could run from sideways RAM and have zero page operations redirected to "upper
1158 memory" - for example, to page &BE (with stack accesses redirected to page
1159 &BF, perhaps) - thereby permitting most CPU operations to occur without
1160 inadvertent accesses to "lower memory" (the RAM) which would risk stalling the
1161 CPU as it contends with the ULA for memory access.
1162
1163 Such facilities could also be provided by a separate circuit between the CPU
1164 and ULA in a fashion similar to that employed by a "turbo" board, but unlike
1165 such boards, no additional RAM would be provided: all memory accesses would
1166 occur as normal through the ULA, albeit redirected when configured
1167 appropriately.
1168
1169 ULA Pin Functions
1170 -----------------
1171
1172 The functions of the ULA pins are described in the Electron Service Manual. Of
1173 interest to video processing are the following:
1174
1175 CSYNC (low during horizontal or vertical synchronisation periods, high
1176 otherwise)
1177
1178 HS (low during horizontal synchronisation periods, high otherwise)
1179
1180 RED, GREEN, BLUE (pixel colour outputs)
1181
1182 CLOCK IN (a 16MHz clock input, 4V peak to peak)
1183
1184 PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
1185
1186 More general memory access pins:
1187
1188 RAM0...RAM3 (data lines to/from the RAM)
1189
1190 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
1191
1192 RAS (row address strobe setting the row address on a negative edge - see the
1193 timing notes)
1194
1195 CAS (column address strobe setting the column address on a negative edge -
1196 see the timing notes)
1197
1198 WE (sets write enable with logic 0, read with logic 1)
1199
1200 ROM (select data access from ROM)
1201
1202 CPU-oriented memory access pins:
1203
1204 A0...A15 (CPU address lines)
1205
1206 PD0...PD7 (CPU data lines)
1207
1208 R/W (indicates CPU write with logic 0, CPU read with logic 1)
1209
1210 Interrupt-related pins:
1211
1212 NMI (CPU request for uninterrupted 1MHz access to memory)
1213
1214 IRQ (signal event to CPU)
1215
1216 POR (power-on reset, resetting the ULA on a positive edge and asserting the
1217 CPU's RST pin)
1218
1219 RST (master reset for the CPU signalled on power-up and by the Break key)
1220
1221 Keyboard-related pins:
1222
1223 KBD0...KBD3 (keyboard inputs)
1224
1225 CAPS LOCK (control status LED)
1226
1227 Sound-related pins:
1228
1229 SOUND O/P (sound output using internal oscillator)
1230
1231 Cassette-related pins:
1232
1233 CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
1234
1235 CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
1236
1237 CAS RC (detect high tone)
1238
1239 CAS MO (motor relay output)
1240
1241 ÷13 IN (~1200 baud clock input)
1242
1243 ULA Socket
1244 ----------
1245
1246 The socket used for the ULA is a 3M/TexTool 268-5400 68-pin socket.
1247
1248 References
1249 ----------
1250
1251 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw.htm
1252
1253 About this Document
1254 -------------------
1255
1256 The most recent version of this document and accompanying distribution should
1257 be available from the following location:
1258
1259 http://hgweb.boddie.org.uk/ULA
1260
1261 Copyright and licence information can be found in the docs directory of this
1262 distribution - see docs/COPYING.txt for more information.