1 Principal Design and Feature Constraints
2 ----------------------------------------
3
4 The features of the ULA are limited by the amount of time and resources that
5 can be allocated to each activity necessary to support such features given the
6 fundamental obligations of the unit. Maintaining a screen display based on the
7 contents of RAM itself requires the ULA to have exclusive access to such
8 hardware resources for a significant period of time. Whilst other elements of
9 the ULA can in principle run in parallel with this activity, they cannot also
10 access the RAM. Consequently, other features that might use the RAM must
11 accept a reduced allocation of that resource in comparison to a hypothetical
12 architecture where concurrent RAM access is possible.
13
14 Thus, the principal constraint for many features is bandwidth. The duration of
15 access to hardware resources is one aspect of this; the rate at which such
16 resources can be accessed is another. For example, the RAM is not fast enough
17 to support access more frequently than one byte per 2MHz cycle, and for screen
18 modes involving 80 bytes of screen data per scanline, there are no free cycles
19 for anything other than the production of pixel output during the active
20 scanline periods.
21
22 Timing
23 ------
24
25 According to 15.3.2 in the Advanced User Guide, there are 312 scanlines, 256
26 of which are used to generate pixel data. At 50Hz, this means that 128 cycles
27 are spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
28 312 ~= 128 cycles). This is consistent with the observation that each scanline
29 requires at most 80 bytes of data, and that the ULA is apparently busy for 40
30 out of 64 microseconds in each scanline.
31
32 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
33 each providing two bits of each byte) using two cycles within the 500ns period
34 of the 2MHz clock to complete each access operation. Since the CPU and ULA
35 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
36 effectively run at 1MHz (since every other 500ns period involves the ULA
37 accessing RAM). The CPU is driven by an external clock (IC8) whose 16MHz
38 frequency is divided by the ULA (IC1) depending on the screen mode in use.
39
40 Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
41 patterns corresponding to 16MHz cycles are required:
42
43 Time (ns): 0-------------- 500------------ ...
44 2 MHz cycle: 0 1 ...
45 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
46 ~RAS: 0 1 0 1 ...
47 ~CAS: 0 1 0 1 0 1 0 1 ...
48 A B C A B C ...
49 F S F S ...
50 a b c a b c ...
51
52 Here, "A" and "B" respectively indicate the row and first column addresses
53 being latched into the RAM (on a negative edge for ~RAS and ~CAS
54 respectively), and "C" indicates the second column address being latched into
55 the RAM. Presumably, the first and second half-bytes can be read at "F" and
56 "S" respectively, and the row and column addresses must be made available at
57 "a" and "b" (and "c") respectively at the latest.
58
59 The TM4164EC4-15 has a row address access time of 150ns (maximum) and a column
60 address access time of 90ns (maximum), which appears to mean that
61 approximately two 16MHz cycles after the row address is latched, and one and a
62 half cycles after the column address is latched, the data becomes available.
63
64 Note that the Service Manual refers to the negative edge of RAS and CAS, but
65 the datasheet for the similar TM4164EC4 product shows latching on the negative
66 edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
67 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
68 "page mode" provides the appropriate behaviour for that particular product.
69
70 See: Acorn Electron Advanced User Guide
71 See: Acorn Electron Service Manual
72 http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
73 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
74
75 Video Timing
76 ------------
77
78 According to 8.7 in the Service Manual, and the PAL Wikipedia page,
79 approximately 4.7µs is used for the sync pulse, 5.7µs for the "back porch"
80 (including the "colour burst"), and 1.65µs for the "front porch", totalling
81 12.05µs and thus leaving 51.95µs for the active video signal for each
82 scanline. As the Service Manual suggests in the oscilloscope traces, the
83 display information is transmitted more or less centred within the active
84 video period since the ULA will only be providing pixel data for 40µs in each
85 scanline.
86
87 Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that
88 each scanline can be divided into 1024 cycles, although only 640 at most are
89 actively used to provide pixel data. Pixel data production should only occur
90 within a certain period on each scanline, approximately 262 cycles after the
91 start of hsync:
92
93 active video period = 51.95µs
94 pixel data period = 40µs
95 total silent period = 51.95µs - 40µs = 11.95µs
96 silent periods (before and after) = 11.95µs / 2 = 5.975µs
97 hsync and back porch period = 4.7µs + 5.7µs = 10.4µs
98 time before pixel data period = 10.4µs + 5.975µs = 16.375µs
99 pixel data period start cycle = 16.375µs / 62.5ns = 262
100
101 By choosing a number divisible by 8, the RAM access mechanism can be
102 synchronised with the pixel production. Thus, 264 is a more appropriate start
103 cycle.
104
105 The "vertical blanking period", meaning the period before picture information
106 in each field is 25 lines out of 312 (strictly 312.5) and thus lasts for
107 1.6ms. Of this, 2.5 lines occur before the vsync (field sync) which also lasts
108 for 2.5 lines. Thus, the first visible scanline on the first field of a frame
109 occurs half way through the 23rd scanline period measured from the start of
110 vsync:
111
112 10 20 23
113 Line in frame: 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
114 Line from 1: 0 22 3
115 Line on screen: .:::::VVVVV::::: 12233445566
116 |_________________________________________________|
117 25 line vertical blanking period
118
119 In the second field of a frame, the first visible scanline coincides with the
120 24th scanline period measured from the start of line 313 in the frame:
121
122 310 336
123 Line in frame: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
124 Line from 313: 0 23
125 Line on screen: 88:::::VVVVV:::: 11223344
126 288 | |
127 |_________________________________________________|
128 25 line vertical blanking period
129
130 In order to consider only full lines, we might consider the start of each
131 frame to occur 23 lines after the start of vsync.
132
133 Again, it is likely that pixel data production should only occur on scanlines
134 within a certain period on each frame. The "625/50" document indicates that
135 only a certain region is "safe" to use, suggesting a vertically centred region
136 with approximately 15 blank lines above and below the picture. Thus, the start
137 of the picture could be chosen as 38 lines after the start of vsync.
138
139 See: http://en.wikipedia.org/wiki/PAL
140 See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal
141 See: The 625/50 PAL Video Signal and TV Compatible Graphics Modes
142 http://lipas.uwasa.fi/~f76998/video/modes/
143 See: PAL TV timing and voltages
144 http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
145 See: Line Standards
146 http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html
147
148 RAM Integrated Circuits
149 -----------------------
150
151 The documentation for the Electron mentions 4164-15 RAM chips for IC4-7, and
152 the Samsung-produced KM41464 series is apparently equivalent to the Texas
153 Instruments 4164 chips presumably used in the Electron.
154
155 The TM4164EC4 series combines 4 64K x 1b units into a single package and
156 appears similar to the TM4164EA4 featured on the Electron's circuit diagram
157 (in the Advanced User Guide but not the Service Manual), and it also has 22
158 pins providing 3 additional inputs and 3 additional outputs over the 16 pins
159 of the individual 4164-15 modules, presumably allowing concurrent access to
160 the packaged memory units.
161
162 As far as currently available replacements are concerned, the NTE4164 is a
163 potential candidate: according to the Vetco Electronics entry, it is
164 supposedly a replacement for the TMS4164-15 amongst many other parts. Similar
165 parts include the NTE2164 and the NTE6664, both of which appear to have
166 largely the same performance and connection characteristics. Meanwhile, the
167 NTE21256 appears to be a 16-pin replacement with four times the capacity that
168 maintains the single data input and output pins. Using the NTE21256 as a
169 replacement for all ICs combined would be difficult because of the single bit
170 output.
171
172 Another device equivalent to the 4164-15 appears to be available under the
173 code 41662 from Jameco Electronics as the Siemens HYB 4164-2. The Jameco Web
174 site lists data sheets for other devices on the same page, but these are
175 different and actually appear to be provided under the 41574 product code (but
176 are listed under 41464-10) and appear to be replacements for the TM4164EC4:
177 the Samsung KM41464A-15 and NEC µPD41464 employ 18 pins, eliminating 4 pins by
178 employing 4 pins for both input and output.
179
180 Pins I/O pins Row access Column access
181 ---- -------- ---------- -------------
182 TM4164EC4 22 4 + 4 150ns (15) 90ns (15)
183 KM41464AP 18 4 150ns (15) 75ns (15)
184 NTE21256 16 1 + 1 150ns 75ns
185 HYB 4164-2 16 1 + 1 150ns 100ns
186 µPD41464 18 4 120ns (12) 60ns (12)
187
188 See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module
189 http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
190 See: KM4164B 64K x 1 Bit Dynamic RAM with Page Mode
191 http://images.ihscontent.net/vipimages/VipMasterIC/IC/SAMS/SAMSD020/SAMSD020-45.pdf
192 See: NTE2164 Integrated Circuit 65,536 X 1 Bit Dynamic Random Access Memory
193 http://www.vetco.net/catalog/product_info.php?products_id=2806
194 See: NTE4164 - IC-NMOS 64K DRAM 150NS
195 http://www.vetco.net/catalog/product_info.php?products_id=3680
196 See: NTE21256 - IC-256K DRAM 150NS
197 http://www.vetco.net/catalog/product_info.php?products_id=2799
198 See: NTE21256 262,144-Bit Dynamic Random Access Memory (DRAM)
199 http://www.nteinc.com/specs/21000to21999/pdf/nte21256.pdf
200 See: NTE6664 - IC-MOS 64K DRAM 150NS
201 http://www.vetco.net/catalog/product_info.php?products_id=5213
202 See: NTE6664 Integrated Circuit 64K-Bit Dynamic RAM
203 http://www.nteinc.com/specs/6600to6699/pdf/nte6664.pdf
204 See: 4164-150: MAJOR BRANDS
205 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41662_-1
206 See: HYB 4164-1, HYB 4164-2, HYB 4164-3 65,536-Bit Dynamic Random Access Memory (RAM)
207 http://www.jameco.com/Jameco/Products/ProdDS/41662SIEMENS.pdf
208 See: KM41464A NMOS DRAM 64K x 4 Bit Dynamic RAM with Page Mode
209 http://www.jameco.com/Jameco/Products/ProdDS/41662SAM.pdf
210 See: NEC µ41464 65,536 x 4-Bit Dynamic NMOS RAM
211 http://www.jameco.com/Jameco/Products/ProdDS/41662NEC.pdf
212 See: 41464-10: MAJOR BRANDS
213 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41574_-1
214
215 Interrupts
216 ----------
217
218 The ULA generates IRQs (maskable interrupts) according to certain conditions
219 and these conditions are controlled by location &FE00:
220
221 * Vertical sync (bottom of displayed screen)
222 * 50MHz real time clock
223 * Transmit data empty
224 * Receive data full
225 * High tone detect
226
227 The ULA is also used to clear interrupt conditions through location &FE05. Of
228 particular significance is bit 7, which must be set if an NMI (non-maskable
229 interrupt) has occurred and has thus suspended ULA access to memory, restoring
230 the normal function of the ULA.
231
232 ROM Paging
233 ----------
234
235 Accessing different ROMs involves bits 0 to 3 of &FE05. Some special ROM
236 mappings exist:
237
238 8 keyboard
239 9 keyboard (duplicate)
240 10 BASIC ROM
241 11 BASIC ROM (duplicate)
242
243 Paging in a ROM involves the following procedure:
244
245 1. Assert ROM page enable (bit 3) together with a ROM number n in bits 0 to
246 2, corresponding to ROM number 8+n, such that one of ROMs 12 to 15 is
247 selected.
248 2. Where a ROM numbered from 0 to 7 is to be selected, set bit 3 to zero
249 whilst writing the desired ROM number n in bits 0 to 2.
250
251 Shadow/Expanded Memory
252 ----------------------
253
254 The Electron exposes all sixteen address lines and all eight data lines
255 through the expansion bus. Using such lines, it is possible to provide
256 additional memory - typically sideways ROM and RAM - on expansion cards and
257 through cartridges, although the official cartridge specification provides
258 fewer address lines and only seeks to provide access to memory in 16K units.
259
260 Various modifications and upgrades were developed to offer "turbo"
261 capabilities to the Electron, permitting the CPU to access a separate 8K of
262 RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
263 the ULA through additional logic. However, an enhanced ULA might support
264 independent CPU access to memory over the expansion bus by allowing itself to
265 be discharged from providing access to memory, potentially for a range of
266 addresses, and for the CPU to communicate with external memory uninterrupted.
267
268 Hardware Scrolling
269 ------------------
270
271 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
272 the least significant 5 bits being zero, thus limiting the scrolling
273 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
274 using the same layout of these addresses.
275
276 |--&FE02--------------| |--&FE03--------------|
277 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
278
279 XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
280
281 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
282 memory to pixel locations is character oriented. A change in 8 bytes would
283 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
284 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
285 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
286 Guide).
287
288 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
289 of changing the screen address by 2 bytes is the change in the number of lines
290 from the initial and final character rows that need reading by the ULA, which
291 would need to maintain this state information (although this is a relatively
292 trivial change). Another pitfall is the complication that might be introduced
293 to software writing bitmaps of character height to the screen.
294
295 Enhancement: Region Blanking
296 ----------------------------
297
298 The problem of permitting character-oriented blitting in programs whilst
299 scrolling the screen by sub-character amounts could be mitigated by permitting
300 a region of the display to be blank, such as the final lines of the display.
301 Consider the following vertical scrolling by 2 bytes that would cause an
302 initial character row of 6 lines and a final character row of 2 lines:
303
304 6 lines - initial, partial character row
305 248 lines - 31 complete rows
306 2 lines - final, partial character row
307
308 If a routine were in use that wrote 8 line bitmaps to the partial character
309 row now split in two, it would be advisable to hide one of the regions in
310 order to prevent content appearing in the wrong place on screen (such as
311 content meant to appear at the top "leaking" onto the bottom). Blanking 6
312 lines would be sufficient, as can be seen from the following cases.
313
314 Scrolling up by 2 lines:
315
316 6 lines - initial, partial character row
317 240 lines - 30 complete rows
318 4 lines - part of 1 complete row
319 -----------------------------------------------------------------
320 4 lines - part of 1 complete row (hidden to maintain 250 lines)
321 2 lines - final, partial character row (hidden)
322
323 Scrolling down by 2 lines:
324
325 2 lines - initial, partial character row
326 248 lines - 31 complete rows
327 ----------------------------------------------------------
328 6 lines - final, partial character row (hidden)
329
330 Thus, in this case, region blanking would impose a 250 line display with the
331 bottom 6 lines blank.
332
333 See the description of the display suspend enhancement for a more efficient
334 way of blanking lines whilst allowing the CPU to perform useful work during
335 the blanking period.
336
337 Enhancement: Screen Height Adjustment
338 -------------------------------------
339
340 The height of the screen could be configurable in order to reduce screen
341 memory consumption. This is not quite done in MODE 3 and 6 since the start of
342 the screen appears to be rounded down to the nearest page, but by reducing the
343 height by amounts more than a page, savings would be possible. For example:
344
345 Screen width Depth Height Bytes per line Saving in bytes Start address
346 ------------ ----- ------ -------------- --------------- -------------
347 640 1 252 80 320 &3140 -> &3100
348 640 1 248 80 640 &3280 -> &3200
349 320 1 240 40 640 &5A80 -> &5A00
350 320 2 240 80 1280 &3500
351
352 Screen Mode Selection
353 ---------------------
354
355 Bits 3, 4 and 5 of address &FE*7 control the selected screen mode. For a wider
356 range of modes, the other bits of &FE*7 (related to sound, cassette
357 input/output and the Caps Lock LED) would need to be reassigned and bit 0
358 potentially being made available for use.
359
360 Enhancement: Palette Definition
361 -------------------------------
362
363 Since all memory accesses go via the ULA, an enhanced ULA could employ more
364 specific addresses than &FE*X to perform enhanced functions. For example, the
365 palette control is done using &FE*8-F and merely involves selecting predefined
366 colours, whereas an enhanced ULA could support the redefinition of all 16
367 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
368 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
369 specifications similar to those used on the Archimedes.
370
371 The principal limitation here is actually the hardware: the Electron has only
372 a single output line for each of the red, green and blue channels, and if
373 those outputs are strictly digital and can only be set to a "high" and "low"
374 value, then only the existing eight colours are possible. If a modern ULA were
375 able to output analogue values, it would still need to be assessed whether the
376 circuitry could successfully handle and propagate such values. Various sources
377 indicate that only "TTL levels" are supported by the RGB output circuit, and
378 since there are 74LS08 AND logic gates involved in the RGB component outputs
379 from the ULA, it is likely that the ULA is expected to provide only "high" or
380 "low" values.
381
382 Short of adding extra outputs from the ULA (either additional red, green and
383 blue outputs or a combined intensity output), another approach might involve
384 some kind of modulation where an output value might be encoded in multiple
385 pulses at a higher frequency than the pixel frequency. However, this would
386 demand additional circuitry outside the ULA, and component RGB monitors would
387 probably not be able to take advantage of this feature; only UHF and composite
388 video devices (the latter with the composite video colour support enabled on
389 the Electron's circuit board) would potentially benefit.
390
391 Flashing Colours
392 ----------------
393
394 According to the Advanced User Guide, "The cursor and flashing colours are
395 entirely generated in software: This means that all of the logical to physical
396 colour map must be changed to cause colours to flash." This appears to suggest
397 that the palette registers must be updated upon the flash counter - read and
398 written by OSBYTE &C1 (193) - reaching zero and that some way of changing the
399 colour pairs to be any combination of colours might be possible, instead of
400 having colour complements as pairs.
401
402 It is conceivable that the interrupt code responsible does the simple thing
403 and merely inverts the current values for any logical colours (LC) for which
404 the associated physical colour (as supplied as the second parameter to the VDU
405 19 call) has the top bit of its four bit value set. These top bits are not
406 recorded in the palette registers but are presumably recorded separately and
407 used to build bitmaps as follows:
408
409 LC 2 colour 4 colour 16 colour 4-bit value for inversion
410 -- -------- -------- --------- -------------------------
411 0 00010001 00010001 00010001 1, 1, 1
412 1 01000100 00100010 00010001 4, 2, 1
413 2 01000100 00100010 4, 2
414 3 10001000 00100010 8, 2
415 4 00010001 1
416 5 00010001 1
417 6 00100010 2
418 7 00100010 2
419 8 01000100 4
420 9 01000100 4
421 10 10001000 8
422 11 10001000 8
423 12 01000100 4
424 13 01000100 4
425 14 10001000 8
426 15 10001000 8
427
428 Inversion value calculation:
429
430 2 colour formula: 1 << (colour * 2)
431 4 colour formula: 1 << colour
432 16 colour formula: 1 << ((colour & 2) + ((colour & 8) * 2))
433
434 For example, where logical colour 0 has been mapped to a physical colour in
435 the range 8 to 15, a bitmap of 00010001 would be chosen as its contribution to
436 the inversion operation. (The lower three bits of the physical colour would be
437 used to set the underlying colour information affected by the inversion
438 operation.)
439
440 An operation in the interrupt code would then combine the bitmaps for all
441 logical colours in 2 and 4 colour modes, with the 16 colour bitmaps being
442 combined for groups of logical colours as follows:
443
444 Logical colours
445 ---------------
446 0, 2, 8, 10
447 4, 6, 12, 14
448 5, 7, 13, 15
449 1, 3, 9, 11
450
451 These combined bitmaps would be EORed with the existing palette register
452 values in order to perform the value inversion necessary to produce the
453 flashing effect.
454
455 Thus, in the VDU 19 operation, the appropriate inversion value would be
456 calculated for the logical colour, and this value would then be combined with
457 other inversion values in a dedicated memory location corresponding to the
458 colour's group as indicated above. Meanwhile, the palette channel values would
459 be derived from the lower three bits of the specified physical colour and
460 combined with other palette data in dedicated memory locations corresponding
461 to the palette registers.
462
463 Enhancement: Palette Definition Lists
464 -------------------------------------
465
466 It can be useful to redefine the palette in order to change the colours
467 available for a particular region of the screen, particularly in modes where
468 the choice of colours is constrained, and if an increased colour depth were
469 available, palette redefinition would be useful to give the illusion of more
470 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
471 by using interrupt-driven timers, but a more efficient approach would involve
472 presenting lists of palette definitions to the ULA so that it can change the
473 palette at a particular display line.
474
475 One might define a palette redefinition list in a region of memory and then
476 communicate its contents to the ULA by writing the address and length of the
477 list, along with the display line at which the palette is to be changed, to
478 ULA registers such that the ULA buffers the list and performs the redefinition
479 at the appropriate time. Throughput/bandwidth considerations might impose
480 restrictions on the practical length of such a list, however.
481
482 Enhancement: Palette-Free Modes
483 -------------------------------
484
485 Palette-free modes might be defined where bit values directly correspond to
486 the red, green and blue channels, although this would mostly make sense only
487 for modes with depths greater than the standard 4 bits per pixel, and such
488 modes would require more memory than MODE 2 if they were to have an acceptable
489 resolution.
490
491 Enhancement: Display Suspend
492 ----------------------------
493
494 Especially when writing to the screen memory, it could be beneficial to be
495 able to suspend the ULA's access to the memory, instead producing blank values
496 for all screen pixels until a program is ready to reveal the screen. This is
497 different from palette blanking since with a blank palette, the ULA is still
498 reading screen memory and translating its contents into pixel values that end
499 up being blank.
500
501 This function is reminiscent of a capability of the ZX81, albeit necessary on
502 that hardware to reduce the load on the system CPU which was responsible for
503 producing the video output. By allowing display suspend on the Electron, the
504 performance benefit would be derived from giving the CPU full access to the
505 memory bandwidth.
506
507 Enhancement: Memory Filling
508 ---------------------------
509
510 A capability that could be given to an enhanced ULA is that of permitting the
511 ULA to write to screen memory as well being able to read from it. Although
512 such a capability would probably not be useful in conjunction with the
513 existing read operations when producing a screen display, and insufficient
514 bandwidth would exist to do so in high-bandwidth screen modes anyway, the
515 capability could be offered during a display suspend period (as described
516 above), permitting a more efficient mechanism to rapidly fill memory with a
517 predetermined value.
518
519 This capability could also support block filling, where the limits of the
520 filled memory would be defined by the position and size of a screen area,
521 although this would demand the provision of additional registers in the ULA to
522 retain the details of such areas and additional logic to control the fill
523 operation.
524
525 Enhancement: Hardware Sprites
526 -----------------------------
527
528 An enhanced ULA might provide hardware sprites, but this would be done in an
529 way that is incompatible with the standard ULA, since no &FE*X locations are
530 available for allocation. To keep the facility simple, hardware sprites would
531 have a standard byte width and height.
532
533 The specification of sprites could involve the reservation of 16 locations
534 (for example, &FE20-F) specifying a fixed number of eight sprites, with each
535 location pair referring to the sprite data. By limiting the ULA to dealing
536 with a fixed number of sprites, the work required inside the ULA would be
537 reduced since it would avoid having to deal with arbitrary numbers of sprites.
538
539 The principal limitation on providing hardware sprites is that of having to
540 obtain sprite data, given that the ULA is usually required to retrieve screen
541 data, and given the lack of memory bandwidth available to retrieve sprite data
542 (particularly from multiple sprites supposedly at the same position) and
543 screen data simultaneously. Although the ULA could potentially read sprite
544 data and screen data in alternate memory accesses in screen modes where the
545 bandwidth is not already fully utilised, this would result in a degradation of
546 performance.
547
548 Enhancement: Additional Screen Mode Configurations
549 --------------------------------------------------
550
551 Alternative screen mode configurations could be supported. The ULA has to
552 produce 640 pixel values across the screen, with pixel doubling or quadrupling
553 employed to fill the screen width:
554
555 Screen width Columns Scaling Depth Bytes
556 ------------ ------- ------- ----- -----
557 640 80 x1 1 80
558 320 40 x2 1, 2 40, 80
559 160 20 x4 2, 4 40, 80
560
561 It must also use at most 80 byte-sized memory accesses to provide the
562 information for the display. Given that characters must occupy an 8x8 pixel
563 array, if a configuration featuring anything other than 20, 40 or 80 character
564 columns is to be supported, compromises must be made such as the introduction
565 of blank pixels either between characters (such as occurs between rows in MODE
566 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
567 in MODE 3 and 6). Consider the following configuration:
568
569 Screen width Columns Scaling Depth Bytes Blank
570 ------------ ------- ------- ----- ------ -----
571 208 26 x3 1, 2 26, 52 16
572
573 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
574 colours could be provided, with 16 blank pixel values (out of a total of 640)
575 generated either at the start or end (or split between the start and end) of
576 each scanline.
577
578 Enhancement: Character Attributes
579 ---------------------------------
580
581 The BBC Micro MODE 7 employs something resembling character attributes to
582 support teletext displays, but depends on circuitry providing a character
583 generator. The ZX Spectrum, on the other hand, provides character attributes
584 as a means of colouring bitmapped graphics. Although such a feature is very
585 limiting as the sole means of providing multicolour graphics, in situations
586 where the choice is between low resolution multicolour graphics or high
587 resolution monochrome graphics, character attributes provide a potentially
588 useful compromise.
589
590 For each byte read, the ULA must deliver 8 pixel values (out of a total of
591 640) to the video output, doing so by either emptying its pixel buffer on a
592 pixel per cycle basis, or by multiplying pixels and thus holding them for more
593 than one cycle. For example for a screen mode having 640 pixels in width:
594
595 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
596 Reads: B B
597 Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
598
599 And for a screen mode having 320 pixels in width:
600
601 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
602 Reads: B
603 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
604
605 However, in modes where less than 80 bytes are required to generate the pixel
606 values, an enhanced ULA might be able to read additional bytes between those
607 providing the bitmapped graphics data:
608
609 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
610 Reads: B A
611 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
612
613 These additional bytes could provide colour information for the bitmapped data
614 in the following character column (of 8 pixels). Since it would be desirable
615 to apply attribute data to the first column, the initial 8 cycles might be
616 configured to not produce pixel values.
617
618 For an entire character, attribute data need only be read for the first row of
619 pixels for a character. The subsequent rows would have attribute information
620 applied to them, although this would require the attribute data to be stored
621 in some kind of buffer. Thus, the following access pattern would be observed:
622
623 Cycle: A B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ...
624
625 A whole byte used for colour information for a whole character would result in
626 a choice of 256 colours, and this might be somewhat excessive. By only reading
627 attribute bytes at every other opportunity, a choice of 16 colours could be
628 applied individually to two characters.
629
630 Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
631 Reads: B A B -
632 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
633
634 Further reductions in attribute data access, offering 4 colours for every
635 character in a four character block, for example, might also be worth
636 considering.
637
638 Consider the following configurations for screen modes with a colour depth of
639 1 bit per pixel for bitmap information:
640
641 Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
642 ------------ ------- ------- --------- --------- ------- ------------
643 320 40 x2 40 40 256 &5300
644 320 40 x2 40 20 16 &5580 -> &5500
645 320 40 x2 40 10 4 &56C0 -> &5600
646 208 26 x3 26 26 256 &62C0 -> &6200
647 208 26 x3 26 13 16 &6460 -> &6400
648
649 Enhancement: MODE 7 Emulation using Character Attributes
650 --------------------------------------------------------
651
652 If the scheme of applying attributes to character regions were employed to
653 emulate MODE 7, in conjunction with the MODE 6 display technique, the
654 following configuration would be required:
655
656 Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
657 ------------ ------- ---- --------- --------- ------- ------------
658 320 40 25 40 20 16 &5ECC -> &5E00
659 320 40 25 40 10 4 &5FC6 -> &5F00
660
661 Although this requires much more memory than MODE 7 (8500 bytes versus MODE
662 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
663 at least make a limited 40-column multicolour mode available as a substitute
664 for MODE 7.
665
666 Enhancement: High Resolution Graphics and Mode Layouts
667 ------------------------------------------------------
668
669 Screen modes with different screen memory mappings, higher resolutions and
670 larger colour depths might be possible, but this would in most cases involve
671 the allocation of more screen memory, and the ULA would probably then be
672 obliged to page in such memory for the CPU to be able to sensibly access it
673 all. Merely changing the memory mappings in order to have Archimedes-style
674 row-oriented screen addresses (instead of character-oriented addresses) could
675 be done for the existing modes, but this might not be sufficiently beneficial,
676 especially since accessing regions of the screen would involve incrementing
677 pointers by amounts that are inconvenient on an 8-bit CPU.
678
679 Enhancement: Genlock Support
680 ----------------------------
681
682 The ULA generates a video signal in conjunction with circuitry producing the
683 output features necessary for the correct display of the screen image.
684 However, it appears that the ULA drives the video synchronisation mechanism
685 instead of reacting to an existing signal. Genlock support might be possible
686 if the ULA were made to be responsive to such external signals, resetting its
687 address generators upon receiving synchronisation events.
688
689 Enhancement: Improved Sound
690 ---------------------------
691
692 The standard ULA reserves &FE*6 for sound generation and cassette input/output
693 (with bits 1 and 2 of &FE*7 being used to select either sound generation or
694 cassette I/O), thus making it impossible to support multiple channels within
695 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
696 and an enhanced ULA could adopt this interface.
697
698 The BBC Micro uses the SN76489 chip to produce sound, and the entire
699 functionality of this chip could be emulated for enhanced sound, with a subset
700 of the functionality exposed via the &FE*6 interface.
701
702 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
703
704 Enhancement: Waveform Upload
705 ----------------------------
706
707 As with a hardware sprite function, waveforms could be uploaded or referenced
708 using locations as registers referencing memory regions.
709
710 Enhancement: Sound Input/Output
711 -------------------------------
712
713 Since the ULA already controls audio input/output for cassette-based data, it
714 would have been interesting to entertain the idea of sampling and output of
715 sounds through the cassette interface. However, a significant amount of
716 circuitry is employed to process the input signal for use by the ULA and to
717 process the output signal for recording.
718
719 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw_03.htm#3.11
720
721 Enhancement: BBC ULA Compatibility
722 ----------------------------------
723
724 Although some new ULA functions could be defined in a way that is also
725 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
726 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
727 map, but controls various functions specific to the 6845 video controller;
728 &FE08-F is reserved for the serial controller. It therefore becomes possible
729 to disregard compatibility where compatibility is already disregarded for a
730 particular area of functionality.
731
732 &FE20-F maps to video ULA functionality on the BBC Micro which provides
733 control over the palette (using address &FE21, compared to &FE07-F on the
734 Electron) and other system-specific functions. Since the location usage is
735 generally incompatible, this region could be reused for other purposes.
736
737 Enhancement: Increased RAM, ULA and CPU Performance
738 ---------------------------------------------------
739
740 More modern implementations of the hardware might feature faster RAM coupled
741 with an increased ULA clock frequency in order to increase the bandwidth
742 available to the ULA and to the CPU in situations where the ULA is not needed
743 to perform work. A ULA employing a 32MHz clock would be able to complete the
744 retrieval of a byte from RAM in only 250ns and thus be able to enable the CPU
745 to access the RAM for the following 250ns even in display modes requiring the
746 retrieval of a byte for the display every 500ns. The CPU could, subject to
747 timing issues, run at 2MHz even in MODE 0, 1 and 2.
748
749 A scheme such as that described above would have a similar effect to the
750 scheme employed in the BBC Micro, although the latter made use of RAM with a
751 wider bandwidth in order to complete memory transfers within 250ns and thus
752 permit the CPU to run continuously at 2MHz.
753
754 Higher bandwidth could potentially be used to implement exotic features such
755 as RAM-resident hardware sprites or indeed any feature demanding RAM access
756 concurrent with the production of the display image.
757
758 ULA Pin Functions
759 -----------------
760
761 The functions of the ULA pins are described in the Electron Service Manual. Of
762 interest to video processing are the following:
763
764 CSYNC (low during horizontal or vertical synchronisation periods, high
765 otherwise)
766
767 HS (low during horizontal synchronisation periods, high otherwise)
768
769 RED, GREEN, BLUE (pixel colour outputs)
770
771 CLOCK IN (a 16MHz clock input, 4V peak to peak)
772
773 PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
774
775 More general memory access pins:
776
777 RAM0...RAM3 (data lines to/from the RAM)
778
779 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
780
781 RAS (row address strobe setting the row address on a negative edge - see the
782 timing notes)
783
784 CAS (column address strobe setting the column address on a negative edge -
785 see the timing notes)
786
787 WE (sets write enable with logic 0, read with logic 1)
788
789 ROM (select data access from ROM)
790
791 CPU-oriented memory access pins:
792
793 A0...A15 (CPU address lines)
794
795 PD0...PD7 (CPU data lines)
796
797 R/W (indicates CPU write with logic 0, CPU read with logic 1)
798
799 Interrupt-related pins:
800
801 NMI (CPU request for uninterrupted 1MHz access to memory)
802
803 IRQ (signal event to CPU)
804
805 POR (power-on reset, resetting the ULA on a positive edge and asserting the
806 CPU's RST pin)
807
808 RST (master reset for the CPU signalled on power-up and by the Break key)
809
810 Keyboard-related pins:
811
812 KBD0...KBD3 (keyboard inputs)
813
814 CAPS LOCK (control status LED)
815
816 Sound-related pins:
817
818 SOUND O/P (sound output using internal oscillator)
819
820 Cassette-related pins:
821
822 CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
823
824 CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
825
826 CAS RC (detect high tone)
827
828 CAS MO (motor relay output)
829
830 ÷13 IN (~1200 baud clock input)
831
832 References
833 ----------
834
835 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw.htm