1 Timing
2 ------
3
4 According to 15.3.2 in the Advanced User Guide, there are 312 scanlines, 256
5 of which are used to generate pixel data. At 50Hz, this means that 128 cycles
6 are spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
7 312 ~= 128 cycles). This is consistent with the observation that each scanline
8 requires at most 80 bytes of data, and that the ULA is apparently busy for 40
9 out of 64 microseconds in each scanline.
10
11 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
12 each providing two bits of each byte) using two cycles within the 500ns period
13 of the 2MHz clock to complete each access operation. Since the CPU and ULA
14 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
15 effectively run at 1MHz (since every other 500ns period involves the ULA
16 accessing RAM). The CPU is driven by an external clock (IC8) whose 16MHz
17 frequency is divided by the ULA (IC1) depending on the screen mode in use.
18
19 Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
20 patterns corresponding to 16MHz cycles are required:
21
22 Time (ns): 0-------------- 500------------ ...
23 2 MHz cycle: 0 1 ...
24 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
25 ~RAS: 0 1 0 1 ...
26 ~CAS: 0 1 0 1 0 1 0 1 ...
27 A B B A B B ...
28 F S F S ...
29 a b b a b b ...
30
31 Here, "A" indicates the row and column addresses being latched into the RAM
32 (on a negative edge for ~RAS and ~CAS respectively), and "B" indicates the
33 second column address being latched into the RAM. Presumably, the first and
34 second half-bytes can be read at "F" and "S" respectively, and the row and
35 column addresses must be made available at "a" and "b" respectively at the
36 latest.
37
38 Note that the Service Manual refers to the negative edge of RAS and CAS, but
39 the datasheet for the similar TM4164EC4 product shows latching on the negative
40 edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
41 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
42 "page mode" provides the appropriate behaviour for that particular product.
43
44 Video Timing
45 ------------
46
47 According to 8.7 in the Service Manual, and the PAL Wikipedia page,
48 approximately 4.7µs is used for the sync pulse, 5.7µs for the "back porch"
49 (including the "colour burst"), and 1.65µs for the "front porch", totalling
50 12.05µs and thus leaving 51.95µs for the active video signal for each
51 scanline. As the Service Manual suggests in the oscilloscope traces, the
52 display information is transmitted more or less centred within the active
53 video period since the ULA will only be providing pixel data for 40µs in each
54 scanline.
55
56 Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that
57 each scanline can be divided into 1024 cycles, although only 640 at most are
58 actively used to provide pixel data. Pixel data production should only occur
59 within a certain period on each scanline, approximately 262 cycles after the
60 start of hsync:
61
62 active video period = 51.95µs
63 pixel data period = 40µs
64 total silent period = 51.95µs - 40µs = 11.95µs
65 silent periods (before and after) = 11.95µs / 2 = 5.975µs
66 hsync and back porch period = 4.7µs + 5.7µs = 10.4µs
67 time before pixel data period = 10.4µs + 5.975µs = 16.375µs
68 pixel data period start cycle = 16.375µs / 62.5ns = 262
69
70 By choosing a number divisible by 8, the RAM access mechanism can be
71 synchronised with the pixel production. Thus, 264 is a more appropriate start
72 cycle.
73
74 The "vertical blanking period", meaning the period before picture information
75 in each field is 25 lines out of 312 (strictly 312.5) and thus lasts for
76 1.6ms. Of this, 2.5 lines occur before the vsync (field sync) which also lasts
77 for 2.5 lines. Thus, the first visible scanline on the first field of a frame
78 occurs half way through the 23rd scanline period measured from the start of
79 vsync:
80
81 10 20 23
82 Line in frame: 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
83 Line from 1: 0 22 3
84 Line on screen: .:::::VVVVV::::: 12233445566
85 |_________________________________________________|
86 25 line vertical blanking period
87
88 In the second field of a frame, the first visible scanline coincides with the
89 24th scanline period measured from the start of line 313 in the frame:
90
91 310 336
92 Line in frame: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
93 Line from 313: 0 23
94 Line on screen: 88:::::VVVVV:::: 11223344
95 288 | |
96 |_________________________________________________|
97 25 line vertical blanking period
98
99 In order to consider only full lines, we might consider the start of each
100 frame to occur 23 lines after the start of vsync.
101
102 Again, it is likely that pixel data production should only occur on scanlines
103 within a certain period on each frame. The "625/50" document indicates that
104 only a certain region is "safe" to use, suggesting a vertically centred region
105 with approximately 15 blank lines above and below the picture. Thus, the start
106 of the picture could be chosen as 38 lines after the start of vsync.
107
108 See: Acorn Electron Advanced User Guide
109 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
110 See: http://en.wikipedia.org/wiki/PAL
111 See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal
112 See: The 625/50 PAL Video Signal and TV Compatible Graphics Modes
113 http://lipas.uwasa.fi/~f76998/video/modes/
114 See: PAL TV timing and voltages
115 http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
116 See: Line Standards
117 http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html
118 See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module
119 http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
120 See: Acorn Electron Service Manual
121 http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
122
123 Interrupts
124 ----------
125
126 The ULA generates IRQs (maskable interrupts) according to certain conditions
127 and these conditions are controlled by location &FE00:
128
129 * Vertical sync (bottom of displayed screen)
130 * 50MHz real time clock
131 * Transmit data empty
132 * Receive data full
133 * High tone detect
134
135 The ULA is also used to clear interrupt conditions through location &FE05. Of
136 particular significance is bit 7, which must be set if an NMI (non-maskable
137 interrupt) has occurred and has thus suspended ULA access to memory, restoring
138 the normal function of the ULA.
139
140 ROM Paging
141 ----------
142
143 Accessing different ROMs involves bits 0 to 3 of &FE05. Some special ROM
144 mappings exist:
145
146 8 keyboard
147 9 keyboard (duplicate)
148 10 BASIC ROM
149 11 BASIC ROM (duplicate)
150
151 Paging in a ROM involves the following procedure:
152
153 1. Assert ROM page enable (bit 3) together with a ROM number n in bits 0 to
154 2, corresponding to ROM number 8+n, such that one of ROMs 12 to 15 is
155 selected.
156 2. Where a ROM numbered from 0 to 7 is to be selected, set bit 3 to zero
157 whilst writing the desired ROM number n in bits 0 to 2.
158
159 Shadow/Expanded Memory
160 ----------------------
161
162 The Electron exposes all sixteen address lines and all eight data lines
163 through the expansion bus. Using such lines, it is possible to provide
164 additional memory - typically sideways ROM and RAM - on expansion cards and
165 through cartridges, although the official cartridge specification provides
166 fewer address lines and only seeks to provide access to memory in 16K units.
167
168 Various modifications and upgrades were developed to offer "turbo"
169 capabilities to the Electron, permitting the CPU to access a separate 8K of
170 RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
171 the ULA through additional logic. However, an enhanced ULA might support
172 independent CPU access to memory over the expansion bus by allowing itself to
173 be discharged from providing access to memory, potentially for a range of
174 addresses, and for the CPU to communicate with external memory uninterrupted.
175
176 Hardware Scrolling
177 ------------------
178
179 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
180 the least significant 5 bits being zero, thus limiting the scrolling
181 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
182 using the same layout of these addresses.
183
184 |--&FE02--------------| |--&FE03--------------|
185 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
186
187 XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
188
189 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
190 memory to pixel locations is character oriented. A change in 8 bytes would
191 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
192 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
193 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
194 Guide).
195
196 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
197 of changing the screen address by 2 bytes is the change in the number of lines
198 from the initial and final character rows that need reading by the ULA, which
199 would need to maintain this state information (although this is a relatively
200 trivial change). Another pitfall is the complication that might be introduced
201 to software writing bitmaps of character height to the screen.
202
203 Region Blanking
204 ---------------
205
206 The problem of permitting character-oriented blitting in programs whilst
207 scrolling the screen by sub-character amounts could be mitigated by permitting
208 a region of the display to be blank, such as the final lines of the display.
209 Consider the following vertical scrolling by 2 bytes that would cause an
210 initial character row of 6 lines and a final character row of 2 lines:
211
212 6 lines - initial, partial character row
213 248 lines - 31 complete rows
214 2 lines - final, partial character row
215
216 If a routine were in use that wrote 8 line bitmaps to the partial character
217 row now split in two, it would be advisable to hide one of the regions in
218 order to prevent content appearing in the wrong place on screen (such as
219 content meant to appear at the top "leaking" onto the bottom). Blanking 6
220 lines would be sufficient, as can be seen from the following cases.
221
222 Scrolling up by 2 lines:
223
224 6 lines - initial, partial character row
225 240 lines - 30 complete rows
226 4 lines - part of 1 complete row
227 -----------------------------------------------------------------
228 4 lines - part of 1 complete row (hidden to maintain 250 lines)
229 2 lines - final, partial character row (hidden)
230
231 Scrolling down by 2 lines:
232
233 2 lines - initial, partial character row
234 248 lines - 31 complete rows
235 ----------------------------------------------------------
236 6 lines - final, partial character row (hidden)
237
238 Thus, in this case, region blanking would impose a 250 line display with the
239 bottom 6 lines blank.
240
241 Screen Height Adjustment
242 ------------------------
243
244 The height of the screen could be configurable in order to reduce screen
245 memory consumption. This is not quite done in MODE 3 and 6 since the start of
246 the screen appears to be rounded down to the nearest page, but by reducing the
247 height by amounts more than a page, savings would be possible. For example:
248
249 Screen width Depth Height Bytes per line Saving in bytes Start address
250 ------------ ----- ------ -------------- --------------- -------------
251 640 1 252 80 320 &3140 -> &3100
252 640 1 248 80 640 &3280 -> &3200
253 320 1 240 40 640 &5A80 -> &5A00
254 320 2 240 80 1280 &3500
255
256 Palette Definition
257 ------------------
258
259 Since all memory accesses go via the ULA, an enhanced ULA could employ more
260 specific addresses than &FE*X to perform enhanced functions. For example, the
261 palette control is done using &FE*8-F and merely involves selecting predefined
262 colours, whereas an enhanced ULA could support the redefinition of all 16
263 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
264 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
265 specifications similar to those used on the Archimedes.
266
267 The principal limitation here is actually the hardware: the Electron has only
268 a single output line for each of the red, green and blue channels, and if
269 those outputs are strictly digital and can only be set to a "high" and "low"
270 value, then only the existing eight colours are possible. If a modern ULA were
271 able to output analogue values, it would still need to be assessed whether the
272 circuitry could successfully handle and propagate such values.
273
274 Palette Definition Lists
275 ------------------------
276
277 It can be useful to redefine the palette in order to change the colours
278 available for a particular region of the screen, particularly in modes where
279 the choice of colours is constrained, and if an increased colour depth were
280 available, palette redefinition would be useful to give the illusion of more
281 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
282 by using interrupt-driven timers, but a more efficient approach would involve
283 presenting lists of palette definitions to the ULA so that it can change the
284 palette at a particular display line.
285
286 One might define a palette redefinition list in a region of memory and then
287 communicate its contents to the ULA by writing the address and length of the
288 list, along with the display line at which the palette is to be changed, to
289 ULA registers such that the ULA buffers the list and performs the redefinition
290 at the appropriate time. Throughput/bandwidth considerations might impose
291 restrictions on the practical length of such a list, however.
292
293 Palette-Free Modes
294 ------------------
295
296 Palette-free modes might be defined where bit values directly correspond to
297 the red, green and blue channels, although this would mostly make sense only
298 for modes with depths greater than the standard 4 bits per pixel, and such
299 modes would require more memory than MODE 2 if they were to have an acceptable
300 resolution.
301
302 Display Suspend
303 ---------------
304
305 Especially when writing to the screen memory, it could be beneficial to be
306 able to suspend the ULA's access to the memory, instead producing blank values
307 for all screen pixels until a program is ready to reveal the screen. This is
308 different from palette blanking since with a blank palette, the ULA is still
309 reading screen memory and translating its contents into pixel values that end
310 up being blank.
311
312 This function is reminiscent of a capability of the ZX81, albeit necessary on
313 that hardware to reduce the load on the system CPU which was responsible for
314 producing the video output.
315
316 Hardware Sprites
317 ----------------
318
319 An enhanced ULA might provide hardware sprites, but this would be done in an
320 way that is incompatible with the standard ULA, since no &FE*X locations are
321 available for allocation. To keep the facility simple, hardware sprites would
322 have a standard byte width and height.
323
324 The specification of sprites could involve the reservation of 16 locations
325 (for example, &FE20-F) specifying a fixed number of eight sprites, with each
326 location pair referring to the sprite data. By limiting the ULA to dealing
327 with a fixed number of sprites, the work required inside the ULA would be
328 reduced since it would avoid having to deal with arbitrary numbers of sprites.
329
330 The principal limitation on providing hardware sprites is that of having to
331 obtain sprite data, given that the ULA is usually required to retrieve screen
332 data, and given the lack of memory bandwidth available to retrieve sprite data
333 (particularly from multiple sprites supposedly at the same position) and
334 screen data simultaneously. Although the ULA could potentially read sprite
335 data and screen data in alternate memory accesses in screen modes where the
336 bandwidth is not already fully utilised, this would result in a degradation of
337 performance.
338
339 Additional Screen Mode Configurations
340 -------------------------------------
341
342 Alternative screen mode configurations could be supported. The ULA has to
343 produce 640 pixel values across the screen, with pixel doubling or quadrupling
344 employed to fill the screen width:
345
346 Screen width Columns Scaling Depth Bytes
347 ------------ ------- ------- ----- -----
348 640 80 x1 1 80
349 320 40 x2 1, 2 40, 80
350 160 20 x4 2, 4 40, 80
351
352 It must also use at most 80 byte-sized memory accesses to provide the
353 information for the display. Given that characters must occupy an 8x8 pixel
354 array, if a configuration featuring anything other than 20, 40 or 80 character
355 columns is to be supported, compromises must be made such as the introduction
356 of blank pixels either between characters (such as occurs between rows in MODE
357 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
358 in MODE 3 and 6). Consider the following configuration:
359
360 Screen width Columns Scaling Depth Bytes Blank
361 ------------ ------- ------- ----- ------ -----
362 208 26 x3 1, 2 26, 52 16
363
364 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
365 colours could be provided, with 16 blank pixel values (out of a total of 640)
366 generated either at the start or end (or split between the start and end) of
367 each scanline.
368
369 Character Attributes
370 --------------------
371
372 The BBC Micro MODE 7 employs something resembling character attributes to
373 support teletext displays, but depends on circuitry providing a character
374 generator. The ZX Spectrum, on the other hand, provides character attributes
375 as a means of colouring bitmapped graphics. Although such a feature is very
376 limiting as the sole means of providing multicolour graphics, in situations
377 where the choice is between low resolution multicolour graphics or high
378 resolution monochrome graphics, character attributes provide a potentially
379 useful compromise.
380
381 For each byte read, the ULA must deliver 8 pixel values (out of a total of
382 640) to the video output, doing so by either emptying its pixel buffer on a
383 pixel per cycle basis, or by multiplying pixels and thus holding them for more
384 than one cycle. For example for a screen mode having 640 pixels in width:
385
386 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
387 Reads: B B
388 Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
389
390 And for a screen mode having 320 pixels in width:
391
392 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
393 Reads: B
394 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
395
396 However, in modes where less than 80 bytes are required to generate the pixel
397 values, an enhanced ULA might be able to read additional bytes between those
398 providing the bitmapped graphics data:
399
400 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
401 Reads: B A
402 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
403
404 These additional bytes could provide colour information for the bitmapped data
405 in the following character column (of 8 pixels). Since it would be desirable
406 to apply attribute data to the first column, the initial 8 cycles might be
407 configured to not produce pixel values.
408
409 For an entire character, attribute data need only be read for the first row of
410 pixels for a character. The subsequent rows would have attribute information
411 applied to them, although this would require the attribute data to be stored
412 in some kind of buffer. Thus, the following access pattern would be observed:
413
414 Cycle: A B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ...
415
416 A whole byte used for colour information for a whole character would result in
417 a choice of 256 colours, and this might be somewhat excessive. By only reading
418 attribute bytes at every other opportunity, a choice of 16 colours could be
419 applied individually to two characters.
420
421 Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
422 Reads: B A B -
423 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
424
425 Further reductions in attribute data access, offering 4 colours for every
426 character in a four character block, for example, might also be worth
427 considering.
428
429 Consider the following configurations for screen modes with a colour depth of
430 1 bit per pixel for bitmap information:
431
432 Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
433 ------------ ------- ------- --------- --------- ------- ------------
434 320 40 x2 40 40 256 &5300
435 320 40 x2 40 20 16 &5580 -> &5500
436 320 40 x2 40 10 4 &56C0 -> &5600
437 208 26 x3 26 26 256 &62C0 -> &6200
438 208 26 x3 26 13 16 &6460 -> &6400
439
440 MODE 7 Emulation using Character Attributes
441 -------------------------------------------
442
443 If the scheme of applying attributes to character regions were employed to
444 emulate MODE 7, in conjunction with the MODE 6 display technique, the
445 following configuration would be required:
446
447 Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
448 ------------ ------- ---- --------- --------- ------- ------------
449 320 40 25 40 20 16 &5ECC -> &5E00
450 320 40 25 40 10 4 &5FC6 -> &5F00
451
452 Although this requires much more memory than MODE 7 (8500 bytes versus MODE
453 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
454 at least make a limited 40-column multicolour mode available as a substitute
455 for MODE 7.
456
457 Enhanced Graphics and Mode Layouts
458 ----------------------------------
459
460 Screen modes with different screen memory mappings, higher resolutions and
461 larger colour depths might be possible, but this would in most cases involve
462 the allocation of more screen memory, and the ULA would probably then be
463 obliged to page in such memory for the CPU to be able to sensibly access it
464 all. Merely changing the memory mappings in order to have Archimedes-style
465 row-oriented screen addresses (instead of character-oriented addresses) could
466 be done for the existing modes, but this might not be sufficiently beneficial,
467 especially since accessing regions of the screen would involve incrementing
468 pointers by amounts that are inconvenient on an 8-bit CPU.
469
470 Enhanced Sound
471 --------------
472
473 The standard ULA reserves &FE*6 for sound generation and cassette
474 input/output, thus making it impossible to support multiple channels within
475 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
476 and an enhanced ULA could adopt this interface.
477
478 The BBC Micro uses the SN76489 chip to produce sound, and the entire
479 functionality of this chip could be emulated for enhanced sound, with a subset
480 of the functionality exposed via the &FE*6 interface.
481
482 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
483
484 Waveform Upload
485 ---------------
486
487 As with a hardware sprite function, waveforms could be uploaded or referenced
488 using locations as registers referencing memory regions.
489
490 BBC ULA Compatibility
491 ---------------------
492
493 Although some new ULA functions could be defined in a way that is also
494 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
495 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
496 map, but controls various functions specific to the 6845 video controller;
497 &FE08-F is reserved for the serial controller. It therefore becomes possible
498 to disregard compatibility where compatibility is already disregarded for a
499 particular area of functionality.
500
501 &FE20-F maps to video ULA functionality on the BBC Micro which provides
502 control over the palette (using address &FE21, compared to &FE07-F on the
503 Electron) and other system-specific functions. Since the location usage is
504 generally incompatible, this region could be reused for other purposes.
505
506 ULA Pin Functions
507 -----------------
508
509 The functions of the ULA pins are described in the Electron Service Manual. Of
510 interest to video processing are the following:
511
512 CSYNC (low during horizontal or vertical synchronisation periods, high
513 otherwise)
514
515 HS (low during horizontal synchronisation periods, high otherwise)
516
517 RED, GREEN, BLUE (pixel colour outputs)
518
519 CLOCK IN (a 16MHz clock input, 4V peak to peak)
520
521 PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
522
523 More general memory access pins:
524
525 RAM0...RAM3 (data lines to/from the RAM)
526
527 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
528
529 RAS (row address strobe setting the row address on a negative edge - see the
530 timing notes)
531
532 CAS (column address strobe setting the column address on a negative edge -
533 see the timing notes)
534
535 WE (sets write enable with logic 0, read with logic 1)
536
537 ROM (select data access from ROM)
538
539 CPU-oriented memory access pins:
540
541 A0...A15 (CPU address lines)
542
543 PD0...PD7 (CPU data lines)
544
545 R/W (indicates CPU write with logic 0, CPU read with logic 1)
546
547 Interrupt-related pins:
548
549 NMI (CPU request for uninterrupted 1MHz access to memory)
550
551 IRQ (signal event to CPU)
552
553 POR (power-on reset, resetting the ULA on a positive edge and asserting the
554 CPU's RST pin)
555
556 RST (master reset for the CPU signalled on power-up and by the Break key)
557
558 Keyboard-related pins:
559
560 KBD0...KBD3 (keyboard inputs)
561
562 CAPS LOCK (control status LED)
563
564 Sound-related pins:
565
566 SOUND O/P (sound output using internal oscillator)
567
568 Cassette-related pins:
569
570 CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
571
572 CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
573
574 CAS RC (detect high tone)
575
576 CAS MO (motor relay output)
577
578 ÷13 IN (~1200 baud clock input)