1 Timing
2 ------
3
4 According to the above (15.3.2 in the AUG), there are 312 scanlines, 256 of
5 which are used to generate pixel data. At 50Hz, this means that 128 cycles are
6 used to produce pixel data (2000000 / 50 = 40000; 40000 / 312 ~= 128). This is
7 consistent with the observation that each scanline requires at most 80 bytes
8 of data, and that the ULA is apparently busy for 40 out of 64 microseconds in
9 each scanline.
10
11 See: Acorn Electron Advanced User Guide
12 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
13
14 Hardware Scrolling
15 ------------------
16
17 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
18 the least significant 5 bits being zero, thus limiting the scrolling
19 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
20 using the same layout of these addresses.
21
22 |--&FE02--------------| |--&FE03--------------|
23 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
24
25 XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
26
27 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
28 memory to pixel locations is character oriented. A change in 8 bytes would
29 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
30 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
31 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
32 Guide).
33
34 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
35 of changing the screen address by 2 bytes is the change in the number of lines
36 from the initial and final character rows that need reading by the ULA, which
37 would need to maintain this state information (although this is a relatively
38 trivial change). Another pitfall is the complication that might be introduced
39 to software writing bitmaps of character height to the screen.
40
41 Region Blanking
42 ---------------
43
44 The problem of permitting character-oriented blitting in programs whilst
45 scrolling the screen by sub-character amounts could be mitigated by permitting
46 a region of the display to be blank, such as the final lines of the display.
47 Consider the following vertical scrolling by 2 bytes that would cause an
48 initial character row of 6 lines and a final character row of 2 lines:
49
50 6 lines - initial, partial character row
51 248 lines - 31 complete rows
52 2 lines - final, partial character row
53
54 If a routine were in use that wrote 8 line bitmaps to the partial character
55 row now split in two, it would be advisable to hide one of the regions in
56 order to prevent content appearing in the wrong place on screen (such as
57 content meant to appear at the top "leaking" onto the bottom). Blanking 6
58 lines would be sufficient, as can be seen from the following cases.
59
60 Scrolling up by 2 lines:
61
62 6 lines - initial, partial character row
63 240 lines - 30 complete rows
64 4 lines - part of 1 complete row
65 -----------------------------------------------------------------
66 4 lines - part of 1 complete row (hidden to maintain 250 lines)
67 2 lines - final, partial character row (hidden)
68
69 Scrolling down by 2 lines:
70
71 2 lines - initial, partial character row
72 248 lines - 31 complete rows
73 ----------------------------------------------------------
74 6 lines - final, partial character row (hidden)
75
76 Thus, in this case, region blanking would impose a 250 line display with the
77 bottom 6 lines blank.
78
79 Screen Height Adjustment
80 ------------------------
81
82 The height of the screen could be configurable in order to reduce screen
83 memory consumption. This is not quite done in MODE 3 and 6 since the start of
84 the screen appears to be rounded down to the nearest page, but by reducing the
85 height by amounts more than a page, savings would be possible. For example:
86
87 Screen width Depth Height Bytes per line Saving in bytes Start address
88 ------------ ----- ------ -------------- --------------- -------------
89 640 1 252 80 320 &3140 -> &3100
90 640 1 248 80 640 &3280 -> &3200
91 320 1 240 40 640 &5A80 -> &5A00
92 320 2 240 80 1280 &3500
93
94 Palette Definition
95 ------------------
96
97 Since all memory accesses go via the ULA, an enhanced ULA could employ more
98 specific addresses than &FE*X to perform enhanced functions. For example, the
99 palette control is done using &FE*8-F and merely involves selecting predefined
100 colours, whereas an enhanced ULA could support the redefinition of all 16
101 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
102 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
103 specifications similar to those used on the Archimedes.
104
105 The principal limitation here is actually the hardware: the Electron has only
106 a single output line for each of the red, green and blue channels, and if
107 those outputs are strictly digital and can only be set to a "high" and "low"
108 value, then only the existing eight colours are possible. If a modern ULA were
109 able to output analogue values, it would still need to be assessed whether the
110 circuitry could successfully handle and propagate such values.
111
112 Palette Definition Lists
113 ------------------------
114
115 It can be useful to redefine the palette in order to change the colours
116 available for a particular region of the screen, particularly in modes where
117 the choice of colours is constrained, and if an increased colour depth were
118 available, palette redefinition would be useful to give the illusion of more
119 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
120 by using interrupt-driven timers, but a more efficient approach would involve
121 presenting lists of palette definitions to the ULA so that it can change the
122 palette at a particular display line.
123
124 One might define a palette redefinition list in a region of memory and then
125 communicate its contents to the ULA by writing the address and length of the
126 list, along with the display line at which the palette is to be changed, to
127 ULA registers such that the ULA buffers the list and performs the redefinition
128 at the appropriate time. Throughput/bandwidth considerations might impose
129 restrictions on the practical length of such a list, however.
130
131 Palette-Free Modes
132 ------------------
133
134 Palette-free modes might be defined where bit values directly correspond to
135 the red, green and blue channels, although this would mostly make sense only
136 for modes with depths greater than the standard 4 bits per pixel, and such
137 modes would require more memory than MODE 2 if they were to have an acceptable
138 resolution.
139
140 Display Suspend
141 ---------------
142
143 Especially when writing to the screen memory, it could be beneficial to be
144 able to suspend the ULA's access to the memory, instead producing blank values
145 for all screen pixels until a program is ready to reveal the screen. This is
146 different from palette blanking since with a blank palette, the ULA is still
147 reading screen memory and translating its contents into pixel values that end
148 up being blank.
149
150 This function is reminiscent of a capability of the ZX81, albeit necessary on
151 that hardware to reduce the load on the system CPU which was responsible for
152 producing the video output.
153
154 Hardware Sprites and Colour Planes
155 ----------------------------------
156
157 An enhanced ULA might provide hardware sprites, but this would be done in an
158 way that is incompatible with the standard ULA, since no &FE*X locations are
159 available for allocation. In a special ULA mode, one might allocate a pair of
160 locations (for example, &FE20 and &FE21) as a pair of registers referencing a
161 region of memory from which a sprite might be found and potentially copied
162 into internal RAM, with other locations (for example, &FE22 and &FE23)
163 providing the size of the region. Alternatively, one might write the region
164 location and size through a single ULA location, with the ULA being put into a
165 particular state after each write. For example: read LSB of region, read MSB
166 of region, read size, read height.
167
168 Providing hardware sprites can be awkward without having some kind of working
169 area, since the ULA would need to remember where each sprite is to be plotted
170 and then deduce which sprites would be contributing to any given pixel. An
171 alternative is to use memory into which the sprites would be plotted, and this
172 memory would be combined with the main screen memory, taking a particular
173 colour as the "colourkey" which is to be considered transparent, and only
174 overwriting the main screen pixels with pixel values for other colours.
175
176 Additional Screen Mode Configurations
177 -------------------------------------
178
179 Alternative screen mode configurations could be supported. The ULA has to
180 produce 640 pixel values across the screen, with pixel doubling or quadrupling
181 employed to fill the screen width:
182
183 Screen width Columns Scaling Depth Bytes
184 ------------ ------- ------- ----- -----
185 640 80 x1 1 80
186 320 40 x2 1, 2 40, 80
187 160 20 x4 2, 4 40, 80
188
189 It must also use at most 80 byte-sized memory accesses to provide the
190 information for the display. Given that characters must occupy an 8x8 pixel
191 array, if a configuration featuring anything other than 20, 40 or 80 character
192 columns is to be supported, compromises must be made such as the introduction
193 of blank pixels either between characters (such as occurs between rows in MODE
194 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
195 in MODE 3 and 6). Consider the following configuration:
196
197 Screen width Columns Scaling Depth Bytes Blank
198 ------------ ------- ------- ----- ------ -----
199 208 26 x3 1, 2 26, 52 16
200
201 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
202 colours could be provided, with 16 blank pixel values (out of a total of 640)
203 generated either at the start or end (or split between the start and end) of
204 each scanline.
205
206 Character Attributes
207 --------------------
208
209 The BBC Micro MODE 7 employs something resembling character attributes to
210 support teletext displays, but depends on circuitry providing a character
211 generator. The ZX Spectrum, on the other hand, provides character attributes
212 as a means of colouring bitmapped graphics. Although such a feature is very
213 limiting as the sole means of providing multicolour graphics, in situations
214 where the choice is between low resolution multicolour graphics or high
215 resolution monochrome graphics, character attributes provide a potentially
216 useful compromise.
217
218 For each byte read, the ULA must deliver 8 pixel values (out of a total of
219 640) to the video output, doing so by either emptying its pixel buffer on a
220 pixel per cycle basis, or by multiplying pixels and thus holding them for more
221 than one cycle. For example for a screen mode having 640 pixels in width:
222
223 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
224 Reads: B B
225 Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
226
227 And for a screen mode having 320 pixels in width:
228
229 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
230 Reads: B
231 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
232
233 However, in modes where less than 80 bytes are required to generate the pixel
234 values, an enhanced ULA might be able to read additional bytes between those
235 providing the bitmapped graphics data:
236
237 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
238 Reads: B A
239 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
240
241 These additional bytes could provide colour information for the bitmapped data
242 in the following character column (of 8 pixels). Since it would be desirable
243 to apply attribute data to the first column, the initial 8 cycles might be
244 configured to not produce pixel values.
245
246 A whole byte used for colour information for a whole character would result in
247 a choice of 256 colours, and this might be somewhat excessive. By only reading
248 attribute bytes at every other opportunity, a choice of 16 colours could be
249 applied individually to two characters.
250
251 Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
252 Reads: B A B -
253 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
254
255 Consider the following configurations for screen modes with a colour depth of
256 1 bit per pixel for bitmap information:
257
258 Screen width Columns Scaling Bytes (B) Bytes (A) Colours
259 ------------ ------- ------- --------- --------- -------
260 320 40 x2 40 40 256
261 320 40 x2 40 20 16
262 208 26 x3 26 26 256
263 208 26 x3 26 13 16
264
265 Here, a mode resembling MODE 4 would occupy the same amount of space as MODE 1
266 if 40 attribute (A) bytes were read in addition to the 40 bitmap (B) bytes.
267 This would offer limited benefit over the mode with the higher colour depth,
268 especially if palette definition lists were also available. However, if only
269 20 attribute bytes were read, the screen memory would be only 150% of the
270 original.
271
272 Similarly, if an additional configuration pixel-tripled mode were to require
273 as many attribute bytes as bitmap bytes, it would occupy as much space as its
274 equivalent with twice the colour depth. However, by requiring only 13
275 attribute bytes for every 26 bitmap bytes, it would actually be more efficient
276 than MODE 6 (a screen start address of &6600 versus MODE 6's &6000).
277
278 MODE 7 Emulation
279 ----------------
280
281 If the scheme of applying attributes to character regions were employed to
282 emulate MODE 7, in conjunction with the MODE 6 display technique, the
283 following configuration would be required:
284
285 Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
286 ------------ ------- ---- --------- --------- ------- ------------
287 320 40 25 40 20 16 &5120 -> &5100
288
289 Although this requires much more memory than MODE 7 (12000 bytes versus
290 MODE 7's 1000 bytes) and more memory than even MODE 6, it would at least make
291 a limited 40-column multicolour mode available as a substitute for MODE 7.
292
293 Enhanced Graphics and Mode Layouts
294 ----------------------------------
295
296 Screen modes with different screen memory mappings, higher resolutions and
297 larger colour depths might be possible, but this would in most cases involve
298 the allocation of more screen memory, and the ULA would probably then be
299 obliged to page in such memory for the CPU to be able to sensibly access it
300 all. Merely changing the memory mappings in order to have Archimedes-style
301 row-oriented screen addresses (instead of character-oriented addresses) could
302 be done for the existing modes, but this might not be sufficiently beneficial,
303 especially since accessing regions of the screen would involve incrementing
304 pointers by amounts that are inconvenient on an 8-bit CPU.
305
306 Enhanced Sound
307 --------------
308
309 The standard ULA reserves &FE*6 for sound generation and cassette
310 input/output, thus making it impossible to support multiple channels within
311 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
312 and an enhanced ULA could adopt this interface.
313
314 The BBC Micro uses the SN76489 chip to produce sound, and the entire
315 functionality of this chip could be emulated for enhanced sound, with a subset
316 of the functionality exposed via the &FE*6 interface.
317
318 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
319
320 Waveform Upload
321 ---------------
322
323 As with a hardware sprite function, waveforms could be uploaded or referenced
324 using locations as registers referencing memory regions.
325
326 BBC ULA Compatibility
327 ---------------------
328
329 Although some new ULA functions could be defined in a way that is also
330 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
331 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
332 map, but controls various functions specific to the 6845 video controller;
333 &FE08-F is reserved for the serial controller. It therefore becomes possible
334 to disregard compatibility where compatibility is already disregarded for a
335 particular area of functionality.
336
337 &FE20-F maps to video ULA functionality on the BBC Micro which provides
338 control over the palette (using address &FE21, compared to &FE07-F on the
339 Electron) and other system-specific functions. Since the location usage is
340 generally incompatible, this region could be reused for other purposes.
341
342 ULA Pin Functions
343 -----------------
344
345 The functions of the ULA pins are described in the Electron Service Manual. Of
346 interest to video processing are the following:
347
348 CSYNC (low during horizontal or vertical synchronisation periods, high
349 otherwise)
350
351 HS (low during horizontal synchronisation periods, high otherwise)
352
353 RED, GREEN, BLUE (pixel colour outputs)
354
355 CLOCK IN (a 16MHz clock input, 4V peak to peak)
356
357 PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
358
359 More general memory access pins:
360
361 RAM0...RAM3 (data lines to/from the RAM)
362
363 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
364
365 RAS (row address strobe setting the row address on a negative edge)
366
367 CAS (column address strobe setting the column address on a negative edge)
368
369 WE (sets write enable with logic 0, read with logic 1)
370
371 ROM (select data access from ROM)
372
373 CPU-oriented memory access pins:
374
375 A0...A15 (CPU address lines)
376
377 PD0...PD7 (CPU data lines)
378
379 R/W (indicates CPU write with logic 0, CPU read with logic 1)
380
381 Interrupt-related pins:
382
383 NMI (CPU request for uninterrupted 1MHz access to memory)
384
385 IRQ (signal event to CPU)
386
387 POR (power-on reset, resetting the ULA on a positive edge and asserting the
388 CPU's RST pin)
389
390 RST (master reset for the CPU signalled on power-up and by the Break key)
391
392 Keyboard-related pins:
393
394 KBD0...KBD3 (keyboard inputs)
395
396 CAPS LOCK (control status LED)
397
398 Sound-related pins:
399
400 SOUND O/P (sound output using internal oscillator)
401
402 Cassette-related pins:
403
404 CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
405
406 CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
407
408 CAS RC (detect high tone)
409
410 CAS MO (motor relay output)
411
412 ÷13 IN (~1200 baud clock input)